• Leo Yan's avatar
    coresight: add support for CPU debug module · 2227b7c7
    Leo Yan authored
    Coresight includes debug module and usually the module connects with CPU
    debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
    description for related info in "Part H: External Debug".
    
    Chapter H7 "The Sample-based Profiling Extension" introduces several
    sampling registers, e.g. we can check program counter value with
    combined CPU exception level, secure state, etc. So this is helpful for
    analysis CPU lockup scenarios, e.g. if one CPU has run into infinite
    loop with IRQ disabled. In this case the CPU cannot switch context and
    handle any interrupt (including IPIs), as the result it cannot handle
    SMP call for stack dump.
    
    This patch is to enable coresight debug module, so firstly this driver
    is to bind apb clock for debug module and this is to ensure the debug
    module can be accessed from program or external debugger. And the driver
    uses sample-based registers for debug purpose, e.g. when system triggers
    panic, the driver will dump program counter and combined context
    registers (EDCIDSR, EDVIDSR); by parsing context registers so can
    quickly get to know CPU secure state, exception level, etc.
    
    Some of the debug module registers are located in CPU power domain, so
    this requires the CPU power domain stays on when access related debug
    registers, but the power management for CPU power domain is quite
    dependent on SoC integration for power management. For the platforms
    which with sane power controller implementations, this driver follows
    the method to set EDPRCR to try to pull the CPU out of low power state
    and then set 'no power down request' bit so the CPU has no chance to
    lose power.
    
    If the SoC has not followed up this design well for power management
    controller, the user should use the command line parameter or sysfs
    to constrain all or partial idle states to ensure the CPU power
    domain is enabled and access coresight CPU debug component safely.
    Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
    Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
    Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
    Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
    2227b7c7
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