• Palmer Dabbelt's avatar
    RISC-V: `sfence.vma` orderes the instruction cache · c901e45a
    Palmer Dabbelt authored
    This is just a comment change, but it's one that bit me on the mailing
    list.  It turns out that issuing a `sfence.vma` enforces instruction
    cache ordering in addition to TLB ordering.  This isn't explicitly
    called out in the ISA manual, but Andrew will be making that more clear
    in a future revision.
    
    CC: Andrew Waterman <andrew@sifive.com>
    Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
    c901e45a
tlbflush.h 1.84 KB