• Martin Blumenstingl's avatar
    mtd: nand: hynix: add support for 20nm NAND chips · fd213b5b
    Martin Blumenstingl authored
    According to the datasheet of the H27UCG8T2BTR the NAND Technology field
    (6th byte of the "Device Identifier Description", bits 0-2) the
    following values are possible:
    - 0x0 = 48nm
    - 0x1 = 41nm
    - 0x2 = 32nm
    - 0x3 = 26nm
    - 0x4 = 20nm
    - (all others are reserved)
    
    Fix this by extending the mask for this field to allow detecting value
    0x4 (20nm) as valid NAND technology.
    Without this the detection of the ECC requirements fails, because the
    code assumes that the device is a 48nm device (0x4 & 0x3 = 0x0) and
    aborts with "Invalid ECC requirements" because it cannot map the "ECC
    Level". Extending the mask makes the ECC requirement detection code
    recognize this chip as <= 26nm and sets up the ECC step size and ECC
    strength correctly.
    Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
    Fixes: 78f3482d ("mtd: nand: hynix: Rework NAND ID decoding to extract more information")
    Cc: <stable@vger.kernel.org>
    Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
    fd213b5b
nand_hynix.c 15.1 KB