Commit 000f64ef authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab

V4L/DVB: Fix bad whitespacing

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 6721b51e
...@@ -125,12 +125,12 @@ static const struct stb0899_s1_reg az6027_stb0899_s1_init_3[] = { ...@@ -125,12 +125,12 @@ static const struct stb0899_s1_reg az6027_stb0899_s1_init_3[] = {
{ STB0899_RCOMPC , 0xc9 }, { STB0899_RCOMPC , 0xc9 },
{ STB0899_AGC1CN , 0x01 }, { STB0899_AGC1CN , 0x01 },
{ STB0899_AGC1REF , 0x10 }, { STB0899_AGC1REF , 0x10 },
{ STB0899_RTC , 0x23 }, { STB0899_RTC , 0x23 },
{ STB0899_TMGCFG , 0x4e }, { STB0899_TMGCFG , 0x4e },
{ STB0899_AGC2REF , 0x34 }, { STB0899_AGC2REF , 0x34 },
{ STB0899_TLSR , 0x84 }, { STB0899_TLSR , 0x84 },
{ STB0899_CFD , 0xf7 }, { STB0899_CFD , 0xf7 },
{ STB0899_ACLC , 0x87 }, { STB0899_ACLC , 0x87 },
{ STB0899_BCLC , 0x94 }, { STB0899_BCLC , 0x94 },
{ STB0899_EQON , 0x41 }, { STB0899_EQON , 0x41 },
{ STB0899_LDT , 0xf1 }, { STB0899_LDT , 0xf1 },
...@@ -183,10 +183,10 @@ static const struct stb0899_s1_reg az6027_stb0899_s1_init_3[] = { ...@@ -183,10 +183,10 @@ static const struct stb0899_s1_reg az6027_stb0899_s1_init_3[] = {
{ STB0899_ECNT3M , 0x0a }, { STB0899_ECNT3M , 0x0a },
{ STB0899_ECNT3L , 0xad }, { STB0899_ECNT3L , 0xad },
{ STB0899_FECAUTO1 , 0x06 }, { STB0899_FECAUTO1 , 0x06 },
{ STB0899_FECM , 0x01 }, { STB0899_FECM , 0x01 },
{ STB0899_VTH12 , 0xb0 }, { STB0899_VTH12 , 0xb0 },
{ STB0899_VTH23 , 0x7a }, { STB0899_VTH23 , 0x7a },
{ STB0899_VTH34 , 0x58 }, { STB0899_VTH34 , 0x58 },
{ STB0899_VTH56 , 0x38 }, { STB0899_VTH56 , 0x38 },
{ STB0899_VTH67 , 0x34 }, { STB0899_VTH67 , 0x34 },
{ STB0899_VTH78 , 0x24 }, { STB0899_VTH78 , 0x24 },
...@@ -195,7 +195,7 @@ static const struct stb0899_s1_reg az6027_stb0899_s1_init_3[] = { ...@@ -195,7 +195,7 @@ static const struct stb0899_s1_reg az6027_stb0899_s1_init_3[] = {
{ STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */ { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
{ STB0899_TSULC , 0x42 }, { STB0899_TSULC , 0x42 },
{ STB0899_RSLLC , 0x41 }, { STB0899_RSLLC , 0x41 },
{ STB0899_TSLPL , 0x12 }, { STB0899_TSLPL , 0x12 },
{ STB0899_TSCFGH , 0x0c }, { STB0899_TSCFGH , 0x0c },
{ STB0899_TSCFGM , 0x00 }, { STB0899_TSCFGM , 0x00 },
{ STB0899_TSCFGL , 0x00 }, { STB0899_TSCFGL , 0x00 },
......
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/ */
#ifndef __ATBM8830_PRIV_H #ifndef __ATBM8830_PRIV_H
#define __ATBM8830_PRIV_H #define __ATBM8830_PRIV_H
......
...@@ -136,12 +136,12 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = { ...@@ -136,12 +136,12 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
{ STB0899_RCOMPC , 0xc9 }, { STB0899_RCOMPC , 0xc9 },
{ STB0899_AGC1CN , 0x01 }, { STB0899_AGC1CN , 0x01 },
{ STB0899_AGC1REF , 0x10 }, { STB0899_AGC1REF , 0x10 },
{ STB0899_RTC , 0x23 }, { STB0899_RTC , 0x23 },
{ STB0899_TMGCFG , 0x4e }, { STB0899_TMGCFG , 0x4e },
{ STB0899_AGC2REF , 0x34 }, { STB0899_AGC2REF , 0x34 },
{ STB0899_TLSR , 0x84 }, { STB0899_TLSR , 0x84 },
{ STB0899_CFD , 0xf7 }, { STB0899_CFD , 0xf7 },
{ STB0899_ACLC , 0x87 }, { STB0899_ACLC , 0x87 },
{ STB0899_BCLC , 0x94 }, { STB0899_BCLC , 0x94 },
{ STB0899_EQON , 0x41 }, { STB0899_EQON , 0x41 },
{ STB0899_LDT , 0xf1 }, { STB0899_LDT , 0xf1 },
...@@ -194,10 +194,10 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = { ...@@ -194,10 +194,10 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
{ STB0899_ECNT3M , 0x0a }, { STB0899_ECNT3M , 0x0a },
{ STB0899_ECNT3L , 0xad }, { STB0899_ECNT3L , 0xad },
{ STB0899_FECAUTO1 , 0x06 }, { STB0899_FECAUTO1 , 0x06 },
{ STB0899_FECM , 0x01 }, { STB0899_FECM , 0x01 },
{ STB0899_VTH12 , 0xb0 }, { STB0899_VTH12 , 0xb0 },
{ STB0899_VTH23 , 0x7a }, { STB0899_VTH23 , 0x7a },
{ STB0899_VTH34 , 0x58 }, { STB0899_VTH34 , 0x58 },
{ STB0899_VTH56 , 0x38 }, { STB0899_VTH56 , 0x38 },
{ STB0899_VTH67 , 0x34 }, { STB0899_VTH67 , 0x34 },
{ STB0899_VTH78 , 0x24 }, { STB0899_VTH78 , 0x24 },
...@@ -206,7 +206,7 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = { ...@@ -206,7 +206,7 @@ static const struct stb0899_s1_reg vp1041_stb0899_s1_init_3[] = {
{ STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */ { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
{ STB0899_TSULC , 0x42 }, { STB0899_TSULC , 0x42 },
{ STB0899_RSLLC , 0x41 }, { STB0899_RSLLC , 0x41 },
{ STB0899_TSLPL , 0x12 }, { STB0899_TSLPL , 0x12 },
{ STB0899_TSCFGH , 0x0c }, { STB0899_TSCFGH , 0x0c },
{ STB0899_TSCFGM , 0x00 }, { STB0899_TSCFGM , 0x00 },
{ STB0899_TSCFGL , 0x00 }, { STB0899_TSCFGL , 0x00 },
......
...@@ -158,7 +158,7 @@ ...@@ -158,7 +158,7 @@
/* gain - offset masks */ /* gain - offset masks */
#define GAIN_INTEGER_SHIFT 9 #define GAIN_INTEGER_SHIFT 9
#define OFFSET_MASK 0xFFF #define OFFSET_MASK 0xFFF
#define GAIN_SDRAM_EN_SHIFT 12 #define GAIN_SDRAM_EN_SHIFT 12
#define GAIN_IPIPE_EN_SHIFT 13 #define GAIN_IPIPE_EN_SHIFT 13
#define GAIN_H3A_EN_SHIFT 14 #define GAIN_H3A_EN_SHIFT 14
......
...@@ -709,7 +709,7 @@ static void setexposure(struct gspca_dev *gspca_dev) ...@@ -709,7 +709,7 @@ static void setexposure(struct gspca_dev *gspca_dev)
/* 'val' is one byte and represents half of the exposure value we are /* 'val' is one byte and represents half of the exposure value we are
* going to set into registers, a two bytes value: * going to set into registers, a two bytes value:
* *
* MSB: ((u16) val << 1) >> 8 == val >> 7 * MSB: ((u16) val << 1) >> 8 == val >> 7
* LSB: ((u16) val << 1) & 0xff == val << 1 * LSB: ((u16) val << 1) & 0xff == val << 1
*/ */
......
...@@ -59,9 +59,9 @@ static const struct ov9640_reg ov9640_regs_dflt[] = { ...@@ -59,9 +59,9 @@ static const struct ov9640_reg ov9640_regs_dflt[] = {
* COM12 |= OV9640_COM12_YUV_AVG * COM12 |= OV9640_COM12_YUV_AVG
* *
* for RGB, alter the following registers: * for RGB, alter the following registers:
* COM7 |= OV9640_COM7_RGB * COM7 |= OV9640_COM7_RGB
* COM13 |= OV9640_COM13_RGB_AVG * COM13 |= OV9640_COM13_RGB_AVG
* COM15 |= proper RGB color encoding mode * COM15 |= proper RGB color encoding mode
*/ */
static const struct ov9640_reg ov9640_regs_qqcif[] = { static const struct ov9640_reg ov9640_regs_qqcif[] = {
{ OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) }, { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
......
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