Commit 0028e1e2 authored by Russell King's avatar Russell King

Merge; remove pci_socket.o from export-objs, add sa1100_pcmcia.o

parents d52a86be 9b4e261a
...@@ -123,6 +123,10 @@ endif ...@@ -123,6 +123,10 @@ endif
MACHINE = sa1100 MACHINE = sa1100
endif endif
ifeq ($(CONFIG_ARCH_PXA),y)
MACHINE = pxa
endif
ifeq ($(CONFIG_ARCH_L7200),y) ifeq ($(CONFIG_ARCH_L7200),y)
MACHINE = l7200 MACHINE = l7200
endif endif
......
...@@ -87,6 +87,10 @@ ifeq ($(CONFIG_SA1111),y) ...@@ -87,6 +87,10 @@ ifeq ($(CONFIG_SA1111),y)
endif endif
endif endif
ifeq ($(CONFIG_ARCH_PXA),y)
ZRELADDR = 0xa0008000
endif
ifeq ($(CONFIG_ARCH_ANAKIN),y) ifeq ($(CONFIG_ARCH_ANAKIN),y)
ZRELADDR = 0x20008000 ZRELADDR = 0x20008000
endif endif
......
...@@ -26,6 +26,7 @@ choice 'ARM system type' \ ...@@ -26,6 +26,7 @@ choice 'ARM system type' \
Cirrus-CL-PS7500FE CONFIG_ARCH_CLPS7500 \ Cirrus-CL-PS7500FE CONFIG_ARCH_CLPS7500 \
CLPS711x/EP721x-based CONFIG_ARCH_CLPS711X \ CLPS711x/EP721x-based CONFIG_ARCH_CLPS711X \
Co-EBSA285 CONFIG_ARCH_CO285 \ Co-EBSA285 CONFIG_ARCH_CO285 \
PXA250/210-based CONFIG_ARCH_PXA \
EBSA-110 CONFIG_ARCH_EBSA110 \ EBSA-110 CONFIG_ARCH_EBSA110 \
Epxa10db CONFIG_ARCH_CAMELOT \ Epxa10db CONFIG_ARCH_CAMELOT \
FootBridge CONFIG_ARCH_FOOTBRIDGE \ FootBridge CONFIG_ARCH_FOOTBRIDGE \
...@@ -125,6 +126,16 @@ dep_tristate ' Support for SA11x0 USB character device emulation' CONFIG_SA1100 ...@@ -125,6 +126,16 @@ dep_tristate ' Support for SA11x0 USB character device emulation' CONFIG_SA1100
dep_tristate 'Compaq iPAQ Handheld sleeve support' CONFIG_H3600_SLEEVE $CONFIG_SA1100_H3600 dep_tristate 'Compaq iPAQ Handheld sleeve support' CONFIG_H3600_SLEEVE $CONFIG_SA1100_H3600
endmenu endmenu
mainmenu_option next_comment
comment 'Intel PXA250/210 Implementations'
dep_bool ' Intel DBPXA250 Development Platform' CONFIG_ARCH_LUBBOCK $CONFIG_ARCH_PXA
dep_bool ' Accelent Xscale IDP' CONFIG_ARCH_PXA_IDP $CONFIG_ARCH_PXA
if [ "$CONFIG_ARCH_LUBBOCK" = "y" ]; then
define_bool CONFIG_SA1111 y
fi
endmenu
mainmenu_option next_comment mainmenu_option next_comment
comment 'CLPS711X/EP721X Implementations' comment 'CLPS711X/EP721X Implementations'
dep_bool ' AUTCPU12' CONFIG_ARCH_AUTCPU12 $CONFIG_ARCH_CLPS711X dep_bool ' AUTCPU12' CONFIG_ARCH_AUTCPU12 $CONFIG_ARCH_CLPS711X
...@@ -227,7 +238,9 @@ if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \ ...@@ -227,7 +238,9 @@ if [ "$CONFIG_ARCH_EBSA110" = "y" -o "$CONFIG_FOOTBRIDGE" = "y" -o \
else else
define_bool CONFIG_CPU_32v4 n define_bool CONFIG_CPU_32v4 n
fi fi
if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then if [ "$CONFIG_ARCH_IOP310" = "y" -o \
"$CONFIG_ARCH_ADIFCC" = "y" -o \
"$CONFIG_ARCH_PXA" = "y" ]; then
define_bool CONFIG_CPU_32v5 y define_bool CONFIG_CPU_32v5 y
else else
define_bool CONFIG_CPU_32v5 n define_bool CONFIG_CPU_32v5 n
...@@ -317,7 +330,9 @@ else ...@@ -317,7 +330,9 @@ else
fi fi
# XScale # XScale
if [ "$CONFIG_ARCH_IOP310" = "y" -o "$CONFIG_ARCH_ADIFCC" = "y" ]; then if [ "$CONFIG_ARCH_IOP310" = "y" -o \
"$CONFIG_ARCH_ADIFCC" = "y" -o \
"$CONFIG_ARCH_PXA" = "y" ]; then
define_bool CONFIG_CPU_XSCALE y define_bool CONFIG_CPU_XSCALE y
else else
define_bool CONFIG_CPU_XSCALE n define_bool CONFIG_CPU_XSCALE n
...@@ -467,6 +482,8 @@ if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \ ...@@ -467,6 +482,8 @@ if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \
"$CONFIG_ARCH_SHARK" = "y" -o \ "$CONFIG_ARCH_SHARK" = "y" -o \
"$CONFIG_ARCH_CO285" = "y" -o \ "$CONFIG_ARCH_CO285" = "y" -o \
"$CONFIG_ARCH_SA1100" = "y" -o \ "$CONFIG_ARCH_SA1100" = "y" -o \
"$CONFIG_ARCH_LUBBOCK" = "y" -o \
"$CONFIG_ARCH_PXA_IDP" = "y" -o \
"$CONFIG_ARCH_INTEGRATOR" = "y" -o \ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \
"$CONFIG_ARCH_CDB89712" = "y" -o \ "$CONFIG_ARCH_CDB89712" = "y" -o \
"$CONFIG_ARCH_P720T" = "y" ]; then "$CONFIG_ARCH_P720T" = "y" ]; then
...@@ -477,6 +494,8 @@ if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \ ...@@ -477,6 +494,8 @@ if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \
"$CONFIG_ARCH_SHARK" = "y" -o \ "$CONFIG_ARCH_SHARK" = "y" -o \
"$CONFIG_ARCH_CO285" = "y" -o \ "$CONFIG_ARCH_CO285" = "y" -o \
"$CONFIG_ARCH_SA1100" = "y" -o \ "$CONFIG_ARCH_SA1100" = "y" -o \
"$CONFIG_ARCH_LUBBOCK" = "y" -o \
"$CONFIG_ARCH_PXA_IDP" = "y" -o \
"$CONFIG_ARCH_INTEGRATOR" = "y" -o \ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \
"$CONFIG_ARCH_P720T" = "y" ]; then "$CONFIG_ARCH_P720T" = "y" ]; then
bool ' Timer LED' CONFIG_LEDS_TIMER bool ' Timer LED' CONFIG_LEDS_TIMER
......
This diff is collapsed.
...@@ -215,8 +215,8 @@ ...@@ -215,8 +215,8 @@
.macro addruart,rx .macro addruart,rx
mrc p15, 0, \rx, c1, c0 mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled? tst \rx, #1 @ MMU enabled?
moveq \rx, #0x40000000 @ physical moveq \rx, #0x40000000 @ physical
movne \rx, #0xfc000000 @ virtual movne \rx, #io_p2v(0x40000000) @ virtual
orr \rx, \rx, #0x00100000 orr \rx, \rx, #0x00100000
.endm .endm
......
...@@ -590,7 +590,7 @@ ENTRY(anakin_active_irqs) ...@@ -590,7 +590,7 @@ ENTRY(anakin_active_irqs)
.endm .endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \base, #0xfc000000 @ IIR Ctl = 0xfcd00000 mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
add \base, \base, #0x00d00000 add \base, \base, #0x00d00000
ldr \irqstat, [\base, #0] @ ICIP ldr \irqstat, [\base, #0] @ ICIP
ldr \irqnr, [\base, #4] @ ICMR ldr \irqnr, [\base, #4] @ ICMR
......
...@@ -29,4 +29,7 @@ leds-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o ...@@ -29,4 +29,7 @@ leds-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
obj-$(CONFIG_LEDS) += $(leds-y) obj-$(CONFIG_LEDS) += $(leds-y)
# Misc features
obj-$(CONFIG_PM) += pm.o sleep.o
include $(TOPDIR)/Rules.make include $(TOPDIR)/Rules.make
...@@ -91,9 +91,10 @@ static struct map_desc standard_io_desc[] __initdata = { ...@@ -91,9 +91,10 @@ static struct map_desc standard_io_desc[] __initdata = {
/* virtual physical length type */ /* virtual physical length type */
{ 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */ { 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */
{ 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */ { 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */
{ 0xfc000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */ { 0xf8000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */
{ 0xfe000000, 0x44000000, 0x00200000, MT_DEVICE }, /* LCD */ { 0xfa000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
{ 0xff000000, 0x48000000, 0x00200000, MT_DEVICE } /* Mem Ctl */ { 0xfc000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
{ 0xff000000, 0x00000000, 0x00100000, MT_DEVICE } /* UNCACHED_PHYS_0 */
}; };
void __init pxa_map_io(void) void __init pxa_map_io(void)
......
...@@ -142,11 +142,20 @@ static void __init lubbock_map_io(void) ...@@ -142,11 +142,20 @@ static void __init lubbock_map_io(void)
/* This is for the SMC chip select */ /* This is for the SMC chip select */
pxa_gpio_mode(GPIO79_nCS_3_MD); pxa_gpio_mode(GPIO79_nCS_3_MD);
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x00008000;
PGSR1 = 0x003F0202;
PGSR2 = 0x0001C000;
PCFR |= PCFR_OPDE;
} }
MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform") MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform")
MAINTAINER("MontaVista Software Inc.") MAINTAINER("MontaVista Software Inc.")
BOOT_MEM(0xa0000000, 0x40000000, 0xfc000000) BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000))
MAPIO(lubbock_map_io) MAPIO(lubbock_map_io)
INITIRQ(lubbock_init_irq) INITIRQ(lubbock_init_irq)
MACHINE_END MACHINE_END
/*
* PXA250/210 Power Management Routines
*
* Original code for the SA11x0:
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
*
* Modified for the PXA250 by Nicolas Pitre:
* Copyright (c) 2002 Monta Vista Software, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/sysctl.h>
#include <linux/errno.h>
#include <asm/hardware.h>
#include <asm/memory.h>
#include <asm/system.h>
#include <asm/leds.h>
/*
* Debug macros
*/
#undef DEBUG
extern void pxa_cpu_suspend(void);
extern void pxa_cpu_resume(void);
#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
/*
* List of global PXA peripheral registers to preserve.
* More ones like CP and general purpose register values are preserved
* with the stack pointer in sleep.S.
*/
enum { SLEEP_SAVE_START = 0,
SLEEP_SAVE_OSCR, SLEEP_SAVE_OIER,
SLEEP_SAVE_OSMR0, SLEEP_SAVE_OSMR1, SLEEP_SAVE_OSMR2, SLEEP_SAVE_OSMR3,
SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR2_L,
SLEEP_SAVE_GAFR0_U, SLEEP_SAVE_GAFR1_U, SLEEP_SAVE_GAFR2_U,
SLEEP_SAVE_FFIER, SLEEP_SAVE_FFLCR, SLEEP_SAVE_FFMCR,
SLEEP_SAVE_FFSPR, SLEEP_SAVE_FFISR,
SLEEP_SAVE_FFDLL, SLEEP_SAVE_FFDLH,
SLEEP_SAVE_ICMR,
SLEEP_SAVE_CKEN,
SLEEP_SAVE_CKSUM,
SLEEP_SAVE_SIZE
};
int pm_do_suspend(void)
{
unsigned long sleep_save[SLEEP_SAVE_SIZE];
unsigned long checksum = 0;
int i;
cli();
clf();
leds_event(led_stop);
/* preserve current time */
RCNR = xtime.tv_sec;
/*
* Temporary solution. This won't be necessary once
* we move pxa support into the serial/* driver
* Save the FF UART
*/
SAVE(FFIER);
SAVE(FFLCR);
SAVE(FFMCR);
SAVE(FFSPR);
SAVE(FFISR);
FFLCR |= 0x80;
SAVE(FFDLL);
SAVE(FFDLH);
FFLCR &= 0xef;
/* save vital registers */
SAVE(OSCR);
SAVE(OSMR0);
SAVE(OSMR1);
SAVE(OSMR2);
SAVE(OSMR3);
SAVE(OIER);
SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
SAVE(GAFR0_L); SAVE(GAFR0_U);
SAVE(GAFR1_L); SAVE(GAFR1_U);
SAVE(GAFR2_L); SAVE(GAFR2_U);
SAVE(ICMR);
ICMR = 0;
SAVE(CKEN);
CKEN = 0;
/* Note: wake up source are set up in each machine specific files */
/* clear GPIO transition detect bits */
GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
/* Clear sleep reset status */
RCSR = RCSR_SMR;
/* set resume return address */
PSPR = virt_to_phys(pxa_cpu_resume);
/* before sleeping, calculate and save a checksum */
for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
checksum += sleep_save[i];
sleep_save[SLEEP_SAVE_CKSUM] = checksum;
/* *** go zzz *** */
pxa_cpu_suspend();
/* after sleeping, validate the checksum */
checksum = 0;
for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
checksum += sleep_save[i];
/* if invalid, display message and wait for a hardware reset */
if (checksum != sleep_save[SLEEP_SAVE_CKSUM]) {
#ifdef CONFIG_ARCH_LUBBOCK
LUB_HEXLED = 0xbadbadc5;
#endif
while (1);
}
/* ensure not to come back here if it wasn't intended */
PSPR = 0;
/* restore registers */
RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
RESTORE(GAFR0_L); RESTORE(GAFR0_U);
RESTORE(GAFR1_L); RESTORE(GAFR1_U);
RESTORE(GAFR2_L); RESTORE(GAFR2_U);
PSSR = PSSR_PH;
RESTORE(OSMR0);
RESTORE(OSMR1);
RESTORE(OSMR2);
RESTORE(OSMR3);
RESTORE(OSCR);
RESTORE(OIER);
RESTORE(CKEN);
ICLR = 0;
ICCR = 1;
RESTORE(ICMR);
/*
* Temporary solution. This won't be necessary once
* we move pxa support into the serial/* driver.
* Restore the FF UART.
*/
RESTORE(FFMCR);
RESTORE(FFSPR);
RESTORE(FFLCR);
FFLCR |= 0x80;
RESTORE(FFDLH);
RESTORE(FFDLL);
RESTORE(FFLCR);
RESTORE(FFISR);
FFFCR = 0x07;
RESTORE(FFIER);
/* restore current time */
xtime.tv_sec = RCNR;
#ifdef DEBUG
printk(KERN_DEBUG "*** made it back from resume\n");
#endif
leds_event(led_start);
sti();
return 0;
}
unsigned long sleep_phys_sp(void *sp)
{
return virt_to_phys(sp);
}
#ifdef CONFIG_SYSCTL
/*
* ARGH! ACPI people defined CTL_ACPI in linux/acpi.h rather than
* linux/sysctl.h.
*
* This means our interface here won't survive long - it needs a new
* interface. Quick hack to get this working - use sysctl id 9999.
*/
#warning ACPI broke the kernel, this interface needs to be fixed up.
#define CTL_ACPI 9999
#define ACPI_S1_SLP_TYP 19
/*
* Send us to sleep.
*/
static int sysctl_pm_do_suspend(void)
{
int retval;
retval = pm_send_all(PM_SUSPEND, (void *)3);
if (retval == 0) {
retval = pm_do_suspend();
pm_send_all(PM_RESUME, (void *)0);
}
return retval;
}
static struct ctl_table pm_table[] =
{
{ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, (proc_handler *)&sysctl_pm_do_suspend},
{0}
};
static struct ctl_table pm_dir_table[] =
{
{CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
{0}
};
/*
* Initialize power interface
*/
static int __init pm_init(void)
{
register_sysctl_table(pm_dir_table, 1);
return 0;
}
__initcall(pm_init);
#endif
/*
* Low-level PXA250/210 sleep/wakeUp support
*
* Initial SA1110 code:
* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
*
* Adapted for PXA by Nicolas Pitre:
* Copyright (c) 2002 Monta Vista Software, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License.
*/
#include <linux/config.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/hardware.h>
.text
/*
* pxa_cpu_suspend()
*
* Forces CPU into sleep state
*/
ENTRY(pxa_cpu_suspend)
mra r2, r3, acc0
stmfd sp!, {r2 - r12, lr} @ save registers on stack
@ get coprocessor registers
mrc p15, 0, r4, c15, c1, 0 @ CP access reg
mrc p15, 0, r5, c13, c0, 0 @ PID
mrc p15, 0, r6, c3, c0, 0 @ domain ID
mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
mrc p15, 0, r9, c1, c0, 0 @ control reg
@ store them plus current virtual stack ptr on stack
mov r10, sp
stmfd sp!, {r4 - r10}
@ preserve phys address of stack
mov r0, sp
bl sleep_phys_sp
ldr r1, =sleep_save_sp
str r0, [r1]
@ clean data cache
bl cpu_xscale_cache_clean_invalidate_all
@ Put the processor to sleep
@ (also workaround for sighting 28071)
@ prepare value for sleep mode
mov r1, #3 @ sleep mode
@ prepare to put SDRAM into self-refresh manually
ldr r4, =MDREFR
ldr r5, [r4]
orr r5, r5, #MDREFR_SLFRSH
@ prepare pointer to physical address 0 (virtual mapping in generic.c)
mov r2, #UNCACHED_PHYS_0
@ align execution to a cache line
b 1f
.ltorg
.align 5
1:
@ All needed values are now in registers.
@ These last instructions should be in cache
@ put SDRAM into self-refresh
str r5, [r4]
@ force address lines low by reading at physical address 0
ldr r3, [r2]
@ enter sleep mode
mcr p14, 0, r1, c7, c0, 0
20: nop
b 20b @ loop waiting for sleep
/*
* cpu_pxa_resume()
*
* entry point from bootloader into kernel during resume
*
* Note: Yes, part of the following code is located into the .data section.
* This is to allow sleep_save_sp to be accessed with a relative load
* while we can't rely on any MMU translation. We could have put
* sleep_save_sp in the .text section as well, but some setups might
* insist on it to be truely read-only.
*/
.data
.align 5
ENTRY(pxa_cpu_resume)
mov r0, #I_BIT | F_BIT | MODE_SVC @ set SVC, irqs off
msr cpsr_c, r0
ldr r0, sleep_save_sp @ stack phys addr
ldr r2, =resume_after_mmu @ its absolute virtual address
ldmfd r0, {r4 - r9, sp} @ CP regs + virt stack ptr
mov r1, #0
mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
#ifdef CONFIG_XSCALE_CACHE_ERRATA
bic r9, r9, #0x0004 @ see cpu_xscale_proc_init
#endif
mcr p15, 0, r4, c15, c1, 0 @ CP access reg
mcr p15, 0, r5, c13, c0, 0 @ PID
mcr p15, 0, r6, c3, c0, 0 @ domain ID
mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
b resume_turn_on_mmu @ cache align execution
.align 5
resume_turn_on_mmu:
mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, caches, etc.
@ Let us ensure we jump to resume_after_mmu only when the mcr above
@ actually took effect. They call it the "cpwait" operation.
mrc p15, 0, r1, c2, c0, 0 @ queue a dependency on CP15
sub pc, r2, r1, lsr #32 @ jump to virtual addr
nop
nop
nop
sleep_save_sp:
.word 0 @ preserve stack phys ptr here
.text
resume_after_mmu:
#ifdef CONFIG_XSCALE_CACHE_ERRATA
bl cpu_xscale_proc_init
#endif
ldmfd sp!, {r2, r3}
mar acc0, r2, r3
ldmfd sp!, {r4 - r12, pc} @ return to caller
...@@ -156,7 +156,7 @@ ENTRY(cpu_xscale_reset) ...@@ -156,7 +156,7 @@ ENTRY(cpu_xscale_reset)
msr cpsr_c, r1 @ reset CPSR msr cpsr_c, r1 @ reset CPSR
mrc p15, 0, r1, c1, c0, 0 @ ctrl register mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x0086 @ ........B....CA. bic r1, r1, #0x0086 @ ........B....CA.
bic r1, r1, #0x1900 @ ...IZ..S........ bic r1, r1, #0x3900 @ ..VIZ..S........
mcr p15, 0, r1, c1, c0, 0 @ ctrl register mcr p15, 0, r1, c1, c0, 0 @ ctrl register
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
bic r1, r1, #0x0001 @ ...............M bic r1, r1, #0x0001 @ ...............M
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
# Makefile for the kernel pcmcia subsystem (c/o David Hinds) # Makefile for the kernel pcmcia subsystem (c/o David Hinds)
# #
export-objs := ds.o cs.o yenta.o export-objs := ds.o cs.o yenta.o sa1100_pcmcia.o
obj-$(CONFIG_PCMCIA) += pcmcia_core.o ds.o obj-$(CONFIG_PCMCIA) += pcmcia_core.o ds.o
ifeq ($(CONFIG_CARDBUS),y) ifeq ($(CONFIG_CARDBUS),y)
......
...@@ -1052,6 +1052,7 @@ int sa1100_register_pcmcia(struct pcmcia_low_level *ops) ...@@ -1052,6 +1052,7 @@ int sa1100_register_pcmcia(struct pcmcia_low_level *ops)
pcmcia_low_level = NULL; pcmcia_low_level = NULL;
return ret; return ret;
} }
EXPORT_SYMBOL(sa1100_register_pcmcia);
/* sa1100_unregister_pcmcia() /* sa1100_unregister_pcmcia()
* ^^^^^^^^^^^^^^^^^^^^^^^^^^ * ^^^^^^^^^^^^^^^^^^^^^^^^^^
...@@ -1091,6 +1092,7 @@ void sa1100_unregister_pcmcia(struct pcmcia_low_level *ops) ...@@ -1091,6 +1092,7 @@ void sa1100_unregister_pcmcia(struct pcmcia_low_level *ops)
pcmcia_low_level = NULL; pcmcia_low_level = NULL;
} }
EXPORT_SYMBOL(sa1100_unregister_pcmcia);
/* sa1100_pcmcia_init() /* sa1100_pcmcia_init()
* ^^^^^^^^^^^^^^^^^^^^ * ^^^^^^^^^^^^^^^^^^^^
......
...@@ -205,9 +205,6 @@ ...@@ -205,9 +205,6 @@
extern void (*sa1100fb_backlight_power)(int on); extern void (*sa1100fb_backlight_power)(int on);
extern void (*sa1100fb_lcd_power)(int on); extern void (*sa1100fb_lcd_power)(int on);
void (*sa1100fb_blank_helper)(int blank);
EXPORT_SYMBOL(sa1100fb_blank_helper);
/* /*
* IMHO this looks wrong. In 8BPP, length should be 8. * IMHO this looks wrong. In 8BPP, length should be 8.
*/ */
...@@ -262,7 +259,7 @@ static struct sa1100fb_mach_info pal_info __initdata = { ...@@ -262,7 +259,7 @@ static struct sa1100fb_mach_info pal_info __initdata = {
#endif #endif
#endif #endif
#ifdef CONFIG_SA1100_H3XXX #ifdef CONFIG_SA1100_H3800
static struct sa1100fb_mach_info h3800_info __initdata = { static struct sa1100fb_mach_info h3800_info __initdata = {
pixclock: 174757, bpp: 16, pixclock: 174757, bpp: 16,
xres: 320, yres: 240, xres: 320, yres: 240,
...@@ -274,9 +271,12 @@ static struct sa1100fb_mach_info h3800_info __initdata = { ...@@ -274,9 +271,12 @@ static struct sa1100fb_mach_info h3800_info __initdata = {
sync: 0, cmap_static: 1, sync: 0, cmap_static: 1,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act, lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
lccr3: LCCR3_ACBsCntOff | LCCR3_PixFlEdg | LCCR3_OutEnH, lccr3: LCCR3_ACBsDiv(2) | LCCR3_PixRsEdg | LCCR3_OutEnH |
LCCR3_ACBsCntOff,
}; };
#endif
#ifdef CONFIG_SA1100_H3600
static struct sa1100fb_mach_info h3600_info __initdata = { static struct sa1100fb_mach_info h3600_info __initdata = {
pixclock: 174757, bpp: 16, pixclock: 174757, bpp: 16,
xres: 320, yres: 240, xres: 320, yres: 240,
...@@ -288,7 +288,8 @@ static struct sa1100fb_mach_info h3600_info __initdata = { ...@@ -288,7 +288,8 @@ static struct sa1100fb_mach_info h3600_info __initdata = {
sync: 0, cmap_static: 1, sync: 0, cmap_static: 1,
lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act, lccr0: LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
lccr3: LCCR3_ACBsCntOff | LCCR3_OutEnH | LCCR3_PixFlEdg, lccr3: LCCR3_ACBsDiv(2) | LCCR3_PixRsEdg | LCCR3_OutEnH |
LCCR3_ACBsCntOff,
}; };
static struct sa1100fb_rgb h3600_rgb_16 = { static struct sa1100fb_rgb h3600_rgb_16 = {
...@@ -297,7 +298,9 @@ static struct sa1100fb_rgb h3600_rgb_16 = { ...@@ -297,7 +298,9 @@ static struct sa1100fb_rgb h3600_rgb_16 = {
blue: { offset: 1, length: 4, }, blue: { offset: 1, length: 4, },
transp: { offset: 0, length: 0, }, transp: { offset: 0, length: 0, },
}; };
#endif
#ifdef CONFIG_SA1100_H3100
static struct sa1100fb_mach_info h3100_info __initdata = { static struct sa1100fb_mach_info h3100_info __initdata = {
pixclock: 406977, bpp: 4, pixclock: 406977, bpp: 4,
xres: 320, yres: 240, xres: 320, yres: 240,
...@@ -680,14 +683,18 @@ sa1100fb_get_machine_info(struct sa1100fb_info *fbi) ...@@ -680,14 +683,18 @@ sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
#endif #endif
} }
#endif #endif
#ifdef CONFIG_SA1100_H3XXX #ifdef CONFIG_SA1100_H3100
if (machine_is_h3100()) {
inf = &h3100_info;
}
#endif
#ifdef CONFIG_SA1100_H3600
if (machine_is_h3600()) { if (machine_is_h3600()) {
inf = &h3600_info; inf = &h3600_info;
fbi->rgb[RGB_16] = &h3600_rgb_16; fbi->rgb[RGB_16] = &h3600_rgb_16;
} }
if (machine_is_h3100()) { #endif
inf = &h3100_info; #ifdef CONFIG_SA1100_H3800
}
if (machine_is_h3800()) { if (machine_is_h3800()) {
inf = &h3800_info; inf = &h3800_info;
} }
...@@ -1310,13 +1317,9 @@ static int sa1100fb_blank(int blank, struct fb_info *info) ...@@ -1310,13 +1317,9 @@ static int sa1100fb_blank(int blank, struct fb_info *info)
for (i = 0; i < fbi->palette_size; i++) for (i = 0; i < fbi->palette_size; i++)
sa1100fb_setpalettereg(i, 0, 0, 0, 0, info); sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
sa1100fb_schedule_task(fbi, C_DISABLE); sa1100fb_schedule_task(fbi, C_DISABLE);
if (sa1100fb_blank_helper)
sa1100fb_blank_helper(blank);
break; break;
case VESA_NO_BLANKING: case VESA_NO_BLANKING:
if (sa1100fb_blank_helper)
sa1100fb_blank_helper(blank);
if (fbi->fb.disp->visual == FB_VISUAL_PSEUDOCOLOR || if (fbi->fb.disp->visual == FB_VISUAL_PSEUDOCOLOR ||
fbi->fb.disp->visual == FB_VISUAL_STATIC_PSEUDOCOLOR) fbi->fb.disp->visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
fb_set_cmap(&fbi->fb.cmap, 1, info); fb_set_cmap(&fbi->fb.cmap, 1, info);
......
...@@ -27,17 +27,27 @@ ...@@ -27,17 +27,27 @@
/* /*
* Intel PXA internal I/O mappings * We requires absolute addresses.
*/ */
#define PCIO_BASE 0
#define io_p2v(x) \ /*
(((x) < 0x44000000) ? ((x) - 0x40000000 + 0xfc000000) : \ * Workarounds for at least 2 errata so far require this.
((x) < 0x48000000) ? ((x) - 0x44000000 + 0xfe000000) : \ * The mapping is set in mach-pxa/generic.c.
((x) - 0x48000000 + 0xff000000)) */
#define io_v2p( x ) \ #define UNCACHED_PHYS_0 0xff000000
(((x) < 0xfe000000) ? ((x) - 0xfc000000 + 0x40000000) : \ #define UNCACHED_ADDR UNCACHED_PHYS_0
((x) < 0xff000000) ? ((x) - 0xfe000000 + 0x44000000) : \
((x) - 0xff000000 + 0x48000000)) /*
* Intel PXA internal I/O mappings:
*
* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
*/
#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
...@@ -51,7 +61,7 @@ ...@@ -51,7 +61,7 @@
* doesn't guess this by itself. * doesn't guess this by itself.
*/ */
#include <asm/types.h> #include <asm/types.h>
typedef struct { volatile u32 offset[1024]; } __regbase; typedef struct { volatile u32 offset[4096]; } __regbase;
# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] # define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
# define __REG(x) __REGP(io_p2v(x)) # define __REG(x) __REGP(io_p2v(x))
#endif #endif
...@@ -93,5 +103,6 @@ extern unsigned int get_lclk_frequency_10khz(void); ...@@ -93,5 +103,6 @@ extern unsigned int get_lclk_frequency_10khz(void);
#include "lubbock.h" #include "lubbock.h"
#include "idp.h" #include "idp.h"
#include "cerf.h"
#endif /* _ASM_ARCH_HARDWARE_H */ #endif /* _ASM_ARCH_HARDWARE_H */
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