Commit 011e3cde authored by Greg Ungerer's avatar Greg Ungerer Committed by Linus Torvalds

[PATCH] m68knommu: change ColdFire 5206 SDRAM register names

Change the SDRAM register names to be consistent across all ColdFire
header files. Simplied their use in common memory sizing code at
startup time.
Signed-off-by: default avatarGreg Ungerer <gerg@snapgear.com>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent c8cf06ef
...@@ -47,12 +47,12 @@ ...@@ -47,12 +47,12 @@
#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */ #define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */ #define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ #define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ #define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ #define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ #define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ #define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */
#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ #define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ #define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
......
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