Commit 013df388 authored by Arnd Bergmann's avatar Arnd Bergmann Committed by Olof Johansson

ARM: tegra: select CPU_FREQ_TABLE

The tegra cpufreq implementation relies on the cpu_freq_table
code, so make sure that this is always there when needed.
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarAlan Ott <alan@signal11.us>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 0e86ca49
...@@ -17,6 +17,7 @@ config ARCH_TEGRA_2x_SOC ...@@ -17,6 +17,7 @@ config ARCH_TEGRA_2x_SOC
select ARM_ERRATA_764369 select ARM_ERRATA_764369
select PL310_ERRATA_727915 if CACHE_L2X0 select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0
select CPU_FREQ_TABLE if CPU_FREQ
help help
Support for NVIDIA Tegra AP20 and T20 processors, based on the Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
...@@ -35,6 +36,7 @@ config ARCH_TEGRA_3x_SOC ...@@ -35,6 +36,7 @@ config ARCH_TEGRA_3x_SOC
select ARM_ERRATA_754322 select ARM_ERRATA_754322
select ARM_ERRATA_764369 select ARM_ERRATA_764369
select PL310_ERRATA_769419 if CACHE_L2X0 select PL310_ERRATA_769419 if CACHE_L2X0
select CPU_FREQ_TABLE if CPU_FREQ
help help
Support for NVIDIA Tegra T30 processor family, based on the Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment