Skip to content

L
linux
Commit 05c7145d authored by Ben Skeggs's avatar Ben Skeggs
Browse files
Options

drm/nouveau/fifo: namespace + nvidia gpu names (no binary change) 

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 5b85057a
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1126 additions and 1188 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/os.h
View file @ 05c7145d
......@@ -248,5 +248,7 @@
#define nouveau_dmaeng nvkm_dmaeng
#define nouveau_dmaobj nvkm_dmaobj
#define nouveau_disp nvkm_disp
#define nouveau_fifo_chan nvkm_fifo_chan
#define nouveau_fifo nvkm_fifo
#endif
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
View file @ 05c7145d
#ifndef __NOUVEAU_FIFO_H__
#define __NOUVEAU_FIFO_H__
#ifndef __NVKM_FIFO_H__
#define __NVKM_FIFO_H__
#include <core/namedb.h>
#include <core/gpuobj.h>
#include <core/engine.h>
#include <core/event.h>
struct nouveau_fifo_chan {
struct nouveau_namedb namedb;
struct nouveau_dmaobj *pushdma;
struct nouveau_gpuobj *pushgpu;
struct nvkm_fifo_chan {
struct nvkm_namedb namedb;
struct nvkm_dmaobj *pushdma;
struct nvkm_gpuobj *pushgpu;
void __iomem *user;
u64 addr;
u32 size;
......@@ -17,110 +13,114 @@ struct nouveau_fifo_chan {
atomic_t refcnt; /* NV04_NVSW_SET_REF */
};
static inline struct nouveau_fifo_chan *
nouveau_fifo_chan(void *obj)
static inline struct nvkm_fifo_chan *
nvkm_fifo_chan(void *obj)
{
return (void *)nv_namedb(obj);
}
#define nouveau_fifo_channel_create(p,e,c,b,a,s,n,m,d) \
nouveau_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \
#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d) \
nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \
(m), sizeof(**d), (void **)d)
#define nouveau_fifo_channel_init(p) \
nouveau_namedb_init(&(p)->namedb)
#define nouveau_fifo_channel_fini(p,s) \
nouveau_namedb_fini(&(p)->namedb, (s))
int nouveau_fifo_channel_create_(struct nouveau_object *,
struct nouveau_object *,
struct nouveau_oclass *,
#define nvkm_fifo_channel_init(p) \
nvkm_namedb_init(&(p)->namedb)
#define nvkm_fifo_channel_fini(p,s) \
nvkm_namedb_fini(&(p)->namedb, (s))
int nvkm_fifo_channel_create_(struct nvkm_object *,
struct nvkm_object *,
struct nvkm_oclass *,
int bar, u32 addr, u32 size, u32 push,
u64 engmask, int len, void **);
void nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *);
void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *);
#define _nouveau_fifo_channel_init _nouveau_namedb_init
#define _nouveau_fifo_channel_fini _nouveau_namedb_fini
#define _nvkm_fifo_channel_init _nvkm_namedb_init
#define _nvkm_fifo_channel_fini _nvkm_namedb_fini
void _nouveau_fifo_channel_dtor(struct nouveau_object *);
int _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *);
u32 _nouveau_fifo_channel_rd32(struct nouveau_object *, u64);
void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32);
int _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
void _nvkm_fifo_channel_dtor(struct nvkm_object *);
int _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *);
u32 _nvkm_fifo_channel_rd32(struct nvkm_object *, u64);
void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32);
int _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
struct nouveau_fifo_base {
struct nouveau_gpuobj gpuobj;
#include <core/gpuobj.h>
struct nvkm_fifo_base {
struct nvkm_gpuobj gpuobj;
};
#define nouveau_fifo_context_create(p,e,c,g,s,a,f,d) \
nouveau_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))
#define nouveau_fifo_context_destroy(p) \
nouveau_gpuobj_destroy(&(p)->gpuobj)
#define nouveau_fifo_context_init(p) \
nouveau_gpuobj_init(&(p)->gpuobj)
#define nouveau_fifo_context_fini(p,s) \
nouveau_gpuobj_fini(&(p)->gpuobj, (s))
#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d) \
nvkm_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d))
#define nvkm_fifo_context_destroy(p) \
nvkm_gpuobj_destroy(&(p)->gpuobj)
#define nvkm_fifo_context_init(p) \
nvkm_gpuobj_init(&(p)->gpuobj)
#define nvkm_fifo_context_fini(p,s) \
nvkm_gpuobj_fini(&(p)->gpuobj, (s))
#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor
#define _nvkm_fifo_context_init _nvkm_gpuobj_init
#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini
#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32
#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32
#define _nouveau_fifo_context_dtor _nouveau_gpuobj_dtor
#define _nouveau_fifo_context_init _nouveau_gpuobj_init
#define _nouveau_fifo_context_fini _nouveau_gpuobj_fini
#define _nouveau_fifo_context_rd32 _nouveau_gpuobj_rd32
#define _nouveau_fifo_context_wr32 _nouveau_gpuobj_wr32
#include <core/engine.h>
#include <core/event.h>
struct nouveau_fifo {
struct nouveau_engine base;
struct nvkm_fifo {
struct nvkm_engine base;
struct nvkm_event cevent; /* channel creation event */
struct nvkm_event uevent; /* async user trigger */
struct nouveau_object **channel;
struct nvkm_object **channel;
spinlock_t lock;
u16 min;
u16 max;
int (*chid)(struct nouveau_fifo *, struct nouveau_object *);
void (*pause)(struct nouveau_fifo *, unsigned long *);
void (*start)(struct nouveau_fifo *, unsigned long *);
int (*chid)(struct nvkm_fifo *, struct nvkm_object *);
void (*pause)(struct nvkm_fifo *, unsigned long *);
void (*start)(struct nvkm_fifo *, unsigned long *);
};
static inline struct nouveau_fifo *
nouveau_fifo(void *obj)
static inline struct nvkm_fifo *
nvkm_fifo(void *obj)
{
return (void *)nouveau_engine(obj, NVDEV_ENGINE_FIFO);
return (void *)nvkm_engine(obj, NVDEV_ENGINE_FIFO);
}
#define nouveau_fifo_create(o,e,c,fc,lc,d) \
nouveau_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)
#define nouveau_fifo_init(p) \
nouveau_engine_init(&(p)->base)
#define nouveau_fifo_fini(p,s) \
nouveau_engine_fini(&(p)->base, (s))
#define nvkm_fifo_create(o,e,c,fc,lc,d) \
nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)
#define nvkm_fifo_init(p) \
nvkm_engine_init(&(p)->base)
#define nvkm_fifo_fini(p,s) \
nvkm_engine_fini(&(p)->base, (s))
int nouveau_fifo_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int min, int max,
int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int min, int max,
int size, void **);
void nouveau_fifo_destroy(struct nouveau_fifo *);
void nvkm_fifo_destroy(struct nvkm_fifo *);
const char *
nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid);
#define _nouveau_fifo_init _nouveau_engine_init
#define _nouveau_fifo_fini _nouveau_engine_fini
extern struct nouveau_oclass *nv04_fifo_oclass;
extern struct nouveau_oclass *nv10_fifo_oclass;
extern struct nouveau_oclass *nv17_fifo_oclass;
extern struct nouveau_oclass *nv40_fifo_oclass;
extern struct nouveau_oclass *nv50_fifo_oclass;
extern struct nouveau_oclass *nv84_fifo_oclass;
extern struct nouveau_oclass *nvc0_fifo_oclass;
extern struct nouveau_oclass *nve0_fifo_oclass;
extern struct nouveau_oclass *gk20a_fifo_oclass;
extern struct nouveau_oclass *nv108_fifo_oclass;
int nouveau_fifo_uevent_ctor(struct nouveau_object *, void *, u32,
struct nvkm_notify *);
void nouveau_fifo_uevent(struct nouveau_fifo *);
void nv04_fifo_intr(struct nouveau_subdev *);
int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);
nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid);
#define _nvkm_fifo_init _nvkm_engine_init
#define _nvkm_fifo_fini _nvkm_engine_fini
extern struct nvkm_oclass *nv04_fifo_oclass;
extern struct nvkm_oclass *nv10_fifo_oclass;
extern struct nvkm_oclass *nv17_fifo_oclass;
extern struct nvkm_oclass *nv40_fifo_oclass;
extern struct nvkm_oclass *nv50_fifo_oclass;
extern struct nvkm_oclass *g84_fifo_oclass;
extern struct nvkm_oclass *gf100_fifo_oclass;
extern struct nvkm_oclass *gk104_fifo_oclass;
extern struct nvkm_oclass *gk20a_fifo_oclass;
extern struct nvkm_oclass *gk208_fifo_oclass;
int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,
struct nvkm_notify *);
void nvkm_fifo_uevent(struct nvkm_fifo *);
void nv04_fifo_intr(struct nvkm_subdev *);
int nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View file @ 05c7145d
......@@ -84,7 +84,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
......@@ -128,7 +128,7 @@ gm100_identify(struct nouveau_device *device)
#endif
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
#if 0
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
#endif
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View file @ 05c7145d
......@@ -106,7 +106,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
......@@ -135,7 +135,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
......@@ -164,7 +164,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
......@@ -193,7 +193,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
......@@ -222,7 +222,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
......@@ -251,7 +251,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
......@@ -280,7 +280,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
......@@ -309,7 +309,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
......@@ -338,7 +338,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
......@@ -368,7 +368,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
......@@ -399,7 +399,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
......@@ -429,7 +429,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
......@@ -459,7 +459,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nv98_mspdec_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
View file @ 05c7145d
......@@ -81,7 +81,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......@@ -114,7 +114,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......@@ -147,7 +147,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......@@ -179,7 +179,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......@@ -212,7 +212,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......@@ -244,7 +244,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......@@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......@@ -309,7 +309,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......@@ -339,7 +339,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
View file @ 05c7145d
......@@ -81,7 +81,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
......@@ -115,7 +115,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
......@@ -149,7 +149,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
......@@ -205,7 +205,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
......@@ -239,7 +239,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
......@@ -273,7 +273,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
......@@ -306,7 +306,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
View file @ 05c7145d
......@@ -4,8 +4,8 @@ nvkm-y += nvkm/engine/fifo/nv10.o
nvkm-y += nvkm/engine/fifo/nv17.o
nvkm-y += nvkm/engine/fifo/nv40.o
nvkm-y += nvkm/engine/fifo/nv50.o
nvkm-y += nvkm/engine/fifo/nv84.o
nvkm-y += nvkm/engine/fifo/nvc0.o
nvkm-y += nvkm/engine/fifo/nve0.o
nvkm-y += nvkm/engine/fifo/g84.o
nvkm-y += nvkm/engine/fifo/gf100.o
nvkm-y += nvkm/engine/fifo/gk104.o
nvkm-y += nvkm/engine/fifo/gk20a.o
nvkm-y += nvkm/engine/fifo/nv108.o
nvkm-y += nvkm/engine/fifo/gk208.o
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
View file @ 05c7145d
......@@ -21,23 +21,21 @@
*
* Authors: Ben Skeggs
*/
#include <engine/fifo.h>
#include <core/client.h>
#include <core/device.h>
#include <core/notify.h>
#include <core/object.h>
#include <core/handle.h>
#include <core/event.h>
#include <nvif/unpack.h>
#include <core/notify.h>
#include <engine/dmaobj.h>
#include <nvif/class.h>
#include <nvif/event.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <nvif/unpack.h>
static int
nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size,
struct nvkm_notify *notify)
nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
{
if (size == 0) {
notify->size = 0;
......@@ -49,33 +47,33 @@ nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size,
}
static const struct nvkm_event_func
nouveau_fifo_event_func = {
.ctor = nouveau_fifo_event_ctor,
nvkm_fifo_event_func = {
.ctor = nvkm_fifo_event_ctor,
};
int
nouveau_fifo_channel_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
int bar, u32 addr, u32 size, u32 pushbuf,
u64 engmask, int len, void **ptr)
nvkm_fifo_channel_create_(struct nvkm_object *parent,
struct nvkm_object *engine,
struct nvkm_oclass *oclass,
int bar, u32 addr, u32 size, u32 pushbuf,
u64 engmask, int len, void **ptr)
{
struct nouveau_device *device = nv_device(engine);
struct nouveau_fifo *priv = (void *)engine;
struct nouveau_fifo_chan *chan;
struct nouveau_dmaeng *dmaeng;
struct nvkm_device *device = nv_device(engine);
struct nvkm_fifo *priv = (void *)engine;
struct nvkm_fifo_chan *chan;
struct nvkm_dmaeng *dmaeng;
unsigned long flags;
int ret;
/* create base object class */
ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
engmask, len, ptr);
ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL,
engmask, len, ptr);
chan = *ptr;
if (ret)
return ret;
/* validate dma object representing push buffer */
chan->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
chan->pushdma = (void *)nvkm_handle_ref(parent, pushbuf);
if (!chan->pushdma)
return -ENOENT;
......@@ -115,9 +113,9 @@ nouveau_fifo_channel_create_(struct nouveau_object *parent,
}
void
nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan)
nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan)
{
struct nouveau_fifo *priv = (void *)nv_object(chan)->engine;
struct nvkm_fifo *priv = (void *)nv_object(chan)->engine;
unsigned long flags;
if (chan->user)
......@@ -127,31 +125,31 @@ nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan)
priv->channel[chan->chid] = NULL;
spin_unlock_irqrestore(&priv->lock, flags);
nouveau_gpuobj_ref(NULL, &chan->pushgpu);
nouveau_object_ref(NULL, (struct nouveau_object **)&chan->pushdma);
nouveau_namedb_destroy(&chan->namedb);
nvkm_gpuobj_ref(NULL, &chan->pushgpu);
nvkm_object_ref(NULL, (struct nvkm_object **)&chan->pushdma);
nvkm_namedb_destroy(&chan->namedb);
}
void
_nouveau_fifo_channel_dtor(struct nouveau_object *object)
_nvkm_fifo_channel_dtor(struct nvkm_object *object)
{
struct nouveau_fifo_chan *chan = (void *)object;
nouveau_fifo_channel_destroy(chan);
struct nvkm_fifo_chan *chan = (void *)object;
nvkm_fifo_channel_destroy(chan);
}
int
_nouveau_fifo_channel_map(struct nouveau_object *object, u64 *addr, u32 *size)
_nvkm_fifo_channel_map(struct nvkm_object *object, u64 *addr, u32 *size)
{
struct nouveau_fifo_chan *chan = (void *)object;
struct nvkm_fifo_chan *chan = (void *)object;
*addr = chan->addr;
*size = chan->size;
return 0;
}
u32
_nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr)
_nvkm_fifo_channel_rd32(struct nvkm_object *object, u64 addr)
{
struct nouveau_fifo_chan *chan = (void *)object;
struct nvkm_fifo_chan *chan = (void *)object;
if (unlikely(!chan->user)) {
chan->user = ioremap(chan->addr, chan->size);
if (WARN_ON_ONCE(chan->user == NULL))
......@@ -161,9 +159,9 @@ _nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr)
}
void
_nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data)
_nvkm_fifo_channel_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
struct nouveau_fifo_chan *chan = (void *)object;
struct nvkm_fifo_chan *chan = (void *)object;
if (unlikely(!chan->user)) {
chan->user = ioremap(chan->addr, chan->size);
if (WARN_ON_ONCE(chan->user == NULL))
......@@ -173,8 +171,8 @@ _nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data)
}
int
nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
struct nvkm_notify *notify)
nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
{
union {
struct nvif_notify_uevent_req none;
......@@ -191,7 +189,7 @@ nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
}
void
nouveau_fifo_uevent(struct nouveau_fifo *fifo)
nvkm_fifo_uevent(struct nvkm_fifo *fifo)
{
struct nvif_notify_uevent_rep rep = {
};
......@@ -199,10 +197,10 @@ nouveau_fifo_uevent(struct nouveau_fifo *fifo)
}
int
_nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type,
struct nvkm_event **event)
_nvkm_fifo_channel_ntfy(struct nvkm_object *object, u32 type,
struct nvkm_event **event)
{
struct nouveau_fifo *fifo = (void *)object->engine;
struct nvkm_fifo *fifo = (void *)object->engine;
switch (type) {
case G82_CHANNEL_DMA_V0_NTFY_UEVENT:
if (nv_mclass(object) >= G82_CHANNEL_DMA) {
......@@ -217,14 +215,14 @@ _nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type,
}
static int
nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object)
nvkm_fifo_chid(struct nvkm_fifo *priv, struct nvkm_object *object)
{
int engidx = nv_hclass(priv) & 0xff;
while (object && object->parent) {
if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) &&
(nv_hclass(object->parent) & 0xff) == engidx)
return nouveau_fifo_chan(object)->chid;
return nvkm_fifo_chan(object)->chid;
object = object->parent;
}
......@@ -232,9 +230,9 @@ nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object)
}
const char *
nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid)
nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid)
{
struct nouveau_fifo_chan *chan = NULL;
struct nvkm_fifo_chan *chan = NULL;
unsigned long flags;
spin_lock_irqsave(&fifo->lock, flags);
......@@ -242,29 +240,28 @@ nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid)
chan = (void *)fifo->channel[chid];
spin_unlock_irqrestore(&fifo->lock, flags);
return nouveau_client_name(chan);
return nvkm_client_name(chan);
}
void
nouveau_fifo_destroy(struct nouveau_fifo *priv)
nvkm_fifo_destroy(struct nvkm_fifo *priv)
{
kfree(priv->channel);
nvkm_event_fini(&priv->uevent);
nvkm_event_fini(&priv->cevent);
nouveau_engine_destroy(&priv->base);
nvkm_engine_destroy(&priv->base);
}
int
nouveau_fifo_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
int min, int max, int length, void **pobject)
nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass,
int min, int max, int length, void **pobject)
{
struct nouveau_fifo *priv;
struct nvkm_fifo *priv;
int ret;
ret = nouveau_engine_create_(parent, engine, oclass, true, "PFIFO",
"fifo", length, pobject);
ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO",
"fifo", length, pobject);
priv = *pobject;
if (ret)
return ret;
......@@ -275,11 +272,11 @@ nouveau_fifo_create_(struct nouveau_object *parent,
if (!priv->channel)
return -ENOMEM;
ret = nvkm_event_init(&nouveau_fifo_event_func, 1, 1, &priv->cevent);
ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &priv->cevent);
if (ret)
return ret;
priv->chid = nouveau_fifo_chid;
priv->chid = nvkm_fifo_chid;
spin_lock_init(&priv->lock);
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h 0 → 100644
View file @ 05c7145d
#ifndef __NVKM_FIFO_NVE0_H__
#define __NVKM_FIFO_NVE0_H__
#include <engine/fifo.h>
int gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void gk104_fifo_dtor(struct nvkm_object *);
int gk104_fifo_init(struct nvkm_object *);
int gk104_fifo_fini(struct nvkm_object *, bool);
struct gk104_fifo_impl {
struct nvkm_oclass base;
u32 channels;
};
#endif
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv108.c → drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
View file @ 05c7145d
......@@ -21,17 +21,16 @@
*
* Authors: Ben Skeggs
*/
#include "gk104.h"
#include "nve0.h"
struct nouveau_oclass *
nv108_fifo_oclass = &(struct nve0_fifo_impl) {
struct nvkm_oclass *
gk208_fifo_oclass = &(struct gk104_fifo_impl) {
.base.handle = NV_ENGINE(FIFO, 0x08),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_fifo_ctor,
.dtor = nve0_fifo_dtor,
.init = nve0_fifo_init,
.fini = _nouveau_fifo_fini,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk104_fifo_ctor,
.dtor = gk104_fifo_dtor,
.init = gk104_fifo_init,
.fini = _nvkm_fifo_fini,
},
.channels = 1024,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
View file @ 05c7145d
......@@ -19,17 +19,16 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "gk104.h"
#include "nve0.h"
struct nouveau_oclass *
gk20a_fifo_oclass = &(struct nve0_fifo_impl) {
struct nvkm_oclass *
gk20a_fifo_oclass = &(struct gk104_fifo_impl) {
.base.handle = NV_ENGINE(FIFO, 0xea),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_fifo_ctor,
.dtor = nve0_fifo_dtor,
.init = nve0_fifo_init,
.fini = nve0_fifo_fini,
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk104_fifo_ctor,
.dtor = gk104_fifo_dtor,
.init = gk104_fifo_init,
.fini = gk104_fifo_fini,
},
.channels = 128,
}.base;
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
View file @ 05c7145d
#ifndef __NV04_FIFO_H__
#define __NV04_FIFO_H__
#include <engine/fifo.h>
#define NV04_PFIFO_DELAY_0 0x00002040
......@@ -141,38 +140,36 @@ struct ramfc_desc {
};
struct nv04_fifo_priv {
struct nouveau_fifo base;
struct nvkm_fifo base;
struct ramfc_desc *ramfc_desc;
struct nouveau_ramht *ramht;
struct nouveau_gpuobj *ramro;
struct nouveau_gpuobj *ramfc;
struct nvkm_ramht *ramht;
struct nvkm_gpuobj *ramro;
struct nvkm_gpuobj *ramfc;
};
struct nv04_fifo_base {
struct nouveau_fifo_base base;
struct nvkm_fifo_base base;
};
struct nv04_fifo_chan {
struct nouveau_fifo_chan base;
struct nvkm_fifo_chan base;
u32 subc[8];
u32 ramfc;
};
int nv04_fifo_object_attach(struct nouveau_object *,
struct nouveau_object *, u32);
void nv04_fifo_object_detach(struct nouveau_object *, int);
void nv04_fifo_chan_dtor(struct nouveau_object *);
int nv04_fifo_chan_init(struct nouveau_object *);
int nv04_fifo_chan_fini(struct nouveau_object *, bool suspend);
int nv04_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32);
void nv04_fifo_object_detach(struct nvkm_object *, int);
int nv04_fifo_context_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void nv04_fifo_chan_dtor(struct nvkm_object *);
int nv04_fifo_chan_init(struct nvkm_object *);
int nv04_fifo_chan_fini(struct nvkm_object *, bool suspend);
void nv04_fifo_dtor(struct nouveau_object *);
int nv04_fifo_init(struct nouveau_object *);
void nv04_fifo_pause(struct nouveau_fifo *, unsigned long *);
void nv04_fifo_start(struct nouveau_fifo *, unsigned long *);
int nv04_fifo_context_ctor(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, void *, u32,
struct nvkm_object **);
void nv04_fifo_dtor(struct nvkm_object *);
int nv04_fifo_init(struct nvkm_object *);
void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
View file @ 05c7145d
......@@ -21,20 +21,15 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include <core/client.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
#include <core/engctx.h>
#include <core/ramht.h>
#include <subdev/instmem.h>
#include <subdev/instmem/nv04.h>
#include <subdev/fb.h>
#include <engine/fifo.h>
#include "nv04.h"
#include <nvif/class.h>
#include <nvif/unpack.h>
static struct ramfc_desc
nv10_ramfc[] = {
......@@ -55,10 +50,10 @@ nv10_ramfc[] = {
******************************************************************************/
static int
nv10_fifo_chan_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv10_fifo_chan_ctor(struct nvkm_object *parent,
struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
......@@ -75,11 +70,11 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent,
} else
return ret;
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
0x10000, args->v0.pushbuf,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR), &chan);
ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
0x10000, args->v0.pushbuf,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
......@@ -104,19 +99,19 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent,
return 0;
}
static struct nouveau_ofuncs
static struct nvkm_ofuncs
nv10_fifo_ofuncs = {
.ctor = nv10_fifo_chan_ctor,
.dtor = nv04_fifo_chan_dtor,
.init = nv04_fifo_chan_init,
.fini = nv04_fifo_chan_fini,
.map = _nouveau_fifo_channel_map,
.rd32 = _nouveau_fifo_channel_rd32,
.wr32 = _nouveau_fifo_channel_wr32,
.ntfy = _nouveau_fifo_channel_ntfy
.map = _nvkm_fifo_channel_map,
.rd32 = _nvkm_fifo_channel_rd32,
.wr32 = _nvkm_fifo_channel_wr32,
.ntfy = _nvkm_fifo_channel_ntfy
};
static struct nouveau_oclass
static struct nvkm_oclass
nv10_fifo_sclass[] = {
{ NV10_CHANNEL_DMA, &nv10_fifo_ofuncs },
{}
......@@ -126,16 +121,16 @@ nv10_fifo_sclass[] = {
* FIFO context - basically just the instmem reserved for the channel
******************************************************************************/
static struct nouveau_oclass
static struct nvkm_oclass
nv10_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fifo_context_ctor,
.dtor = _nouveau_fifo_context_dtor,
.init = _nouveau_fifo_context_init,
.fini = _nouveau_fifo_context_fini,
.rd32 = _nouveau_fifo_context_rd32,
.wr32 = _nouveau_fifo_context_wr32,
.dtor = _nvkm_fifo_context_dtor,
.init = _nvkm_fifo_context_init,
.fini = _nvkm_fifo_context_fini,
.rd32 = _nvkm_fifo_context_rd32,
.wr32 = _nvkm_fifo_context_wr32,
},
};
......@@ -144,22 +139,22 @@ nv10_fifo_cclass = {
******************************************************************************/
static int
nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv04_instmem_priv *imem = nv04_instmem(parent);
struct nv04_fifo_priv *priv;
int ret;
ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nouveau_ramht_ref(imem->ramht, &priv->ramht);
nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
nvkm_ramht_ref(imem->ramht, &priv->ramht);
nvkm_gpuobj_ref(imem->ramro, &priv->ramro);
nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc);
nv_subdev(priv)->unit = 0x00000100;
nv_subdev(priv)->intr = nv04_fifo_intr;
......@@ -171,13 +166,13 @@ nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass *
nv10_fifo_oclass = &(struct nouveau_oclass) {
struct nvkm_oclass *
nv10_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_fifo_ctor,
.dtor = nv04_fifo_dtor,
.init = nv04_fifo_init,
.fini = _nouveau_fifo_fini,
.fini = _nvkm_fifo_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
View file @ 05c7145d
......@@ -21,20 +21,15 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include <core/client.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
#include <core/engctx.h>
#include <core/ramht.h>
#include <subdev/instmem.h>
#include <subdev/instmem/nv04.h>
#include <subdev/fb.h>
#include <engine/fifo.h>
#include "nv04.h"
#include <nvif/class.h>
#include <nvif/unpack.h>
static struct ramfc_desc
nv17_ramfc[] = {
......@@ -60,10 +55,10 @@ nv17_ramfc[] = {
******************************************************************************/
static int
nv17_fifo_chan_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv17_fifo_chan_ctor(struct nvkm_object *parent,
struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
......@@ -80,13 +75,13 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent,
} else
return ret;
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
0x10000, args->v0.pushbuf,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG), /* NV31- */
&chan);
ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
0x10000, args->v0.pushbuf,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG), /* NV31- */
&chan);
*pobject = nv_object(chan);
if (ret)
return ret;
......@@ -111,19 +106,19 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent,
return 0;
}
static struct nouveau_ofuncs
static struct nvkm_ofuncs
nv17_fifo_ofuncs = {
.ctor = nv17_fifo_chan_ctor,
.dtor = nv04_fifo_chan_dtor,
.init = nv04_fifo_chan_init,
.fini = nv04_fifo_chan_fini,
.map = _nouveau_fifo_channel_map,
.rd32 = _nouveau_fifo_channel_rd32,
.wr32 = _nouveau_fifo_channel_wr32,
.ntfy = _nouveau_fifo_channel_ntfy
.map = _nvkm_fifo_channel_map,
.rd32 = _nvkm_fifo_channel_rd32,
.wr32 = _nvkm_fifo_channel_wr32,
.ntfy = _nvkm_fifo_channel_ntfy
};
static struct nouveau_oclass
static struct nvkm_oclass
nv17_fifo_sclass[] = {
{ NV17_CHANNEL_DMA, &nv17_fifo_ofuncs },
{}
......@@ -133,16 +128,16 @@ nv17_fifo_sclass[] = {
* FIFO context - basically just the instmem reserved for the channel
******************************************************************************/
static struct nouveau_oclass
static struct nvkm_oclass
nv17_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x17),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fifo_context_ctor,
.dtor = _nouveau_fifo_context_dtor,
.init = _nouveau_fifo_context_init,
.fini = _nouveau_fifo_context_fini,
.rd32 = _nouveau_fifo_context_rd32,
.wr32 = _nouveau_fifo_context_wr32,
.dtor = _nvkm_fifo_context_dtor,
.init = _nvkm_fifo_context_init,
.fini = _nvkm_fifo_context_fini,
.rd32 = _nvkm_fifo_context_rd32,
.wr32 = _nvkm_fifo_context_wr32,
},
};
......@@ -151,22 +146,22 @@ nv17_fifo_cclass = {
******************************************************************************/
static int
nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv04_instmem_priv *imem = nv04_instmem(parent);
struct nv04_fifo_priv *priv;
int ret;
ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nouveau_ramht_ref(imem->ramht, &priv->ramht);
nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
nvkm_ramht_ref(imem->ramht, &priv->ramht);
nvkm_gpuobj_ref(imem->ramro, &priv->ramro);
nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc);
nv_subdev(priv)->unit = 0x00000100;
nv_subdev(priv)->intr = nv04_fifo_intr;
......@@ -179,12 +174,12 @@ nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
nv17_fifo_init(struct nouveau_object *object)
nv17_fifo_init(struct nvkm_object *object)
{
struct nv04_fifo_priv *priv = (void *)object;
int ret;
ret = nouveau_fifo_init(&priv->base);
ret = nvkm_fifo_init(&priv->base);
if (ret)
return ret;
......@@ -208,13 +203,13 @@ nv17_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass *
nv17_fifo_oclass = &(struct nouveau_oclass) {
struct nvkm_oclass *
nv17_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x17),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv17_fifo_ctor,
.dtor = nv04_fifo_dtor,
.init = nv17_fifo_init,
.fini = _nouveau_fifo_fini,
.fini = _nvkm_fifo_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View file @ 05c7145d
......@@ -21,21 +21,17 @@
*
* Authors: Ben Skeggs
*/
#include "nv04.h"
#include <core/client.h>
#include <core/device.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
#include <core/engctx.h>
#include <core/ramht.h>
#include <subdev/instmem.h>
#include <subdev/instmem/nv04.h>
#include <subdev/fb.h>
#include <subdev/instmem/nv04.h>
#include <engine/fifo.h>
#include "nv04.h"
#include <nvif/class.h>
#include <nvif/unpack.h>
static struct ramfc_desc
nv40_ramfc[] = {
......@@ -69,8 +65,8 @@ nv40_ramfc[] = {
******************************************************************************/
static int
nv40_fifo_object_attach(struct nouveau_object *parent,
struct nouveau_object *object, u32 handle)
nv40_fifo_object_attach(struct nvkm_object *parent,
struct nvkm_object *object, u32 handle)
{
struct nv04_fifo_priv *priv = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
......@@ -100,14 +96,13 @@ nv40_fifo_object_attach(struct nouveau_object *parent,
context |= chid << 23;
mutex_lock(&nv_subdev(priv)->mutex);
ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
ret = nvkm_ramht_insert(priv->ramht, chid, handle, context);
mutex_unlock(&nv_subdev(priv)->mutex);
return ret;
}
static int
nv40_fifo_context_attach(struct nouveau_object *parent,
struct nouveau_object *engctx)
nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx)
{
struct nv04_fifo_priv *priv = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
......@@ -143,8 +138,8 @@ nv40_fifo_context_attach(struct nouveau_object *parent,
}
static int
nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend,
struct nouveau_object *engctx)
nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend,
struct nvkm_object *engctx)
{
struct nv04_fifo_priv *priv = (void *)parent->engine;
struct nv04_fifo_chan *chan = (void *)parent;
......@@ -179,10 +174,9 @@ nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend,
}
static int
nv40_fifo_chan_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
union {
struct nv03_channel_dma_v0 v0;
......@@ -199,12 +193,12 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent,
} else
return ret;
ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
0x1000, args->v0.pushbuf,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG), &chan);
ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
0x1000, args->v0.pushbuf,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_SW) |
(1ULL << NVDEV_ENGINE_GR) |
(1ULL << NVDEV_ENGINE_MPEG), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
......@@ -231,19 +225,19 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent,
return 0;
}
static struct nouveau_ofuncs
static struct nvkm_ofuncs
nv40_fifo_ofuncs = {
.ctor = nv40_fifo_chan_ctor,
.dtor = nv04_fifo_chan_dtor,
.init = nv04_fifo_chan_init,
.fini = nv04_fifo_chan_fini,
.map = _nouveau_fifo_channel_map,
.rd32 = _nouveau_fifo_channel_rd32,
.wr32 = _nouveau_fifo_channel_wr32,
.ntfy = _nouveau_fifo_channel_ntfy
.map = _nvkm_fifo_channel_map,
.rd32 = _nvkm_fifo_channel_rd32,
.wr32 = _nvkm_fifo_channel_wr32,
.ntfy = _nvkm_fifo_channel_ntfy
};
static struct nouveau_oclass
static struct nvkm_oclass
nv40_fifo_sclass[] = {
{ NV40_CHANNEL_DMA, &nv40_fifo_ofuncs },
{}
......@@ -253,16 +247,16 @@ nv40_fifo_sclass[] = {
* FIFO context - basically just the instmem reserved for the channel
******************************************************************************/
static struct nouveau_oclass
static struct nvkm_oclass
nv40_fifo_cclass = {
.handle = NV_ENGCTX(FIFO, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_fifo_context_ctor,
.dtor = _nouveau_fifo_context_dtor,
.init = _nouveau_fifo_context_init,
.fini = _nouveau_fifo_context_fini,
.rd32 = _nouveau_fifo_context_rd32,
.wr32 = _nouveau_fifo_context_wr32,
.dtor = _nvkm_fifo_context_dtor,
.init = _nvkm_fifo_context_init,
.fini = _nvkm_fifo_context_fini,
.rd32 = _nvkm_fifo_context_rd32,
.wr32 = _nvkm_fifo_context_wr32,
},
};
......@@ -271,22 +265,22 @@ nv40_fifo_cclass = {
******************************************************************************/
static int
nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv04_instmem_priv *imem = nv04_instmem(parent);
struct nv04_fifo_priv *priv;
int ret;
ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nouveau_ramht_ref(imem->ramht, &priv->ramht);
nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
nvkm_ramht_ref(imem->ramht, &priv->ramht);
nvkm_gpuobj_ref(imem->ramro, &priv->ramro);
nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc);
nv_subdev(priv)->unit = 0x00000100;
nv_subdev(priv)->intr = nv04_fifo_intr;
......@@ -299,13 +293,13 @@ nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
static int
nv40_fifo_init(struct nouveau_object *object)
nv40_fifo_init(struct nvkm_object *object)
{
struct nv04_fifo_priv *priv = (void *)object;
struct nouveau_fb *pfb = nouveau_fb(object);
struct nvkm_fb *pfb = nvkm_fb(object);
int ret;
ret = nouveau_fifo_init(&priv->base);
ret = nvkm_fifo_init(&priv->base);
if (ret)
return ret;
......@@ -350,13 +344,13 @@ nv40_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass *
nv40_fifo_oclass = &(struct nouveau_oclass) {
struct nvkm_oclass *
nv40_fifo_oclass = &(struct nvkm_oclass) {
.handle = NV_ENGINE(FIFO, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_fifo_ctor,
.dtor = nv04_fifo_dtor,
.init = nv40_fifo_init,
.fini = _nouveau_fifo_fini,
.fini = _nvkm_fifo_fini,
},
};
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
View file @ 05c7145d
#ifndef __NV50_FIFO_H__
#define __NV50_FIFO_H__
#include <engine/fifo.h>
struct nv50_fifo_priv {
struct nouveau_fifo base;
struct nouveau_gpuobj *playlist[2];
struct nvkm_fifo base;
struct nvkm_gpuobj *playlist[2];
int cur_playlist;
};
struct nv50_fifo_base {
struct nouveau_fifo_base base;
struct nouveau_gpuobj *ramfc;
struct nouveau_gpuobj *cache;
struct nouveau_gpuobj *eng;
struct nouveau_gpuobj *pgd;
struct nouveau_vm *vm;
struct nvkm_fifo_base base;
struct nvkm_gpuobj *ramfc;
struct nvkm_gpuobj *cache;
struct nvkm_gpuobj *eng;
struct nvkm_gpuobj *pgd;
struct nvkm_vm *vm;
};
struct nv50_fifo_chan {
struct nouveau_fifo_chan base;
struct nvkm_fifo_chan base;
u32 subc[8];
struct nouveau_ramht *ramht;
struct nvkm_ramht *ramht;
};
void nv50_fifo_playlist_update(struct nv50_fifo_priv *);
void nv50_fifo_object_detach(struct nouveau_object *, int);
void nv50_fifo_chan_dtor(struct nouveau_object *);
int nv50_fifo_chan_fini(struct nouveau_object *, bool);
void nv50_fifo_object_detach(struct nvkm_object *, int);
void nv50_fifo_chan_dtor(struct nvkm_object *);
int nv50_fifo_chan_fini(struct nvkm_object *, bool);
void nv50_fifo_context_dtor(struct nouveau_object *);
void nv50_fifo_dtor(struct nouveau_object *);
int nv50_fifo_init(struct nouveau_object *);
void nv50_fifo_context_dtor(struct nvkm_object *);
void nv50_fifo_dtor(struct nvkm_object *);
int nv50_fifo_init(struct nvkm_object *);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.h deleted 100644 → 0
View file @ 5b85057a
#ifndef __NVKM_FIFO_NVE0_H__
#define __NVKM_FIFO_NVE0_H__
#include <engine/fifo.h>
int nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void nve0_fifo_dtor(struct nouveau_object *);
int nve0_fifo_init(struct nouveau_object *);
int nve0_fifo_fini(struct nouveau_object *, bool);
struct nve0_fifo_impl {
struct nouveau_oclass base;
u32 channels;
};
#endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7