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Commit 07b75260 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS for 4.7.  Here's the summary of
  the changes:

   - ATH79: Support for DTB passuing using the UHI boot protocol
   - ATH79: Remove support for builtin DTB.
   - ATH79: Add zboot debug serial support.
   - ATH79: Add initial support for Dragino MS14 (Dragine 2), Onion Omega
            and DPT-Module.
   - ATH79: Update devicetree clock support for AR9132 and AR9331.
   - ATH79: Cleanup the DT code.
   - ATH79: Support newer SOCs in ath79_ddr_ctrl_init.
   - ATH79: Fix regression in PCI window initialization.
   - BCM47xx: Move SPROM driver to drivers/firmware/
   - BCM63xx: Enable partition parser in defconfig.
   - BMIPS: BMIPS5000 has I cache filing from D cache
   - BMIPS: BMIPS: Add cpu-feature-overrides.h
   - BMIPS: Add Whirlwind support
   - BMIPS: Adjust mips-hpt-frequency for BCM7435
   - BMIPS: Remove maxcpus from BCM97435SVMB DTS
   - BMIPS: Add missing 7038 L1 register cells to BCM7435
   - BMIPS: Various tweaks to initialization code.
   - BMIPS: Enable partition parser in defconfig.
   - BMIPS: Cache tweaks.
   - BMIPS: Add UART, I2C and SATA devices to DT.
   - BMIPS: Add BCM6358 and BCM63268support
   - BMIPS: Add device tree example for BCM6358.
   - BMIPS: Improve Improve BCM6328 and BCM6368 device trees
   - Lantiq: Add support for device tree file from boot loader
   - Lantiq: Allow build with no built-in DT.
   - Loongson 3: Reserve 32MB for RS780E integrated GPU.
   - Loongson 3: Fix build error after ld-version.sh modification
   - Loongson 3: Move chipset ACPI code from drivers to arch.
   - Loongson 3: Speedup irq processing.
   - Loongson 3: Add basic Loongson 3A support.
   - Loongson 3: Set cache flush handlers to nop.
   - Loongson 3: Invalidate special TLBs when needed.
   - Loongson 3: Fast TLB refill handler.
   - MT7620: Fallback strategy for invalid syscfg0.
   - Netlogic: Fix CP0_EBASE redefinition warnings
   - Octeon: Initialization fixes
   - Octeon: Add DTS files for the D-Link DSR-1000N and EdgeRouter Lite
   - Octeon: Enable add Octeon-drivers in cavium_octeon_defconfig
   - Octeon: Correctly handle endian-swapped initramfs images.
   - Octeon: Support CN73xx, CN75xx and CN78xx.
   - Octeon: Remove dead code from cvmx-sysinfo.
   - Octeon: Extend number of supported CPUs past 32.
   - Octeon: Remove some code limiting NR_IRQS to 255.
   - Octeon: Simplify octeon_irq_ciu_gpio_set_type.
   - Octeon: Mark some functions __init in smp.c
   - Octeon: Octeon: Add Octeon III CN7xxx interface detection
   - PIC32: Add serial driver and bindings for it.
   - PIC32: Add PIC32 deadman timer driver and bindings.
   - PIC32: Add PIC32 clock timer driver and bindings.
   - Pistachio: Determine SoC revision during boot
   - Sibyte: Fix Kconfig dependencies of SIBYTE_BUS_WATCHER.
   - Sibyte: Strip redundant comments from bcm1480_regs.h.
   - Panic immediately if panic_on_oops is set.
   - module: fix incorrect IS_ERR_VALUE macro usage.
   - module: Make consistent use of pr_*
   - Remove no longer needed work_on_cpu() call.
   - Remove CONFIG_IPV6_PRIVACY from defconfigs.
   - Fix registers of non-crashing CPUs in dumps.
   - Handle MIPSisms in new vmcore_elf32_check_arch.
   - Select CONFIG_HANDLE_DOMAIN_IRQ and make it work.
   - Allow RIXI to be used on non-R2 or R6 cores.
   - Reserve nosave data for hibernation
   - Fix siginfo.h to use strict POSIX types.
   - Don't unwind user mode with EVA.
   - Fix watchpoint restoration
   - Ptrace watchpoints for R6.
   - Sync icache when it fills from dcache
   - I6400 I-cache fills from dcache.
   - Various MSA fixes.
   - Cleanup MIPS_CPU_* definitions.
   - Signal: Move generic copy_siginfo to signal.h
   - Signal: Fix uapi include in exported asm/siginfo.h
   - Timer fixes for sake of KVM.
   - XPA TLB refill fixes.
   - Treat perf counter feature
   - Update John Crispin's email address
   - Add PIC32 watchdog and bindings.
   - Handle R10000 LL/SC bug in set_pte()
   - cpufreq: Various fixes for Longson1.
   - R6: Fix R2 emulation.
   - mathemu: Cosmetic fix to ADDIUPC emulation, plenty of other small fixes
   - ELF: ABI and FP fixes.
   - Allow for relocatable kernel and use that to support KASLR.
   - Fix CPC_BASE_ADDR mask
   - Plenty fo smp-cps, CM, R6 and M6250 fixes.
   - Make reset_control_ops const.
   - Fix kernel command line handling of leading whitespace.
   - Cleanups to cache handling.
   - Add brcm, bcm6345-l1-intc device tree bindings.
   - Use generic clkdev.h header
   - Remove CLK_IS_ROOT usage.
   - Misc small cleanups.
   - CM: Fix compilation error when !MIPS_CM
   - oprofile: Fix a preemption issue
   - Detect DSP ASE v3 support:1"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (275 commits)
  MIPS: pic32mzda: fix getting timer clock rate.
  MIPS: ath79: fix regression in PCI window initialization
  MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer SoCs
  MIPS: Fix VZ probe gas errors with binutils <2.24
  MIPS: perf: Fix I6400 event numbers
  MIPS: DEC: Export `ioasic_ssr_lock' to modules
  MIPS: MSA: Fix a link error on `_init_msa_upper' with older GCC
  MIPS: CM: Fix compilation error when !MIPS_CM
  MIPS: Fix genvdso error on rebuild
  USB: ohci-jz4740: Remove obsolete driver
  MIPS: JZ4740: Probe OHCI platform device via DT
  MIPS: JZ4740: Qi LB60: Remove support for AVT2 variant
  MIPS: pistachio: Determine SoC revision during boot
  MIPS: BMIPS: Adjust mips-hpt-frequency for BCM7435
  mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type
  MIPS: Prevent "restoration" of MSA context in non-MSA kernels
  MIPS: cevt-r4k: Dynamically calculate min_delta_ns
  MIPS: malta-time: Take seconds into account
  MIPS: malta-time: Start GIC count before syncing to RTC
  MIPS: Force CPUs to lose FP context during mode switches
  ...
parents 0efacbba 6e4ad1b4
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Documentation/devicetree/bindings/clock/microchip,pic32.txt 0 → 100644
View file @ 07b75260
Microchip PIC32 Clock Controller Binding
----------------------------------------
Microchip clock controller is consists of few oscillators, PLL, multiplexer
and few divider modules.
This binding uses common clock bindings.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: shall be "microchip,pic32mzda-clk".
- reg: shall contain base address and length of clock registers.
- #clock-cells: shall be 1.
Optional properties:
- microchip,pic32mzda-sosc: shall be added only if platform has
secondary oscillator connected.
Example:
rootclk: clock-controller@1f801200 {
compatible = "microchip,pic32mzda-clk";
reg = <0x1f801200 0x200>;
#clock-cells = <1>;
/* optional */
microchip,pic32mzda-sosc;
};
The clock consumer shall specify the desired clock-output of the clock
controller (as defined in [2]) by specifying output-id in its "clock"
phandle cell.
[2] include/dt-bindings/clock/microchip,pic32-clock.h
For example for UART2:
uart2: serial@2 {
compatible = "microchip,pic32mzda-uart";
reg = <>;
interrupts = <>;
clocks = <&rootclk PB2CLK>;
};
Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt 0 → 100644
View file @ 07b75260
Broadcom BCM6345-style Level 1 interrupt controller
This block is a first level interrupt controller that is typically connected
directly to one of the HW INT lines on each CPU.
Key elements of the hardware design include:
- 32, 64 or 128 incoming level IRQ lines
- Most onchip peripherals are wired directly to an L1 input
- A separate instance of the register set for each CPU, allowing individual
peripheral IRQs to be routed to any CPU
- Contains one or more enable/status word pairs per CPU
- No atomic set/clear operations
- No polarity/level/edge settings
- No FIFO or priority encoder logic; software is expected to read all
2-4 status words to determine which IRQs are pending
Required properties:
- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
- reg: specifies the base physical address and size of the registers;
the number of supported IRQs is inferred from the size argument
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
- interrupt-parent: specifies the phandle to the parent interrupt controller(s)
this one is cascaded from
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
node; valid values depend on the type of parent interrupt controller
If multiple reg ranges and interrupt-parent entries are present on an SMP
system, the driver will allow IRQ SMP affinity to be set up through the
/proc/irq/ interface. In the simplest possible configuration, only one
reg range and one interrupt-parent is needed.
The driver operates in native CPU endian by default, there is no support for
specifying an alternative endianness.
Example:
periph_intc: interrupt-controller@10000000 {
compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x20>,
<0x10000040 0x20>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};
Documentation/devicetree/bindings/mips/brcm/soc.txt
View file @ 07b75260
......@@ -4,7 +4,8 @@ Required properties:
- compatible: "brcm,bcm3384", "brcm,bcm33843"
"brcm,bcm3384-viper", "brcm,bcm33843-viper"
"brcm,bcm6328", "brcm,bcm6368",
"brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6368",
"brcm,bcm63168", "brcm,bcm63268",
"brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
"brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"
......
Documentation/devicetree/bindings/mips/cavium/ciu3.txt 0 → 100644
View file @ 07b75260
* Central Interrupt Unit v3
Properties:
- compatible: "cavium,octeon-7890-ciu3"
Compatibility with 78XX and 73XX SOCs.
- interrupt-controller: This is an interrupt controller.
- reg: The base address of the CIU's register bank.
- #interrupt-cells: Must be <2>. The first cell is source number.
The second cell indicates the triggering semantics, and may have a
value of either 4 for level semantics, or 1 for edge semantics.
Example:
interrupt-controller@1010000000000 {
compatible = "cavium,octeon-7890-ciu3";
interrupt-controller;
/* Interrupts are specified by two parts:
* 1) Source number (20 significant bits)
* 2) Trigger type: (4 == level, 1 == edge)
*/
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x10100 0x00000000 0x0 0xb0000000>;
};
Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt 0 → 100644
View file @ 07b75260
* Microchip Universal Asynchronous Receiver Transmitter (UART)
Required properties:
- compatible: Should be "microchip,pic32mzda-uart"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt
- clocks: Phandle to the clock.
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- pinctrl-names: A pinctrl state names "default" must be defined.
- pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
Optional properties:
- cts-gpios: CTS pin for UART
Example:
uart1: serial@1f822000 {
compatible = "microchip,pic32mzda-uart";
reg = <0x1f822000 0x50>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
<113 IRQ_TYPE_LEVEL_HIGH>,
<114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1
&pinctrl_uart1_cts
&pinctrl_uart1_rts>;
cts-gpios = <&gpio1 15 0>;
};
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ 07b75260
......@@ -72,6 +72,8 @@ digilent Diglent, Inc.
dlg Dialog Semiconductor
dlink D-Link Corporation
dmo Data Modul AG
dptechnics DPTechnics
dragino Dragino Technology Co., Limited
ea Embedded Artists AB
ebv EBV Elektronik
edt Emerging Display Technologies
......@@ -176,6 +178,7 @@ nvidia NVIDIA
nxp NXP Semiconductors
okaya Okaya Electric America, Inc.
olimex OLIMEX Ltd.
onion Onion Corporation
onnn ON Semiconductor Corp.
opencores OpenCores.org
option Option NV
......
Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt 0 → 100644
View file @ 07b75260
* Microchip PIC32 Deadman Timer
The deadman timer is used to reset the processor in the event of a software
malfunction. It is a free-running instruction fetch timer, which is clocked
whenever an instruction fetch occurs until a count match occurs.
Required properties:
- compatible: must be "microchip,pic32mzda-dmt".
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: phandle of parent clock (should be &PBCLK7).
Example:
watchdog@1f800a00 {
compatible = "microchip,pic32mzda-dmt";
reg = <0x1f800a00 0x80>;
clocks = <&PBCLK7>;
};
Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt 0 → 100644
View file @ 07b75260
* Microchip PIC32 Watchdog Timer
When enabled, the watchdog peripheral can be used to reset the device if the
WDT is not cleared periodically in software.
Required properties:
- compatible: must be "microchip,pic32mzda-wdt".
- reg: physical base address of the controller and length of memory mapped
region.
- clocks: phandle of source clk. should be <&LPRC> clk.
Example:
watchdog@1f800800 {
compatible = "microchip,pic32mzda-wdt";
reg = <0x1f800800 0x200>;
clocks = <&LPRC>;
};
MAINTAINERS
View file @ 07b75260
......@@ -6491,7 +6491,7 @@ F: net/l3mdev
F: include/net/l3mdev.h
LANTIQ MIPS ARCHITECTURE
M: John Crispin <blogic@openwrt.org>
M: John Crispin <john@phrozen.org>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/lantiq
......@@ -7332,6 +7332,15 @@ S: Supported
F: Documentation/mips/
F: arch/mips/
MIPS/LOONGSON1 ARCHITECTURE
M: Keguang Zhang <keguang.zhang@gmail.com>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/loongson32/
F: arch/mips/include/asm/mach-loongson32/
F: drivers/*/*loongson1*
F: drivers/*/*/*loongson1*
MIROSOUND PCM20 FM RADIO RECEIVER DRIVER
M: Hans Verkuil <hverkuil@xs4all.nl>
L: linux-media@vger.kernel.org
......@@ -9251,7 +9260,7 @@ S: Maintained
F: drivers/video/fbdev/aty/aty128fb.c
RALINK MIPS ARCHITECTURE
M: John Crispin <blogic@openwrt.org>
M: John Crispin <john@phrozen.org>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/ralink
......
arch/mips/Kconfig
View file @ 07b75260
......@@ -62,6 +62,7 @@ config MIPS
select HAVE_IRQ_TIME_ACCOUNTING
select GENERIC_TIME_VSYSCALL
select ARCH_CLOCKSOURCE_DATA
select HANDLE_DOMAIN_IRQ
menu "Machine selection"
......@@ -137,7 +138,7 @@ config ATH79
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_ZBOOT
select SYS_SUPPORTS_ZBOOT_UART_PROM
select USE_OF
help
Support for the Atheros AR71XX/AR724X/AR913X SoCs.
......@@ -194,6 +195,7 @@ config BCM47XX
select GPIOLIB
select LEDS_GPIO_REGISTER
select BCM47XX_NVRAM
select BCM47XX_SPROM
help
Support for BCM47XX based boards
......@@ -471,6 +473,7 @@ config MIPS_MALTA
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_SMARTMIPS
select SYS_SUPPORTS_ZBOOT
select SYS_SUPPORTS_RELOCATABLE
select USE_OF
select ZONE_DMA32 if 64BIT
select BUILTIN_DTB
......@@ -505,6 +508,7 @@ config MIPS_SEAD3
select MIPS_MSC
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS32_R6
select SYS_HAS_CPU_MIPS64_R1
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
......@@ -514,6 +518,7 @@ config MIPS_SEAD3
select SYS_SUPPORTS_SMARTMIPS
select SYS_SUPPORTS_MICROMIPS
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_RELOCATABLE
select USB_EHCI_BIG_ENDIAN_DESC
select USB_EHCI_BIG_ENDIAN_MMIO
select USE_OF
......@@ -1153,6 +1158,13 @@ config ISA_DMA_API
config HOLES_IN_ZONE
bool
config SYS_SUPPORTS_RELOCATABLE
bool
help
Selected if the platform supports relocating the kernel.
The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
to allow access to command line and entropy sources.
#
# Endianness selection. Sufficiently obscure so many users don't know what to
# answer,so we try hard to limit the available choices. Also the use of a
......@@ -1340,11 +1352,30 @@ config CPU_LOONGSON3
select CPU_SUPPORTS_HUGEPAGES
select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC
select MIPS_PGD_C0_CONTEXT
select GPIOLIB
help
The Loongson 3 processor implements the MIPS64R2 instruction
set with many extensions.
config LOONGSON3_ENHANCEMENT
bool "New Loongson 3 CPU Enhancements"
default n
select CPU_MIPSR2
select CPU_HAS_PREFETCH
depends on CPU_LOONGSON3
help
New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
Fast TLB refill support, etc.
This option enable those enhancements which are not probed at run
time. If you want a generic kernel to run on all Loongson 3 machines,
please say 'N' here. If you want a high-performance kernel to run on
new Loongson 3 machines only, please say 'Y' here.
config CPU_LOONGSON2E
bool "Loongson 2E"
depends on SYS_HAS_CPU_LOONGSON2E
......@@ -1373,6 +1404,8 @@ config CPU_LOONGSON1B
bool "Loongson 1B"
depends on SYS_HAS_CPU_LOONGSON1B
select CPU_LOONGSON1
select ARCH_WANT_OPTIONAL_GPIOLIB
select LEDS_GPIO_REGISTER
help
The Loongson 1B is a 32-bit SoC, which implements the MIPS32
release 2 instruction set.
......@@ -1671,6 +1704,7 @@ config CPU_XLP
select CPU_HAS_PREFETCH
select CPU_MIPSR2
select CPU_SUPPORTS_HUGEPAGES
select MIPS_ASID_BITS_VARIABLE
help
Netlogic Microsystems XLP processors.
endchoice
......@@ -1796,6 +1830,7 @@ config CPU_BMIPS4380
select MIPS_L1_CACHE_SHIFT_6
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_HOTPLUG_CPU
select CPU_HAS_RIXI
config CPU_BMIPS5000
bool
......@@ -1803,10 +1838,12 @@ config CPU_BMIPS5000
select MIPS_L1_CACHE_SHIFT_7
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_HOTPLUG_CPU
select CPU_HAS_RIXI
config SYS_HAS_CPU_LOONGSON3
bool
select CPU_SUPPORTS_CPUFREQ
select CPU_HAS_RIXI
config SYS_HAS_CPU_LOONGSON2E
bool
......@@ -1959,11 +1996,15 @@ config CPU_MIPSR1
config CPU_MIPSR2
bool
default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
select CPU_HAS_RIXI
select MIPS_SPRAM
config CPU_MIPSR6
bool
default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
select CPU_HAS_RIXI
select HAVE_ARCH_BITREVERSE
select MIPS_ASID_BITS_VARIABLE
select MIPS_SPRAM
config EVA
......@@ -1997,7 +2038,7 @@ config MIPS_PGD_C0_CONTEXT
#
config HARDWARE_WATCHPOINTS
bool
default y if CPU_MIPSR1 || CPU_MIPSR2
default y if CPU_MIPSR1 || CPU_MIPSR2 || CPU_MIPSR6
menu "Kernel type"
......@@ -2040,6 +2081,16 @@ config KVM_GUEST_TIMER_FREQ
emulation when determining guest CPU Frequency. Instead, the guest's
timer frequency is specified directly.
config MIPS_VA_BITS_48
bool "48 bits virtual memory"
depends on 64BIT
help
Support a maximum at least 48 bits of application virtual memory.
Default is 40 bits or less, depending on the CPU.
This option result in a small memory overhead for page tables.
This option is only supported with 16k and 64k page sizes.
If unsure, say N.
choice
prompt "Kernel page size"
default PAGE_SIZE_4KB
......@@ -2047,6 +2098,7 @@ choice
config PAGE_SIZE_4KB
bool "4kB"
depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
depends on !MIPS_VA_BITS_48
help
This option select the standard 4kB Linux page size. On some
R3000-family processors this is the only available page size. Using
......@@ -2056,6 +2108,7 @@ config PAGE_SIZE_4KB
config PAGE_SIZE_8KB
bool "8kB"
depends on CPU_R8000 || CPU_CAVIUM_OCTEON
depends on !MIPS_VA_BITS_48
help
Using 8kB page size will result in higher performance kernel at
the price of higher memory consumption. This option is available
......@@ -2074,6 +2127,7 @@ config PAGE_SIZE_16KB
config PAGE_SIZE_32KB
bool "32kB"
depends on CPU_CAVIUM_OCTEON
depends on !MIPS_VA_BITS_48
help
Using 32kB page size will result in higher performance kernel at
the price of higher memory consumption. This option is available
......@@ -2278,7 +2332,7 @@ config MIPS_CMP
config MIPS_CPS
bool "MIPS Coherent Processing System support"
depends on SYS_SUPPORTS_MIPS_CPS && !CPU_MIPSR6
depends on SYS_SUPPORTS_MIPS_CPS
select MIPS_CM
select MIPS_CPC
select MIPS_CPS_PM if HOTPLUG_CPU
......@@ -2369,6 +2423,9 @@ config CPU_HAS_WB
config XKS01
bool
config CPU_HAS_RIXI
bool
#
# Vectored interrupt mode is an R2 feature
#
......@@ -2399,6 +2456,21 @@ config CPU_R4000_WORKAROUNDS
config CPU_R4400_WORKAROUNDS
bool
config MIPS_ASID_SHIFT
int
default 6 if CPU_R3000 || CPU_TX39XX
default 4 if CPU_R8000
default 0
config MIPS_ASID_BITS
int
default 0 if MIPS_ASID_BITS_VARIABLE
default 6 if CPU_R3000 || CPU_TX39XX
default 8
config MIPS_ASID_BITS_VARIABLE
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed
......@@ -2468,6 +2540,61 @@ config NUMA
config SYS_SUPPORTS_NUMA
bool
config RELOCATABLE
bool "Relocatable kernel"
depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6)
help
This builds a kernel image that retains relocation information
so it can be loaded someplace besides the default 1MB.
The relocations make the kernel binary about 15% larger,
but are discarded at runtime
config RELOCATION_TABLE_SIZE
hex "Relocation table size"
depends on RELOCATABLE
range 0x0 0x01000000
default "0x00100000"
---help---
A table of relocation data will be appended to the kernel binary
and parsed at boot to fix up the relocated kernel.
This option allows the amount of space reserved for the table to be
adjusted, although the default of 1Mb should be ok in most cases.
The build will fail and a valid size suggested if this is too small.
If unsure, leave at the default value.
config RANDOMIZE_BASE
bool "Randomize the address of the kernel image"
depends on RELOCATABLE
---help---
Randomizes the physical and virtual address at which the
kernel image is loaded, as a security feature that
deters exploit attempts relying on knowledge of the location
of kernel internals.
Entropy is generated using any coprocessor 0 registers available.
The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
If unsure, say N.
config RANDOMIZE_BASE_MAX_OFFSET
hex "Maximum kASLR offset" if EXPERT
depends on RANDOMIZE_BASE
range 0x0 0x40000000 if EVA || 64BIT
range 0x0 0x08000000
default "0x01000000"
---help---
When kASLR is active, this provides the maximum offset that will
be applied to the kernel image. It should be set according to the
amount of physical RAM available in the target system minus
PHYSICAL_START and must be a power of 2.
This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
EVA or 64-bit. The default is 16Mb.
config NODES_SHIFT
int
default "6"
......@@ -2475,7 +2602,7 @@ config NODES_SHIFT
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
depends on PERF_EVENTS && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP || CPU_LOONGSON3)
default y
help
Enable hardware performance counter support for perf events. If
......@@ -2808,6 +2935,10 @@ choice
config MIPS_CMDLINE_FROM_BOOTLOADER
bool "Bootloader kernel arguments if available"
config MIPS_CMDLINE_BUILTIN_EXTEND
depends on CMDLINE_BOOL
bool "Extend builtin kernel arguments with bootloader arguments"
endchoice
endmenu
......
arch/mips/Makefile
View file @ 07b75260
......@@ -12,6 +12,9 @@
# for "archclean" cleaning up for this architecture.
#
archscripts: scripts_basic
$(Q)$(MAKE) $(build)=arch/mips/boot/tools relocs
KBUILD_DEFCONFIG := ip22_defconfig
#
......@@ -93,6 +96,10 @@ LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
KBUILD_AFLAGS_MODULE += -mlong-calls
KBUILD_CFLAGS_MODULE += -mlong-calls
ifeq ($(CONFIG_RELOCATABLE),y)
LDFLAGS_vmlinux += --emit-relocs
endif
#
# pass -msoft-float to GAS if it supports it. However on newer binutils
# (specifically newer than 2.24.51.20140728) we then also need to explicitly
......@@ -193,6 +200,8 @@ ifeq ($(CONFIG_CPU_HAS_MSA),y)
toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa)
cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
endif
toolchain-virt := $(call cc-option-yn,$(mips-cflags) -mvirt)
cflags-$(toolchain-virt) += -DTOOLCHAIN_SUPPORTS_VIRT
cflags-$(CONFIG_MIPS_COMPACT_BRANCHES_NEVER) += -mcompact-branches=never
cflags-$(CONFIG_MIPS_COMPACT_BRANCHES_OPTIMAL) += -mcompact-branches=optimal
......@@ -310,6 +319,10 @@ rom.bin rom.sw: vmlinux
$(bootvars-y) $@
endif
CMD_RELOCS = arch/mips/boot/tools/relocs
quiet_cmd_relocs = RELOCS $<
cmd_relocs = $(CMD_RELOCS) $<
#
# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
......@@ -318,6 +331,11 @@ endif
quiet_cmd_32 = OBJCOPY $@
cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
vmlinux.32: vmlinux
ifeq ($(CONFIG_RELOCATABLE)$(CONFIG_64BIT),yy)
# Currently, objcopy fails to handle the relocations in the elf64
# So the relocs tool must be run here to remove them first
$(call cmd,relocs)
endif
$(call cmd,32)
#
......@@ -333,6 +351,9 @@ all: $(all-y)
# boot
$(boot-y): $(vmlinux-32) FORCE
ifeq ($(CONFIG_RELOCATABLE)$(CONFIG_32BIT),yy)
$(call cmd,relocs)
endif
$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
$(bootvars-y) arch/mips/boot/$@
......@@ -385,6 +406,7 @@ endif
archclean:
$(Q)$(MAKE) $(clean)=arch/mips/boot
$(Q)$(MAKE) $(clean)=arch/mips/boot/compressed
$(Q)$(MAKE) $(clean)=arch/mips/boot/tools
$(Q)$(MAKE) $(clean)=arch/mips/lasat
define archhelp
......
arch/mips/alchemy/common/clock.c
View file @ 07b75260
......@@ -1043,8 +1043,7 @@ static int __init alchemy_clk_init(void)
/* Root of the Alchemy clock tree: external 12MHz crystal osc */
c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL,
CLK_IS_ROOT,
ALCHEMY_ROOTCLK_RATE);
0, ALCHEMY_ROOTCLK_RATE);
ERRCK(c)
/* CPU core clock */
......
arch/mips/ath79/Kconfig
View file @ 07b75260
......@@ -71,18 +71,6 @@ config ATH79_MACH_UBNT_XM
Say 'Y' here if you want your kernel to support the
Ubiquiti Networks XM (rev 1.0) board.
choice
prompt "Build a DTB in the kernel"
optional
help
Select a devicetree that should be built into the kernel.
config DTB_TL_WR1043ND_V1
bool "TL-WR1043ND Version 1"
select BUILTIN_DTB
select SOC_AR913X
endchoice
endmenu
config SOC_AR71XX
......
arch/mips/ath79/clock.c
View file @ 07b75260
......@@ -18,17 +18,21 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/ath79-clk.h>
#include <asm/div64.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "machtypes.h"
#define AR71XX_BASE_FREQ 40000000
#define AR724X_BASE_FREQ 40000000
static struct clk *clks[3];
static struct clk *clks[ATH79_CLK_END];
static struct clk_onecell_data clk_data = {
.clks = clks,
.clk_num = ARRAY_SIZE(clks),
......@@ -40,7 +44,7 @@ static struct clk *__init ath79_add_sys_clkdev(
struct clk *clk;
int err;
clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
if (!clk)
panic("failed to allocate %s clock structure", id);
......@@ -78,107 +82,139 @@ static void __init ar71xx_clocks_init(void)
ahb_rate = cpu_rate / div;
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
}
static void __init ar724x_clocks_init(void)
static struct clk * __init ath79_reg_ffclk(const char *name,
const char *parent_name, unsigned int mult, unsigned int div)
{
unsigned long ref_rate;
unsigned long cpu_rate;
unsigned long ddr_rate;
unsigned long ahb_rate;
u32 pll;
u32 freq;
u32 div;
struct clk *clk;
ref_rate = AR724X_BASE_FREQ;
pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
if (!clk)
panic("failed to allocate %s clock structure", name);
div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
freq = div * ref_rate;
return clk;
}
static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
{
u32 pll;
u32 mult, div, ddr_div, ahb_div;
pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
freq /= div;
cpu_rate = freq;
ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
ddr_rate = freq / div;
clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
}
div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
ahb_rate = cpu_rate / div;
static void __init ar724x_clocks_init(void)
{
struct clk *ref_clk;
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
ar724x_clk_init(ref_clk, ath79_pll_base);
/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
}
static void __init ar933x_clocks_init(void)
static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
unsigned long ddr_rate;
unsigned long ahb_rate;
u32 clock_ctrl;
u32 cpu_config;
u32 freq;
u32 t;
u32 ref_div;
u32 ninit_mul;
u32 out_div;
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
ref_rate = (40 * 1000 * 1000);
else
ref_rate = (25 * 1000 * 1000);
u32 cpu_div;
u32 ddr_div;
u32 ahb_div;
clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
cpu_rate = ref_rate;
ahb_rate = ref_rate;
ddr_rate = ref_rate;
ref_div = 1;
ninit_mul = 1;
out_div = 1;
cpu_div = 1;
ddr_div = 1;
ahb_div = 1;
} else {
cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
u32 cpu_config;
u32 t;
cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
freq = ref_rate / t;
ref_div = t;
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
AR933X_PLL_CPU_CONFIG_NINT_MASK;
freq *= t;
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
if (t == 0)
t = 1;
freq >>= t;
out_div = (1 << t);
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
cpu_rate = freq / t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
ddr_rate = freq / t;
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
ahb_rate = freq / t;
}
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
ninit_mul, ref_div * out_div * cpu_div);
clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
ninit_mul, ref_div * out_div * ddr_div);
clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
ninit_mul, ref_div * out_div * ahb_div);
}
static void __init ar933x_clocks_init(void)
{
struct clk *ref_clk;
unsigned long ref_rate;
u32 t;
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
ref_rate = (40 * 1000 * 1000);
else
ref_rate = (25 * 1000 * 1000);
ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
ar9330_clk_init(ref_clk, ath79_pll_base);
/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
......@@ -310,9 +346,9 @@ static void __init ar934x_clocks_init(void)
ahb_rate = cpu_pll / (postdiv + 1);
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
......@@ -397,9 +433,9 @@ static void __init qca955x_clocks_init(void)
ahb_rate = cpu_pll / (postdiv + 1);
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
......@@ -419,8 +455,6 @@ void __init ath79_clocks_init(void)
qca955x_clocks_init();
else
BUG();
of_clk_init(NULL);
}
unsigned long __init
......@@ -447,8 +481,49 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
static void __init ath79_clocks_init_dt_ng(struct device_node *np)
{
struct clk *ref_clk;
void __iomem *pll_base;
const char *dnfn = of_node_full_name(np);
ref_clk = of_clk_get(np, 0);
if (IS_ERR(ref_clk)) {
pr_err("%s: of_clk_get failed\n", dnfn);
goto err;
}
pll_base = of_iomap(np, 0);
if (!pll_base) {
pr_err("%s: can't map pll registers\n", dnfn);
goto err_clk;
}
if (of_device_is_compatible(np, "qca,ar9130-pll"))
ar724x_clk_init(ref_clk, pll_base);
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
ar9330_clk_init(ref_clk, pll_base);
else {
pr_err("%s: could not find any appropriate clk_init()\n", dnfn);
goto err_clk;
}
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%s: could not register clk provider\n", dnfn);
goto err_clk;
}
return;
err_clk:
clk_put(ref_clk);
err:
return;
}
CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
#endif
arch/mips/ath79/common.c
View file @ 07b75260
......@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void)
{
ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
AR71XX_DDR_CTRL_SIZE);
if (soc_is_ar71xx() || soc_is_ar934x()) {
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
} else {
if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
ath79_ddr_pci_win_base = 0;
} else {
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
}
}
EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
......@@ -76,14 +76,14 @@ void ath79_ddr_set_pci_windows(void)
{
BUG_ON(!ath79_ddr_pci_win_base);
__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0);
__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1);
__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2);
__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3);
__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4);
__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5);
__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6);
__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7);
__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
}
EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
......
arch/mips/ath79/setup.c
View file @ 07b75260
......@@ -17,6 +17,7 @@
#include <linux/bootmem.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_platform.h>
#include <linux/of_fdt.h>
......@@ -203,26 +204,57 @@ void __init plat_mem_setup(void)
fdt_start = fw_getenvl("fdt_start");
if (fdt_start)
__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
#ifdef CONFIG_BUILTIN_DTB
else
__dt_setup_arch(__dtb_start);
#endif
else if (fw_arg0 == -2)
__dt_setup_arch((void *)KSEG0ADDR(fw_arg1));
ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE);
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE);
ath79_detect_sys_type();
ath79_ddr_ctrl_init();
if (mips_machtype != ATH79_MACH_GENERIC_OF) {
ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE);
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE);
ath79_detect_sys_type();
ath79_ddr_ctrl_init();
if (mips_machtype != ATH79_MACH_GENERIC_OF)
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
_machine_restart = ath79_restart;
/* OF machines should use the reset driver */
_machine_restart = ath79_restart;
}
_machine_halt = ath79_halt;
pm_power_off = ath79_halt;
}
static void __init ath79_of_plat_time_init(void)
{
struct device_node *np;
struct clk *clk;
unsigned long cpu_clk_rate;
of_clk_init(NULL);
np = of_get_cpu_node(0, NULL);
if (!np) {
pr_err("Failed to get CPU node\n");
return;
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
return;
}
cpu_clk_rate = clk_get_rate(clk);
pr_info("CPU clock: %lu.%03lu MHz\n",
cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
mips_hpt_frequency = cpu_clk_rate / 2;
clk_put(clk);
}
void __init plat_time_init(void)
{
unsigned long cpu_clk_rate;
......@@ -230,6 +262,11 @@ void __init plat_time_init(void)
unsigned long ddr_clk_rate;
unsigned long ref_clk_rate;
if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
ath79_of_plat_time_init();
return;
}
ath79_clocks_init();
cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
......
arch/mips/bcm47xx/Makefile
View file @ 07b75260
......@@ -3,5 +3,5 @@
# under Linux.
#
obj-y += irq.o prom.o serial.o setup.o time.o sprom.o
obj-y += irq.o prom.o serial.o setup.o time.o
obj-y += board.o buttons.o leds.o workarounds.o
arch/mips/bcm47xx/bcm47xx_private.h
View file @ 07b75260
......@@ -10,9 +10,6 @@
/* prom.c */
void __init bcm47xx_prom_highmem_init(void);
/* sprom.c */
void bcm47xx_sprom_register_fallbacks(void);
/* buttons.c */
int __init bcm47xx_buttons_register(void);
......
arch/mips/bcm47xx/setup.c
View file @ 07b75260
......@@ -28,6 +28,7 @@
#include "bcm47xx_private.h"
#include <linux/bcm47xx_sprom.h>
#include <linux/export.h>
#include <linux/types.h>
#include <linux/ethtool.h>
......@@ -151,7 +152,6 @@ void __init plat_mem_setup(void)
pr_info("Using bcma bus\n");
#ifdef CONFIG_BCM47XX_BCMA
bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
bcm47xx_sprom_register_fallbacks();
bcm47xx_register_bcma();
bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id);
#ifdef CONFIG_HIGHMEM
......
arch/mips/bmips/Kconfig
View file @ 07b75260
......@@ -21,6 +21,10 @@ config DT_BCM93384WVG_VIPER
bool "BCM93384WVG Viper CPU (EXPERIMENTAL)"
select BUILTIN_DTB
config DT_BCM96358NB4SER
bool "BCM96358NB4SER"
select BUILTIN_DTB
config DT_BCM96368MVWG
bool "BCM96368MVWG"
select BUILTIN_DTB
......
arch/mips/bmips/setup.c
View file @ 07b75260
......@@ -95,6 +95,15 @@ static void bcm6328_quirks(void)
bcm63xx_fixup_cpu1();
}
static void bcm6358_quirks(void)
{
/*
* BCM6358 needs special handling for its shared TLB, so
* disable SMP for now
*/
bmips_smp_enabled = 0;
}
static void bcm6368_quirks(void)
{
bcm63xx_fixup_cpu1();
......@@ -104,13 +113,16 @@ static const struct bmips_quirk bmips_quirk_list[] = {
{ "brcm,bcm3384-viper", &bcm3384_viper_quirks },
{ "brcm,bcm33843-viper", &bcm3384_viper_quirks },
{ "brcm,bcm6328", &bcm6328_quirks },
{ "brcm,bcm6358", &bcm6358_quirks },
{ "brcm,bcm6368", &bcm6368_quirks },
{ "brcm,bcm63168", &bcm6368_quirks },
{ "brcm,bcm63268", &bcm6368_quirks },
{ },
};
void __init prom_init(void)
{
bmips_cpu_setup();
register_bmips_smp_ops();
}
......
arch/mips/boot/compressed/Makefile
View file @ 07b75260
......@@ -37,8 +37,13 @@ vmlinuzobjs-$(CONFIG_DEBUG_ZBOOT) += $(obj)/dbg.o
vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM) += $(obj)/uart-prom.o
vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
vmlinuzobjs-$(CONFIG_ATH79) += $(obj)/uart-ath79.o
endif
extra-y += uart-ath79.c
$(obj)/uart-ath79.c: $(srctree)/arch/mips/ath79/early_printk.c
$(call cmd,shipped)
vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o $(obj)/bswapsi.o
extra-y += ashldi3.c bswapsi.c
......
arch/mips/boot/dts/brcm/Makefile
View file @ 07b75260
dtb-$(CONFIG_DT_BCM93384WVG) += bcm93384wvg.dtb
dtb-$(CONFIG_DT_BCM93384WVG_VIPER) += bcm93384wvg_viper.dtb
dtb-$(CONFIG_DT_BCM96358NB4SER) += bcm96358nb4ser.dtb
dtb-$(CONFIG_DT_BCM96368MVWG) += bcm96368mvwg.dtb
dtb-$(CONFIG_DT_BCM9EJTAGPRB) += bcm9ejtagprb.dtb
dtb-$(CONFIG_DT_BCM97125CBMB) += bcm97125cbmb.dtb
......@@ -14,6 +15,7 @@ dtb-$(CONFIG_DT_BCM97435SVMB) += bcm97435svmb.dtb
dtb-$(CONFIG_DT_NONE) += \
bcm93384wvg.dtb \
bcm93384wvg_viper.dtb \
bcm96358nb4ser.dtb \
bcm96368mvwg.dtb \
bcm9ejtagprb.dtb \
bcm97125cbmb.dtb \
......
arch/mips/boot/dts/brcm/bcm6328.dtsi
View file @ 07b75260
......@@ -23,7 +23,7 @@ cpu@1 {
};
clocks {
periph_clk: periph_clk {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
......@@ -31,11 +31,11 @@ periph_clk: periph_clk {
};
aliases {
leds0 = &leds0;
uart0 = &uart0;
serial0 = &uart0;
serial1 = &uart1;
};
cpu_intc: cpu_intc {
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
......@@ -50,16 +50,16 @@ ubus {
compatible = "simple-bus";
ranges;
periph_intc: periph_intc@10000020 {
compatible = "brcm,bcm3380-l2-intc";
reg = <0x10000024 0x4 0x1000002c 0x4>,
<0x10000020 0x4 0x10000028 0x4>;
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,
<0x10000030 0x10>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
interrupts = <2>, <3>;
};
uart0: serial@10000100 {
......@@ -71,13 +71,22 @@ uart0: serial@10000100 {
status = "disabled";
};
timer: timer@10000040 {
uart1: serial@10000120 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000120 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <39>;
clocks = <&periph_clk>;
status = "disabled";
};
timer: syscon@10000040 {
compatible = "syscon";
reg = <0x10000040 0x2c>;
native-endian;
};
reboot {
reboot: syscon-reboot@10000068 {
compatible = "syscon-reboot";
regmap = <&timer>;
offset = <0x28>;
......@@ -91,5 +100,24 @@ leds0: led-controller@10000800 {
reg = <0x10000800 0x24>;
status = "disabled";
};
ehci: usb@10002500 {
compatible = "brcm,bcm6328-ehci", "generic-ehci";
reg = <0x10002500 0x100>;
big-endian;
interrupt-parent = <&periph_intc>;
interrupts = <42>;
status = "disabled";
};
ohci: usb@10002600 {
compatible = "brcm,bcm6328-ohci", "generic-ohci";
reg = <0x10002600 0x100>;
big-endian;
no-big-frame-no;
interrupt-parent = <&periph_intc>;
interrupts = <41>;
status = "disabled";
};
};
};
arch/mips/boot/dts/brcm/bcm6358.dtsi 0 → 100644
View file @ 07b75260
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6358";
cpus {
#address-cells = <1>;
#size-cells = <0>;
mips-hpt-frequency = <150000000>;
cpu@0 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <0>;
};
cpu@1 {
compatible = "brcm,bmips4350";
device_type = "cpu";
reg = <1>;
};
};
clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
ubus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
periph_cntl: syscon@fffe0000 {
compatible = "syscon";
reg = <0xfffe0000 0xc>;
native-endian;
};
reboot: syscon-reboot@fffe0008 {
compatible = "syscon-reboot";
regmap = <&periph_cntl>;
offset = <0x8>;
mask = <0x1>;
};
periph_intc: interrupt-controller@fffe000c {
compatible = "brcm,bcm6345-l1-intc";
reg = <0xfffe000c 0x8>,
<0xfffe0038 0x8>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
};
leds0: led-controller@fffe00d0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm6358-leds";
reg = <0xfffe00d0 0x8>;
status = "disabled";
};
uart0: serial@fffe0100 {
compatible = "brcm,bcm6345-uart";
reg = <0xfffe0100 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <2>;
clocks = <&periph_clk>;
status = "disabled";
};
uart1: serial@fffe0120 {
compatible = "brcm,bcm6345-uart";
reg = <0xfffe0120 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <3>;
clocks = <&periph_clk>;
status = "disabled";
};
ehci: usb@fffe1300 {
compatible = "brcm,bcm6358-ehci", "generic-ehci";
reg = <0xfffe1300 0x100>;
big-endian;
interrupt-parent = <&periph_intc>;
interrupts = <10>;
status = "disabled";
};
ohci: usb@fffe1400 {
compatible = "brcm,bcm6358-ohci", "generic-ohci";
reg = <0xfffe1400 0x100>;
big-endian;
no-big-frame-no;
interrupt-parent = <&periph_intc>;
interrupts = <5>;
status = "disabled";
};
};
};
arch/mips/boot/dts/brcm/bcm6368.dtsi
View file @ 07b75260
......@@ -20,11 +20,10 @@ cpu@1 {
device_type = "cpu";
reg = <1>;
};
};
clocks {
periph_clk: periph_clk {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
......@@ -32,11 +31,11 @@ periph_clk: periph_clk {
};
aliases {
leds0 = &leds0;
uart0 = &uart0;
serial0 = &uart0;
serial1 = &uart1;
};
cpu_intc: cpu_intc {
cpu_intc: interrupt-controller {
#address-cells = <0>;
compatible = "mti,cpu-interrupt-controller";
......@@ -64,16 +63,16 @@ reboot: syscon-reboot@10000008 {
mask = <0x1>;
};
periph_intc: periph_intc@10000020 {
compatible = "brcm,bcm3380-l2-intc";
reg = <0x10000024 0x4 0x1000002c 0x4>,
<0x10000020 0x4 0x10000028 0x4>;
periph_intc: interrupt-controller@10000020 {
compatible = "brcm,bcm6345-l1-intc";
reg = <0x10000020 0x10>,
<0x10000030 0x10>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>;
interrupts = <2>, <3>;
};
leds0: led-controller@100000d0 {
......@@ -93,7 +92,16 @@ uart0: serial@10000100 {
status = "disabled";
};
ehci0: usb@10001500 {
uart1: serial@10000120 {
compatible = "brcm,bcm6345-uart";
reg = <0x10000120 0x18>;
interrupt-parent = <&periph_intc>;
interrupts = <3>;
clocks = <&periph_clk>;
status = "disabled";
};
ehci: usb@10001500 {
compatible = "brcm,bcm6368-ehci", "generic-ehci";
reg = <0x10001500 0x100>;
big-endian;
......@@ -102,7 +110,7 @@ ehci0: usb@10001500 {
status = "disabled";
};
ohci0: usb@10001600 {
ohci: usb@10001600 {
compatible = "brcm,bcm6368-ohci", "generic-ohci";
reg = <0x10001600 0x100>;
big-endian;
......
arch/mips/boot/dts/brcm/bcm7125.dtsi
View file @ 07b75260
......@@ -85,14 +85,15 @@ upg_irq0_intc: upg_irq0_intc@406780 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
brcm,int-map-mask = <0x44>;
brcm,int-map-mask = <0x44>, <0xf000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <18>;
interrupts = <18>, <19>;
interrupt-names = "upg_main", "upg_bsc";
};
sun_top_ctrl: syscon@404000 {
......@@ -118,6 +119,70 @@ uart0: serial@406b00 {
status = "disabled";
};
uart1: serial@406b40 {
compatible = "ns16550a";
reg = <0x406b40 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <64>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406b80 {
compatible = "ns16550a";
reg = <0x406b80 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
native-endian;
interrupt-parent = <&periph_intc>;
interrupts = <65>;
clocks = <&uart_clk>;
status = "disabled";
};
bsca: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscc: i2c@406300 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406300 0x58>;
interrupts = <26>;
interrupt-names = "upg_bscc";
status = "disabled";
};
bscd: i2c@406380 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406380 0x58>;
interrupts = <27>;
interrupt-names = "upg_bscd";
status = "disabled";
};
ehci0: usb@488300 {
compatible = "brcm,bcm7125-ehci", "generic-ehci";
reg = <0x488300 0x100>;
......
arch/mips/boot/dts/brcm/bcm7346.dtsi
View file @ 07b75260
......@@ -24,8 +24,6 @@ cpu@1 {
aliases {
uart0 = &uart0;
uart1 = &uart1;
uart2 = &uart2;
};
cpu_intc: cpu_intc {
......@@ -323,8 +321,6 @@ sata: sata@181000 {
interrupts = <40>;
#address-cells = <1>;
#size-cells = <0>;
brcm,broken-ncq;
brcm,broken-phy;
status = "disabled";
sata0: sata-port@0 {
......@@ -338,7 +334,7 @@ sata1: sata-port@1 {
};
};
sata_phy: sata-phy@1800000 {
sata_phy: sata-phy@180100 {
compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
reg = <0x180100 0x0eff>;
reg-names = "phy";
......
arch/mips/boot/dts/brcm/bcm7358.dtsi
View file @ 07b75260
......@@ -18,8 +18,6 @@ cpu@0 {
aliases {
uart0 = &uart0;
uart1 = &uart1;
uart2 = &uart2;
};
cpu_intc: cpu_intc {
......
arch/mips/boot/dts/brcm/bcm7360.dtsi
View file @ 07b75260
......@@ -18,8 +18,6 @@ cpu@0 {
aliases {
uart0 = &uart0;
uart1 = &uart1;
uart2 = &uart2;
};
cpu_intc: cpu_intc {
......@@ -241,5 +239,45 @@ ohci0: usb@480400 {
interrupts = <66>;
status = "disabled";
};
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0x181000 0xa9c>, <0x180020 0x1c>;
interrupt-parent = <&periph_intc>;
interrupts = <86>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy1>;
};
};
sata_phy: sata-phy@180100 {
compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
reg = <0x180100 0x0eff>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
sata_phy1: sata-phy@1 {
reg = <1>;
#phy-cells = <0>;
};
};
};
};
arch/mips/boot/dts/brcm/bcm7362.dtsi
View file @ 07b75260
......@@ -24,8 +24,6 @@ cpu@1 {
aliases {
uart0 = &uart0;
uart1 = &uart1;
uart2 = &uart2;
};
cpu_intc: cpu_intc {
......@@ -246,8 +244,6 @@ sata: sata@181000 {
interrupts = <86>;
#address-cells = <1>;
#size-cells = <0>;
brcm,broken-ncq;
brcm,broken-phy;
status = "disabled";
sata0: sata-port@0 {
......@@ -261,7 +257,7 @@ sata1: sata-port@1 {
};
};
sata_phy: sata-phy@1800000 {
sata_phy: sata-phy@180100 {
compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
reg = <0x180100 0x0eff>;
reg-names = "phy";
......
arch/mips/boot/dts/brcm/bcm7420.dtsi
View file @ 07b75260
......@@ -86,14 +86,15 @@ upg_irq0_intc: upg_irq0_intc@406780 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
brcm,int-map-mask = <0x44>;
brcm,int-map-mask = <0x44>, <0x1f000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <18>;
interrupts = <18>, <19>;
interrupt-names = "upg_main", "upg_bsc";
};
sun_top_ctrl: syscon@404000 {
......@@ -118,6 +119,78 @@ uart0: serial@406b00 {
status = "disabled";
};
uart1: serial@406b40 {
compatible = "ns16550a";
reg = <0x406b40 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
interrupt-parent = <&periph_intc>;
interrupts = <64>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406b80 {
compatible = "ns16550a";
reg = <0x406b80 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
interrupt-parent = <&periph_intc>;
interrupts = <65>;
clocks = <&uart_clk>;
status = "disabled";
};
bsca: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscc: i2c@406300 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406300 0x58>;
interrupts = <26>;
interrupt-names = "upg_bscc";
status = "disabled";
};
bscd: i2c@406380 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406380 0x58>;
interrupts = <27>;
interrupt-names = "upg_bscd";
status = "disabled";
};
bsce: i2c@406800 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406800 0x58>;
interrupts = <28>;
interrupt-names = "upg_bsce";
status = "disabled";
};
enet0: ethernet@468000 {
phy-mode = "internal";
phy-handle = <&phy1>;
......
arch/mips/boot/dts/brcm/bcm7425.dtsi
View file @ 07b75260
......@@ -87,14 +87,32 @@ upg_irq0_intc: upg_irq0_intc@406780 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
brcm,int-map-mask = <0x44>;
brcm,int-map-mask = <0x44>, <0x7000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <55>;
interrupts = <55>, <53>;
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x409480 0x8>;
brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
brcm,int-fwd-mask = <0>;
brcm,irq-can-wake;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <56>, <54>, <59>;
interrupt-names = "upg_main_aon", "upg_bsc_aon",
"upg_spi";
};
sun_top_ctrl: syscon@404000 {
......@@ -119,6 +137,78 @@ uart0: serial@406b00 {
status = "disabled";
};
uart1: serial@406b40 {
compatible = "ns16550a";
reg = <0x406b40 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
interrupt-parent = <&periph_intc>;
interrupts = <62>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406b80 {
compatible = "ns16550a";
reg = <0x406b80 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
interrupt-parent = <&periph_intc>;
interrupts = <63>;
clocks = <&uart_clk>;
status = "disabled";
};
bsca: i2c@409180 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x409180 0x58>;
interrupts = <27>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@409400 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x409400 0x58>;
interrupts = <28>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscc: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bscc";
status = "disabled";
};
bscd: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscd";
status = "disabled";
};
bsce: i2c@406300 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406300 0x58>;
interrupts = <26>;
interrupt-names = "upg_bsce";
status = "disabled";
};
enet0: ethernet@b80000 {
phy-mode = "internal";
phy-handle = <&phy1>;
......@@ -227,11 +317,9 @@ sata: sata@181000 {
reg-names = "ahci", "top-ctrl";
reg = <0x181000 0xa9c>, <0x180020 0x1c>;
interrupt-parent = <&periph_intc>;
interrupts = <40>;
interrupts = <41>;
#address-cells = <1>;
#size-cells = <0>;
brcm,broken-ncq;
brcm,broken-phy;
status = "disabled";
sata0: sata-port@0 {
......@@ -245,7 +333,7 @@ sata1: sata-port@1 {
};
};
sata_phy: sata-phy@1800000 {
sata_phy: sata-phy@180100 {
compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
reg = <0x180100 0x0eff>;
reg-names = "phy";
......
arch/mips/boot/dts/brcm/bcm7435.dtsi
View file @ 07b75260
......@@ -7,7 +7,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
mips-hpt-frequency = <163125000>;
mips-hpt-frequency = <175625000>;
cpu@0 {
compatible = "brcm,bmips5200";
......@@ -63,13 +63,14 @@ rdb {
periph_intc: periph_intc@41b500 {
compatible = "brcm,bcm7038-l1-intc";
reg = <0x41b500 0x40>, <0x41b600 0x40>;
reg = <0x41b500 0x40>, <0x41b600 0x40>,
<0x41b700 0x40>, <0x41b800 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&cpu_intc>;
interrupts = <2>, <3>;
interrupts = <2>, <3>, <2>, <3>;
};
sun_l2_intc: sun_l2_intc@403000 {
......@@ -101,14 +102,32 @@ upg_irq0_intc: upg_irq0_intc@406780 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
brcm,int-map-mask = <0x44>;
brcm,int-map-mask = <0x44>, <0x7000000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <60>;
interrupts = <60>, <58>;
interrupt-names = "upg_main", "upg_bsc";
};
upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
compatible = "brcm,bcm7120-l2-intc";
reg = <0x409480 0x8>;
brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
brcm,int-fwd-mask = <0>;
brcm,irq-can-wake;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <61>, <59>, <64>;
interrupt-names = "upg_main_aon", "upg_bsc_aon",
"upg_spi";
};
sun_top_ctrl: syscon@404000 {
......@@ -133,6 +152,78 @@ uart0: serial@406b00 {
status = "disabled";
};
uart1: serial@406b40 {
compatible = "ns16550a";
reg = <0x406b40 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
interrupt-parent = <&periph_intc>;
interrupts = <67>;
clocks = <&uart_clk>;
status = "disabled";
};
uart2: serial@406b80 {
compatible = "ns16550a";
reg = <0x406b80 0x20>;
reg-io-width = <0x4>;
reg-shift = <0x2>;
interrupt-parent = <&periph_intc>;
interrupts = <68>;
clocks = <&uart_clk>;
status = "disabled";
};
bsca: i2c@406300 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406300 0x58>;
interrupts = <26>;
interrupt-names = "upg_bsca";
status = "disabled";
};
bscb: i2c@409400 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x409400 0x58>;
interrupts = <28>;
interrupt-names = "upg_bscb";
status = "disabled";
};
bscc: i2c@406200 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406200 0x58>;
interrupts = <24>;
interrupt-names = "upg_bscc";
status = "disabled";
};
bscd: i2c@406280 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_irq0_intc>;
reg = <0x406280 0x58>;
interrupts = <25>;
interrupt-names = "upg_bscd";
status = "disabled";
};
bsce: i2c@409180 {
clock-frequency = <390000>;
compatible = "brcm,brcmstb-i2c";
interrupt-parent = <&upg_aon_irq0_intc>;
reg = <0x409180 0x58>;
interrupts = <27>;
interrupt-names = "upg_bsce";
status = "disabled";
};
enet0: ethernet@b80000 {
phy-mode = "internal";
phy-handle = <&phy1>;
......@@ -235,5 +326,45 @@ ohci3: usb@490600 {
interrupts = <78>;
status = "disabled";
};
sata: sata@181000 {
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0x181000 0xa9c>, <0x180020 0x1c>;
interrupt-parent = <&periph_intc>;
interrupts = <45>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy1>;
};
};
sata_phy: sata-phy@180100 {
compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
reg = <0x180100 0x0eff>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
sata_phy1: sata-phy@1 {
reg = <1>;
#phy-cells = <0>;
};
};
};
};
arch/mips/boot/dts/brcm/bcm96358nb4ser.dts 0 → 100644
View file @ 07b75260
/dts-v1/;
/include/ "bcm6358.dtsi"
/ {
compatible = "sfr,nb4-ser", "brcm,bcm6358";
model = "SFR Neufbox 4 (Sercomm)";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x02000000>;
};
chosen {
stdout-path = &uart0;
};
};
&leds0 {
status = "ok";
led@0 {
reg = <0>;
active-low;
label = "nb4-ser:white:alarm";
};
led@2 {
reg = <2>;
active-low;
label = "nb4-ser:white:tv";
};
led@3 {
reg = <3>;
active-low;
label = "nb4-ser:white:tel";
};
led@4 {
reg = <4>;
active-low;
label = "nb4-ser:white:adsl";
};
};
&uart0 {
status = "okay";
};
arch/mips/boot/dts/brcm/bcm96368mvwg.dts
View file @ 07b75260
......@@ -22,10 +22,10 @@ &uart0 {
};
/* FIXME: need to set up USB_CTRL registers first */
&ehci0 {
&ehci {
status = "disabled";
};
&ohci0 {
&ohci {
status = "disabled";
};
arch/mips/boot/dts/brcm/bcm97125cbmb.dts
View file @ 07b75260
......@@ -21,6 +21,30 @@ &uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&bsca {
status = "okay";
};
&bscb {
status = "okay";
};
&bscc {
status = "okay";
};
&bscd {
status = "okay";
};
/* FIXME: USB is wonky; disable it for now */
&ehci0 {
status = "disabled";
......
arch/mips/boot/dts/brcm/bcm97360svmb.dts
View file @ 07b75260
......@@ -56,3 +56,11 @@ &ehci0 {
&ohci0 {
status = "okay";
};
&sata {
status = "okay";
};
&sata_phy {
status = "okay";
};
arch/mips/boot/dts/brcm/bcm97420c.dts
View file @ 07b75260
......@@ -23,6 +23,34 @@ &uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&bsca {
status = "okay";
};
&bscb {
status = "okay";
};
&bscc {
status = "okay";
};
&bscd {
status = "okay";
};
&bsce {
status = "okay";
};
/* FIXME: MAC driver comes up but cannot attach to PHY */
&enet0 {
status = "disabled";
......
arch/mips/boot/dts/brcm/bcm97425svmb.dts
View file @ 07b75260
......@@ -23,6 +23,34 @@ &uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&bsca {
status = "okay";
};
&bscb {
status = "okay";
};
&bscc {
status = "okay";
};
&bscd {
status = "okay";
};
&bsce {
status = "okay";
};
&enet0 {
status = "okay";
};
......
arch/mips/boot/dts/brcm/bcm97435svmb.dts
View file @ 07b75260
......@@ -14,7 +14,7 @@ memory@0 {
};
chosen {
bootargs = "console=ttyS0,115200 maxcpus=1";
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
};
};
......@@ -23,6 +23,34 @@ &uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&bsca {
status = "okay";
};
&bscb {
status = "okay";
};
&bscc {
status = "okay";
};
&bscd {
status = "okay";
};
&bsce {
status = "okay";
};
&enet0 {
status = "okay";
};
......@@ -58,3 +86,11 @@ &ehci3 {
&ohci3 {
status = "okay";
};
&sata {
status = "okay";
};
&sata_phy {
status = "okay";
};
arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts 0 → 100644
View file @ 07b75260
/*
* Device tree source for D-Link DSR-1000N.
*
* Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "octeon_3xxx.dtsi"
/ {
model = "dlink,dsr-1000n";
soc@0 {
smi0: mdio@1180000001800 {
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c22";
};
};
pip: pip@11800a0000000 {
interface@0 {
ethernet@0 {
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@1 {
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@2 {
phy-handle = <&phy8>;
};
};
};
twsi0: i2c@1180000001000 {
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
uart0: serial@1180000000800 {
clock-frequency = <500000000>;
};
usbn: usbn@1180068000000 {
refclk-frequency = <12000000>;
refclk-type = "crystal";
};
};
leds {
compatible = "gpio-leds";
usb1 {
label = "usb1";
gpios = <&gpio 9 1>; /* Active low */
};
usb2 {
label = "usb2";
gpios = <&gpio 10 1>; /* Active low */
};
};
aliases {
pip = &pip;
};
};
arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts
View file @ 07b75260
/dts-v1/;
/*
* OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
*
......@@ -6,56 +5,12 @@
* use. Because of this, it contains a super-set of the available
* devices and properties.
*/
/ {
compatible = "cavium,octeon-3860";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&ciu>;
soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges; /* Direct mapping */
ciu: interrupt-controller@1070000000000 {
compatible = "cavium,octeon-3860-ciu";
interrupt-controller;
/* Interrupts are specified by two parts:
* 1) Controller register (0 or 1)
* 2) Bit within the register (0..63)
*/
#interrupt-cells = <2>;
reg = <0x10700 0x00000000 0x0 0x7000>;
};
gpio: gpio-controller@1070000000800 {
#gpio-cells = <2>;
compatible = "cavium,octeon-3860-gpio";
reg = <0x10700 0x00000800 0x0 0x100>;
gpio-controller;
/* Interrupts are specified by two parts:
* 1) GPIO pin number (0..15)
* 2) Triggering (1 - edge rising
* 2 - edge falling
* 4 - level active high
* 8 - level active low)
*/
interrupt-controller;
#interrupt-cells = <2>;
/* The GPIO pin connect to 16 consecutive CUI bits */
interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
<0 20>, <0 21>, <0 22>, <0 23>,
<0 24>, <0 25>, <0 26>, <0 27>,
<0 28>, <0 29>, <0 30>, <0 31>;
};
/include/ "octeon_3xxx.dtsi"
/ {
soc@0 {
smi0: mdio@1180000001800 {
compatible = "cavium,octeon-3860-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x11800 0x00001800 0x0 0x40>;
phy0: ethernet-phy@0 {
compatible = "marvell,88e1118";
marvell,reg-init =
......@@ -220,35 +175,16 @@ mix1: ethernet@1070000100800 {
};
pip: pip@11800a0000000 {
compatible = "cavium,octeon-3860-pip";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x11800 0xa0000000 0x0 0x2000>;
interface@0 {
compatible = "cavium,octeon-3860-pip-interface";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; /* interface */
ethernet@0 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x0>; /* Port */
local-mac-address = [ 00 00 00 00 00 00 ];
phy-handle = <&phy2>;
cavium,alt-phy-handle = <&phy100>;
};
ethernet@1 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x1>; /* Port */
local-mac-address = [ 00 00 00 00 00 00 ];
phy-handle = <&phy3>;
cavium,alt-phy-handle = <&phy101>;
};
ethernet@2 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x2>; /* Port */
local-mac-address = [ 00 00 00 00 00 00 ];
phy-handle = <&phy4>;
cavium,alt-phy-handle = <&phy102>;
};
......@@ -322,11 +258,6 @@ ethernet@f {
};
interface@1 {
compatible = "cavium,octeon-3860-pip-interface";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; /* interface */
ethernet@0 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x0>; /* Port */
......@@ -355,13 +286,6 @@ ethernet@3 {
};
twsi0: i2c@1180000001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cavium,octeon-3860-twsi";
reg = <0x11800 0x00001000 0x0 0x200>;
interrupts = <0 45>;
clock-frequency = <100000>;
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
......@@ -381,15 +305,6 @@ twsi1: i2c@1180000001200 {
clock-frequency = <100000>;
};
uart0: serial@1180000000800 {
compatible = "cavium,octeon-3860-uart","ns16550";
reg = <0x11800 0x00000800 0x0 0x400>;
clock-frequency = <0>;
current-speed = <115200>;
reg-shift = <3>;
interrupts = <0 34>;
};
uart1: serial@1180000000c00 {
compatible = "cavium,octeon-3860-uart","ns16550";
reg = <0x11800 0x00000c00 0x0 0x400>;
......@@ -409,98 +324,6 @@ uart2: serial@1180000000400 {
};
bootbus: bootbus@1180000000000 {
compatible = "cavium,octeon-3860-bootbus";
reg = <0x11800 0x00000000 0x0 0x200>;
/* The chip select number and offset */
#address-cells = <2>;
/* The size of the chip select region */
#size-cells = <1>;
ranges = <0 0 0x0 0x1f400000 0xc00000>,
<1 0 0x10000 0x30000000 0>,
<2 0 0x10000 0x40000000 0>,
<3 0 0x10000 0x50000000 0>,
<4 0 0x0 0x1d020000 0x10000>,
<5 0 0x0 0x1d040000 0x10000>,
<6 0 0x0 0x1d050000 0x10000>,
<7 0 0x10000 0x90000000 0>;
cavium,cs-config@0 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <0>;
cavium,t-adr = <20>;
cavium,t-ce = <60>;
cavium,t-oe = <60>;
cavium,t-we = <45>;
cavium,t-rd-hld = <35>;
cavium,t-wr-hld = <45>;
cavium,t-pause = <0>;
cavium,t-wait = <0>;
cavium,t-page = <35>;
cavium,t-rd-dly = <0>;
cavium,pages = <0>;
cavium,bus-width = <8>;
};
cavium,cs-config@4 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <4>;
cavium,t-adr = <320>;
cavium,t-ce = <320>;
cavium,t-oe = <320>;
cavium,t-we = <320>;
cavium,t-rd-hld = <320>;
cavium,t-wr-hld = <320>;
cavium,t-pause = <320>;
cavium,t-wait = <320>;
cavium,t-page = <320>;
cavium,t-rd-dly = <0>;
cavium,pages = <0>;
cavium,bus-width = <8>;
};
cavium,cs-config@5 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <5>;
cavium,t-adr = <5>;
cavium,t-ce = <300>;
cavium,t-oe = <125>;
cavium,t-we = <150>;
cavium,t-rd-hld = <100>;
cavium,t-wr-hld = <30>;
cavium,t-pause = <0>;
cavium,t-wait = <30>;
cavium,t-page = <320>;
cavium,t-rd-dly = <0>;
cavium,pages = <0>;
cavium,bus-width = <16>;
};
cavium,cs-config@6 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <6>;
cavium,t-adr = <5>;
cavium,t-ce = <300>;
cavium,t-oe = <270>;
cavium,t-we = <150>;
cavium,t-rd-hld = <100>;
cavium,t-wr-hld = <70>;
cavium,t-pause = <0>;
cavium,t-wait = <0>;
cavium,t-page = <320>;
cavium,t-rd-dly = <0>;
cavium,pages = <0>;
cavium,wait-mode;
cavium,bus-width = <16>;
};
flash0: nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
};
led0: led-display@4,0 {
compatible = "avago,hdsp-253x";
reg = <4 0x20 0x20>, <4 0 0x20>;
......@@ -515,17 +338,6 @@ cf0: compact-flash@5,0 {
};
};
dma0: dma-engine@1180000000100 {
compatible = "cavium,octeon-5750-bootbus-dma";
reg = <0x11800 0x00000100 0x0 0x8>;
interrupts = <0 63>;
};
dma1: dma-engine@1180000000108 {
compatible = "cavium,octeon-5750-bootbus-dma";
reg = <0x11800 0x00000108 0x0 0x8>;
interrupts = <0 63>;
};
uctl: uctl@118006f000000 {
compatible = "cavium,octeon-6335-uctl";
reg = <0x11800 0x6f000000 0x0 0x100>;
......@@ -552,21 +364,10 @@ ohci@16f0000000400 {
};
usbn: usbn@1180068000000 {
compatible = "cavium,octeon-5750-usbn";
reg = <0x11800 0x68000000 0x0 0x1000>;
ranges; /* Direct mapping */
#address-cells = <2>;
#size-cells = <2>;
/* 12MHz, 24MHz and 48MHz allowed */
refclk-frequency = <12000000>;
/* Either "crystal" or "external" */
refclk-type = "crystal";
usbc@16f0010000000 {
compatible = "cavium,octeon-5750-usbc";
reg = <0x16f00 0x10000000 0x0 0x80000>;
interrupts = <0 56>;
};
};
};
......
arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi 0 → 100644
View file @ 07b75260
/* OCTEON 3XXX DTS common parts. */
/dts-v1/;
/ {
compatible = "cavium,octeon-3860";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&ciu>;
soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges; /* Direct mapping */
ciu: interrupt-controller@1070000000000 {
compatible = "cavium,octeon-3860-ciu";
interrupt-controller;
/* Interrupts are specified by two parts:
* 1) Controller register (0 or 1)
* 2) Bit within the register (0..63)
*/
#interrupt-cells = <2>;
reg = <0x10700 0x00000000 0x0 0x7000>;
};
gpio: gpio-controller@1070000000800 {
#gpio-cells = <2>;
compatible = "cavium,octeon-3860-gpio";
reg = <0x10700 0x00000800 0x0 0x100>;
gpio-controller;
/* Interrupts are specified by two parts:
* 1) GPIO pin number (0..15)
* 2) Triggering (1 - edge rising
* 2 - edge falling
* 4 - level active high
* 8 - level active low)
*/
interrupt-controller;
#interrupt-cells = <2>;
/* The GPIO pin connect to 16 consecutive CUI bits */
interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
<0 20>, <0 21>, <0 22>, <0 23>,
<0 24>, <0 25>, <0 26>, <0 27>,
<0 28>, <0 29>, <0 30>, <0 31>;
};
smi0: mdio@1180000001800 {
compatible = "cavium,octeon-3860-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x11800 0x00001800 0x0 0x40>;
};
pip: pip@11800a0000000 {
compatible = "cavium,octeon-3860-pip";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x11800 0xa0000000 0x0 0x2000>;
interface@0 {
compatible = "cavium,octeon-3860-pip-interface";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; /* interface */
ethernet@0 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x0>; /* Port */
local-mac-address = [ 00 00 00 00 00 00 ];
};
ethernet@1 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x1>; /* Port */
local-mac-address = [ 00 00 00 00 00 00 ];
};
ethernet@2 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x2>; /* Port */
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
interface@1 {
compatible = "cavium,octeon-3860-pip-interface";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; /* interface */
};
};
twsi0: i2c@1180000001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cavium,octeon-3860-twsi";
reg = <0x11800 0x00001000 0x0 0x200>;
interrupts = <0 45>;
clock-frequency = <100000>;
};
uart0: serial@1180000000800 {
compatible = "cavium,octeon-3860-uart","ns16550";
reg = <0x11800 0x00000800 0x0 0x400>;
clock-frequency = <0>;
current-speed = <115200>;
reg-shift = <3>;
interrupts = <0 34>;
};
bootbus: bootbus@1180000000000 {
compatible = "cavium,octeon-3860-bootbus";
reg = <0x11800 0x00000000 0x0 0x200>;
/* The chip select number and offset */
#address-cells = <2>;
/* The size of the chip select region */
#size-cells = <1>;
ranges = <0 0 0x0 0x1f400000 0xc00000>,
<1 0 0x10000 0x30000000 0>,
<2 0 0x10000 0x40000000 0>,
<3 0 0x10000 0x50000000 0>,
<4 0 0x0 0x1d020000 0x10000>,
<5 0 0x0 0x1d040000 0x10000>,
<6 0 0x0 0x1d050000 0x10000>,
<7 0 0x10000 0x90000000 0>;
cavium,cs-config@0 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <0>;
cavium,t-adr = <20>;
cavium,t-ce = <60>;
cavium,t-oe = <60>;
cavium,t-we = <45>;
cavium,t-rd-hld = <35>;
cavium,t-wr-hld = <45>;
cavium,t-pause = <0>;
cavium,t-wait = <0>;
cavium,t-page = <35>;
cavium,t-rd-dly = <0>;
cavium,pages = <0>;
cavium,bus-width = <8>;
};
cavium,cs-config@4 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <4>;
cavium,t-adr = <320>;
cavium,t-ce = <320>;
cavium,t-oe = <320>;
cavium,t-we = <320>;
cavium,t-rd-hld = <320>;
cavium,t-wr-hld = <320>;
cavium,t-pause = <320>;
cavium,t-wait = <320>;
cavium,t-page = <320>;
cavium,t-rd-dly = <0>;
cavium,pages = <0>;
cavium,bus-width = <8>;
};
cavium,cs-config@5 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <5>;
cavium,t-adr = <5>;
cavium,t-ce = <300>;
cavium,t-oe = <125>;
cavium,t-we = <150>;
cavium,t-rd-hld = <100>;
cavium,t-wr-hld = <30>;
cavium,t-pause = <0>;
cavium,t-wait = <30>;
cavium,t-page = <320>;
cavium,t-rd-dly = <0>;
cavium,pages = <0>;
cavium,bus-width = <16>;
};
cavium,cs-config@6 {
compatible = "cavium,octeon-3860-bootbus-config";
cavium,cs-index = <6>;
cavium,t-adr = <5>;
cavium,t-ce = <300>;
cavium,t-oe = <270>;
cavium,t-we = <150>;
cavium,t-rd-hld = <100>;
cavium,t-wr-hld = <70>;
cavium,t-pause = <0>;
cavium,t-wait = <0>;
cavium,t-page = <320>;
cavium,t-rd-dly = <0>;
cavium,pages = <0>;
cavium,wait-mode;
cavium,bus-width = <16>;
};
flash0: nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
dma0: dma-engine@1180000000100 {
compatible = "cavium,octeon-5750-bootbus-dma";
reg = <0x11800 0x00000100 0x0 0x8>;
interrupts = <0 63>;
};
dma1: dma-engine@1180000000108 {
compatible = "cavium,octeon-5750-bootbus-dma";
reg = <0x11800 0x00000108 0x0 0x8>;
interrupts = <0 63>;
};
usbn: usbn@1180068000000 {
compatible = "cavium,octeon-5750-usbn";
reg = <0x11800 0x68000000 0x0 0x1000>;
ranges; /* Direct mapping */
#address-cells = <2>;
#size-cells = <2>;
usbc@16f0010000000 {
compatible = "cavium,octeon-5750-usbc";
reg = <0x16f00 0x10000000 0x0 0x80000>;
interrupts = <0 56>;
};
};
};
};
arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts 0 → 100644
View file @ 07b75260
/*
* Device tree source for EdgeRouter Lite.
*
* Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "octeon_3xxx.dtsi"
/ {
model = "ubnt,e100";
soc@0 {
smi0: mdio@1180000001800 {
phy5: ethernet-phy@5 {
reg = <5>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy6: ethernet-phy@6 {
reg = <6>;
compatible = "ethernet-phy-ieee802.3-c22";
};
phy7: ethernet-phy@7 {
reg = <7>;
compatible = "ethernet-phy-ieee802.3-c22";
};
};
pip: pip@11800a0000000 {
interface@0 {
ethernet@0 {
phy-handle = <&phy7>;
};
ethernet@1 {
phy-handle = <&phy6>;
};
ethernet@2 {
phy-handle = <&phy5>;
};
};
};
uart0: serial@1180000000800 {
clock-frequency = <500000000>;
};
usbn: usbn@1180068000000 {
refclk-frequency = <12000000>;
refclk-type = "crystal";
};
};
aliases {
pip = &pip;
};
};
arch/mips/boot/dts/ingenic/jz4740.dtsi
View file @ 07b75260
......@@ -65,4 +65,18 @@ uart1: serial@10031000 {
clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
clock-names = "baud", "module";
};
uhc: uhc@13030000 {
compatible = "ingenic,jz4740-ohci", "generic-ohci";
reg = <0x13030000 0x1000>;
clocks = <&cgu JZ4740_CLK_UHC>;
assigned-clocks = <&cgu JZ4740_CLK_UHC>;
assigned-clock-rates = <48000000>;
interrupt-parent = <&intc>;
interrupts = <3>;
status = "disabled";
};
};
arch/mips/boot/dts/lantiq/easy50712.dts
View file @ 07b75260
......@@ -52,7 +52,7 @@ partition@400000 {
};
gpio: pinmux@E100B10 {
compatible = "lantiq,pinctrl-xway";
compatible = "lantiq,danube-pinctrl";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......
arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi deleted 100644 → 0
View file @ 0efacbba
/*
* Device Tree Source for PIC32MZDA clock data
*
* Purna Chandra Mandal <purna.mandal@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*
* Licensed under GPLv2 or later.
*/
/* all fixed rate clocks */
/ {
POSC:posc_clk { /* On-chip primary oscillator */
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
FRC:frc_clk { /* internal FRC oscillator */
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <8000000>;
};
BFRC:bfrc_clk { /* internal backup FRC oscillator */
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <8000000>;
};
LPRC:lprc_clk { /* internal low-power FRC oscillator */
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
/* UPLL provides clock to USBCORE */
UPLL:usb_phy_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "usbphy_clk";
};
TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <4000000>;
status = "disabled";
};
/* external clock input on REFCLKIx pin */
REFIx:refix_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
status = "disabled";
};
/* PIC32 specific clks */
pic32_clktree {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1f801200 0x200>;
compatible = "microchip,pic32mzda-clk";
ranges = <0 0x1f801200 0x200>;
/* secondary oscillator; external input on SOSCI pin */
SOSC:sosc_clk@0 {
#clock-cells = <0>;
compatible = "microchip,pic32mzda-sosc";
clock-frequency = <32768>;
reg = <0x000 0x10>, /* enable reg */
<0x1d0 0x10>; /* status reg */
microchip,bit-mask = <0x02>; /* enable mask */
microchip,status-bit-mask = <0x10>; /* status-mask*/
};
FRCDIV:frcdiv_clk {
#clock-cells = <0>;
compatible = "microchip,pic32mzda-frcdivclk";
clocks = <&FRC>;
clock-output-names = "frcdiv_clk";
};
/* System PLL clock */
SYSPLL:spll_clk@020 {
#clock-cells = <0>;
compatible = "microchip,pic32mzda-syspll";
reg = <0x020 0x10>, /* SPLL register */
<0x1d0 0x10>; /* CLKSTAT register */
clocks = <&POSC>, <&FRC>;
clock-output-names = "sys_pll";
microchip,status-bit-mask = <0x80>; /* SPLLRDY */
};
/* system clock; mux with postdiv & slew */
SYSCLK:sys_clk@1c0 {
#clock-cells = <0>;
compatible = "microchip,pic32mzda-sysclk-v2";
reg = <0x1c0 0x04>; /* SLEWCON */
clocks = <&FRCDIV>, <&SYSPLL>, <&POSC>, <&SOSC>,
<&LPRC>, <&FRCDIV>;
microchip,clock-indices = <0>, <1>, <2>, <4>,
<5>, <7>;
clock-output-names = "sys_clk";
};
/* Peripheral bus1 clock */
PBCLK1:pb1_clk@140 {
reg = <0x140 0x10>;
#clock-cells = <0>;
compatible = "microchip,pic32mzda-pbclk";
clocks = <&SYSCLK>;
clock-output-names = "pb1_clk";
/* used by system modules, not gateable */
microchip,ignore-unused;
};
/* Peripheral bus2 clock */
PBCLK2:pb2_clk@150 {
reg = <0x150 0x10>;
#clock-cells = <0>;
compatible = "microchip,pic32mzda-pbclk";
clocks = <&SYSCLK>;
clock-output-names = "pb2_clk";
/* avoid gating even if unused */
microchip,ignore-unused;
};
/* Peripheral bus3 clock */
PBCLK3:pb3_clk@160 {
reg = <0x160 0x10>;
#clock-cells = <0>;
compatible = "microchip,pic32mzda-pbclk";
clocks = <&SYSCLK>;
clock-output-names = "pb3_clk";
};
/* Peripheral bus4 clock(I/O ports, GPIO) */
PBCLK4:pb4_clk@170 {
reg = <0x170 0x10>;
#clock-cells = <0>;
compatible = "microchip,pic32mzda-pbclk";
clocks = <&SYSCLK>;
clock-output-names = "pb4_clk";
};
/* Peripheral bus clock */
PBCLK5:pb5_clk@180 {
reg = <0x180 0x10>;
#clock-cells = <0>;
compatible = "microchip,pic32mzda-pbclk";
clocks = <&SYSCLK>;
clock-output-names = "pb5_clk";
};
/* Peripheral Bus6 clock; */
PBCLK6:pb6_clk@190 {
reg = <0x190 0x10>;
compatible = "microchip,pic32mzda-pbclk";
clocks = <&SYSCLK>;
#clock-cells = <0>;
};
/* Peripheral bus7 clock */
PBCLK7:pb7_clk@1a0 {
reg = <0x1a0 0x10>;
#clock-cells = <0>;
compatible = "microchip,pic32mzda-pbclk";
/* CPU is driven by this clock; so named */
clock-output-names = "cpu_clk";
clocks = <&SYSCLK>;
};
/* Reference Oscillator clock for SPI/I2S */
REFCLKO1:refo1_clk@80 {
reg = <0x080 0x20>;
#clock-cells = <0>;
compatible = "microchip,pic32mzda-refoclk";
clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
<&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
<5>, <7>, <8>, <9>;
clock-output-names = "refo1_clk";
};
/* Reference Oscillator clock for SQI */
REFCLKO2:refo2_clk@a0 {
reg = <0x0a0 0x20>;
#clock-cells = <0>;
compatible = "microchip,pic32mzda-refoclk";
clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
<&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
<5>, <7>, <8>, <9>;
clock-output-names = "refo2_clk";
};
/* Reference Oscillator clock, ADC */
REFCLKO3:refo3_clk@c0 {
reg = <0x0c0 0x20>;
compatible = "microchip,pic32mzda-refoclk";
clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
<&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
<5>, <7>, <8>, <9>;
#clock-cells = <0>;
clock-output-names = "refo3_clk";
};
/* Reference Oscillator clock */
REFCLKO4:refo4_clk@e0 {
reg = <0x0e0 0x20>;
compatible = "microchip,pic32mzda-refoclk";
clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
<&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
<5>, <7>, <8>, <9>;
#clock-cells = <0>;
clock-output-names = "refo4_clk";
};
/* Reference Oscillator clock, LCD */
REFCLKO5:refo5_clk@100 {
reg = <0x100 0x20>;
compatible = "microchip,pic32mzda-refoclk";
clocks = <&SYSCLK>,<&PBCLK1>,<&POSC>,<&FRC>,<&LPRC>,
<&SOSC>,<&SYSPLL>,<&REFIx>,<&BFRC>;
microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
<5>, <7>, <8>, <9>;
#clock-cells = <0>;
clock-output-names = "refo5_clk";
};
};
};
arch/mips/boot/dts/pic32/pic32mzda.dtsi
View file @ 07b75260
......@@ -6,11 +6,9 @@
* published by the Free Software Foundation.
*
*/
#include <dt-bindings/clock/microchip,pic32-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "pic32mzda-clk.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
......@@ -50,6 +48,29 @@ soc {
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
};
/* external clock input on TxCLKI pin */
txcki: txcki_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <4000000>;
status = "disabled";
};
/* external input on REFCLKIx pin */
refix: refix_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
status = "disabled";
};
rootclk: clock-controller@1f801200 {
compatible = "microchip,pic32mzda-clk";
reg = <0x1f801200 0x200>;
#clock-cells = <1>;
microchip,pic32mzda-sosc;
};
evic: interrupt-controller@1f810000 {
compatible = "microchip,pic32mzda-evic";
interrupt-controller;
......@@ -63,7 +84,7 @@ pic32_pinctrl: pinctrl@1f801400{
#size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>;
clocks = <&PBCLK1>;
clocks = <&rootclk PB1CLK>;
};
/* PORTA */
......@@ -75,7 +96,7 @@ gpio0: gpio0@1f860000 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <0>;
gpio-ranges = <&pic32_pinctrl 0 0 16>;
};
......@@ -89,7 +110,7 @@ gpio1: gpio1@1f860100 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <1>;
gpio-ranges = <&pic32_pinctrl 0 16 16>;
};
......@@ -103,7 +124,7 @@ gpio2: gpio2@1f860200 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <2>;
gpio-ranges = <&pic32_pinctrl 0 32 16>;
};
......@@ -117,7 +138,7 @@ gpio3: gpio3@1f860300 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <3>;
gpio-ranges = <&pic32_pinctrl 0 48 16>;
};
......@@ -131,7 +152,7 @@ gpio4: gpio4@1f860400 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <4>;
gpio-ranges = <&pic32_pinctrl 0 64 16>;
};
......@@ -145,7 +166,7 @@ gpio5: gpio5@1f860500 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <5>;
gpio-ranges = <&pic32_pinctrl 0 80 16>;
};
......@@ -159,7 +180,7 @@ gpio6: gpio6@1f860600 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <6>;
gpio-ranges = <&pic32_pinctrl 0 96 16>;
};
......@@ -173,7 +194,7 @@ gpio7: gpio7@1f860700 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <7>;
gpio-ranges = <&pic32_pinctrl 0 112 16>;
};
......@@ -189,7 +210,7 @@ gpio8: gpio8@1f860800 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <8>;
gpio-ranges = <&pic32_pinctrl 0 128 16>;
};
......@@ -203,7 +224,7 @@ gpio9: gpio9@1f860900 {
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
clocks = <&rootclk PB4CLK>;
microchip,gpio-bank = <9>;
gpio-ranges = <&pic32_pinctrl 0 144 16>;
};
......@@ -212,7 +233,7 @@ sdhci: sdhci@1f8ec000 {
compatible = "microchip,pic32mzda-sdhci";
reg = <0x1f8ec000 0x100>;
interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&REFCLKO4>, <&PBCLK5>;
clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
clock-names = "base_clk", "sys_clk";
bus-width = <4>;
cap-sd-highspeed;
......@@ -225,7 +246,7 @@ uart1: serial@1f822000 {
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
<113 IRQ_TYPE_LEVEL_HIGH>,
<114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>;
clocks = <&rootclk PB2CLK>;
status = "disabled";
};
......@@ -235,7 +256,7 @@ uart2: serial@1f822200 {
interrupts = <145 IRQ_TYPE_LEVEL_HIGH>,
<146 IRQ_TYPE_LEVEL_HIGH>,
<147 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>;
clocks = <&rootclk PB2CLK>;
status = "disabled";
};
......@@ -245,7 +266,7 @@ uart3: serial@1f822400 {
interrupts = <157 IRQ_TYPE_LEVEL_HIGH>,
<158 IRQ_TYPE_LEVEL_HIGH>,
<159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>;
clocks = <&rootclk PB2CLK>;
status = "disabled";
};
......@@ -255,7 +276,7 @@ uart4: serial@1f822600 {
interrupts = <170 IRQ_TYPE_LEVEL_HIGH>,
<171 IRQ_TYPE_LEVEL_HIGH>,
<172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>;
clocks = <&rootclk PB2CLK>;
status = "disabled";
};
......@@ -265,7 +286,7 @@ uart5: serial@1f822800 {
interrupts = <179 IRQ_TYPE_LEVEL_HIGH>,
<180 IRQ_TYPE_LEVEL_HIGH>,
<181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>;
clocks = <&rootclk PB2CLK>;
status = "disabled";
};
......@@ -275,7 +296,7 @@ uart6: serial@1f822A00 {
interrupts = <188 IRQ_TYPE_LEVEL_HIGH>,
<189 IRQ_TYPE_LEVEL_HIGH>,
<190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&PBCLK2>;
clocks = <&rootclk PB2CLK>;
status = "disabled";
};
};
arch/mips/boot/dts/pic32/pic32mzda_sk.dts
View file @ 07b75260
......@@ -95,8 +95,9 @@ &sdhci {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhc1>;
status = "okay";
assigned-clocks = <&REFCLKO2>,<&REFCLKO4>,<&REFCLKO5>;
assigned-clock-rates = <50000000>,<25000000>,<40000000>;
assigned-clocks = <&rootclk REF2CLK>, <&rootclk REF4CLK>,
<&rootclk REF5CLK>;
assigned-clock-rates = <50000000>, <25000000>, <40000000>;
};
&pic32_pinctrl {
......
arch/mips/boot/dts/qca/Makefile
View file @ 07b75260
# All DTBs
dtb-$(CONFIG_ATH79) += ar9132_tl_wr1043nd_v1.dtb
# Select a DTB to build in the kernel
obj-$(CONFIG_DTB_TL_WR1043ND_V1) += ar9132_tl_wr1043nd_v1.dtb.o
dtb-$(CONFIG_ATH79) += ar9331_dpt_module.dtb
dtb-$(CONFIG_ATH79) += ar9331_dragino_ms14.dtb
dtb-$(CONFIG_ATH79) += ar9331_omega.dtb
dtb-$(CONFIG_ATH79) += ar9331_tl_mr3020.dtb
# Force kbuild to make empty built-in.o if necessary
obj- += dummy.o
......
arch/mips/boot/dts/qca/ar9132.dtsi
View file @ 07b75260
#include <dt-bindings/clock/ath79-clk.h>
/ {
compatible = "qca,ar9132";
......@@ -11,6 +13,7 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "mips,mips24Kc";
clocks = <&pll ATH79_CLK_CPU>;
reg = <0>;
};
};
......@@ -52,12 +55,12 @@ ddr_ctrl: memory-controller@18000000 {
#qca,ddr-wb-channel-cells = <1>;
};
uart@18020000 {
uart: uart@18020000 {
compatible = "ns8250";
reg = <0x18020000 0x20>;
interrupts = <3>;
clocks = <&pll 2>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "uart";
reg-io-width = <4>;
......@@ -94,13 +97,13 @@ pll: pll-controller@18050000 {
clock-output-names = "cpu", "ddr", "ahb";
};
wdt@18060008 {
wdt: wdt@18060008 {
compatible = "qca,ar7130-wdt";
reg = <0x18060008 0x8>;
interrupts = <4>;
clocks = <&pll 2>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "wdt";
};
......@@ -125,7 +128,7 @@ rst: reset-controller@1806001c {
};
};
usb@1b000100 {
usb: usb@1b000100 {
compatible = "qca,ar7100-ehci", "generic-ehci";
reg = <0x1b000100 0x100>;
......@@ -140,11 +143,11 @@ usb@1b000100 {
status = "disabled";
};
spi@1f000000 {
spi: spi@1f000000 {
compatible = "qca,ar9132-spi", "qca,ar7100-spi";
reg = <0x1f000000 0x10>;
clocks = <&pll 2>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "ahb";
status = "disabled";
......
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
View file @ 07b75260
......@@ -9,10 +9,6 @@ / {
compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132";
model = "TP-Link TL-WR1043ND Version 1";
alias {
serial0 = "/ahb/apb/uart@18020000";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x2000000>;
......@@ -24,55 +20,6 @@ extosc: ref {
clock-frequency = <40000000>;
};
ahb {
apb {
uart@18020000 {
status = "okay";
};
pll-controller@18050000 {
clocks = <&extosc>;
};
};
usb@1b000100 {
status = "okay";
};
spi@1f000000 {
status = "okay";
num-cs = <1>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25sl064a";
reg = <0>;
spi-max-frequency = <25000000>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x020000>;
};
partition@1 {
label = "firmware";
reg = <0x020000 0x7D0000>;
};
partition@2 {
label = "art";
reg = <0x7F0000 0x010000>;
read-only;
};
};
};
};
usb-phy {
status = "okay";
};
gpio-keys {
compatible = "gpio-keys-polled";
#address-cells = <1>;
......@@ -118,3 +65,48 @@ led@3 {
};
};
};
&uart {
status = "okay";
};
&pll {
clocks = <&extosc>;
};
&usb {
status = "okay";
};
&usb_phy {
status = "okay";
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25sl064a";
reg = <0>;
spi-max-frequency = <25000000>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x020000>;
};
partition@1 {
label = "firmware";
reg = <0x020000 0x7D0000>;
};
partition@2 {
label = "art";
reg = <0x7F0000 0x010000>;
read-only;
};
};
};
arch/mips/boot/dts/qca/ar9331.dtsi 0 → 100644
View file @ 07b75260
#include <dt-bindings/clock/ath79-clk.h>
/ {
compatible = "qca,ar9331";
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips24Kc";
clocks = <&pll ATH79_CLK_CPU>;
reg = <0>;
};
};
cpuintc: interrupt-controller {
compatible = "qca,ar7100-cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
qca,ddr-wb-channel-interrupts = <2>, <3>;
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
};
ref: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
};
ahb {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&cpuintc>;
apb {
compatible = "simple-bus";
ranges;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&miscintc>;
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar7240-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};
uart: uart@18020000 {
compatible = "qca,ar9330-uart";
reg = <0x18020000 0x14>;
interrupts = <3>;
clocks = <&ref>;
clock-names = "uart";
status = "disabled";
};
gpio: gpio@18040000 {
compatible = "qca,ar7100-gpio";
reg = <0x18040000 0x34>;
interrupts = <2>;
ngpios = <30>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
pll: pll-controller@18050000 {
compatible = "qca,ar9330-pll";
reg = <0x18050000 0x100>;
clocks = <&ref>;
clock-names = "ref";
#clock-cells = <1>;
};
miscintc: interrupt-controller@18060010 {
compatible = "qca,ar7240-misc-intc";
reg = <0x18060010 0x4>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <1>;
};
rst: reset-controller@1806001c {
compatible = "qca,ar7100-reset";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
};
};
usb: usb@1b000100 {
compatible = "chipidea,usb2";
reg = <0x1b000000 0x200>;
interrupts = <3>;
resets = <&rst 5>;
phy-names = "usb-phy";
phys = <&usb_phy>;
status = "disabled";
};
spi: spi@1f000000 {
compatible = "qca,ar7100-spi";
reg = <0x1f000000 0x10>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "ahb";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
usb_phy: usb-phy {
compatible = "qca,ar7100-usb-phy";
reset-names = "usb-phy", "usb-suspend-override";
resets = <&rst 4>, <&rst 3>;
#phy-cells = <0>;
status = "disabled";
};
};
arch/mips/boot/dts/qca/ar9331_dpt_module.dts 0 → 100644
View file @ 07b75260
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ar9331.dtsi"
/ {
model = "DPTechnics DPT-Module";
compatible = "dptechnics,dpt-module";
aliases {
serial0 = &uart;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x4000000>;
};
leds {
compatible = "gpio-leds";
system {
label = "dpt-module:green:system";
gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
};
};
&ref {
clock-frequency = <25000000>;
};
&uart {
status = "okay";
};
&gpio {
status = "okay";
};
&usb {
dr_mode = "host";
status = "okay";
};
&usb_phy {
status = "okay";
};
&spi {
num-chipselects = <1>;
status = "okay";
/* Winbond 25Q128FVSG SPI flash */
spiflash: w25q128@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q128", "jedec,spi-nor";
spi-max-frequency = <104000000>;
reg = <0>;
};
};
arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts 0 → 100644
View file @ 07b75260
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ar9331.dtsi"
/ {
model = "Dragino MS14 (Dragino 2)";
compatible = "dragino,ms14";
aliases {
serial0 = &uart;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x4000000>;
};
leds {
compatible = "gpio-leds";
wlan {
label = "dragino2:red:wlan";
gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
lan {
label = "dragino2:red:lan";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wan {
label = "dragino2:red:wan";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
default-state = "off";
};
system {
label = "dragino2:red:system";
gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "jumpstart";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
button@1 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
};
};
};
&ref {
clock-frequency = <25000000>;
};
&uart {
status = "okay";
};
&gpio {
status = "okay";
};
&usb {
dr_mode = "host";
status = "okay";
};
&usb_phy {
status = "okay";
};
&spi {
num-chipselects = <1>;
status = "okay";
/* Winbond 25Q128BVFG SPI flash */
spiflash: w25q128@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q128", "jedec,spi-nor";
spi-max-frequency = <104000000>;
reg = <0>;
};
};
arch/mips/boot/dts/qca/ar9331_omega.dts 0 → 100644
View file @ 07b75260
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ar9331.dtsi"
/ {
model = "Onion Omega";
compatible = "onion,omega";
aliases {
serial0 = &uart;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x4000000>;
};
leds {
compatible = "gpio-leds";
system {
label = "onion:amber:system";
gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
};
};
};
&ref {
clock-frequency = <25000000>;
};
&uart {
status = "okay";
};
&gpio {
status = "okay";
};
&usb {
dr_mode = "host";
status = "okay";
};
&usb_phy {
status = "okay";
};
&spi {
num-chipselects = <1>;
status = "okay";
/* Winbond 25Q128FVSG SPI flash */
spiflash: w25q128@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "winbond,w25q128", "jedec,spi-nor";
spi-max-frequency = <104000000>;
reg = <0>;
};
};
arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts 0 → 100644
View file @ 07b75260
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ar9331.dtsi"
/ {
model = "TP-Link TL-MR3020";
compatible = "tplink,tl-mr3020";
aliases {
serial0 = &uart;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x2000000>;
};
leds {
compatible = "gpio-leds";
wlan {
label = "tp-link:green:wlan";
gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
lan {
label = "tp-link:green:lan";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wps {
label = "tp-link:green:wps";
gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3g {
label = "tp-link:green:3g";
gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <100>;
button@0 {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
};
button@1 {
label = "sw1";
linux,code = <BTN_0>;
gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
};
button@2 {
label = "sw2";
linux,code = <BTN_1>;
gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
};
};
reg_usb_vbus: reg_usb_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&ref {
clock-frequency = <25000000>;
};
&uart {
status = "okay";
};
&gpio {
status = "okay";
};
&usb {
dr_mode = "host";
vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&spi {
num-chipselects = <1>;
status = "okay";
/* Spansion S25FL032PIF SPI flash */
spiflash: s25sl032p@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25sl032p", "jedec,spi-nor";
spi-max-frequency = <104000000>;
reg = <0>;
};
};
arch/mips/boot/tools/Makefile 0 → 100644
View file @ 07b75260
hostprogs-y += relocs
relocs-objs += relocs_32.o
relocs-objs += relocs_64.o
relocs-objs += relocs_main.o
PHONY += relocs
relocs: $(obj)/relocs
@:
arch/mips/boot/tools/relocs.c 0 → 100644
View file @ 07b75260
This diff is collapsed.
arch/mips/boot/tools/relocs.h 0 → 100644
View file @ 07b75260
#ifndef RELOCS_H
#define RELOCS_H
#include <stdio.h>
#include <stdarg.h>
#include <stdlib.h>
#include <stdint.h>
#include <inttypes.h>
#include <string.h>
#include <errno.h>
#include <unistd.h>
#include <elf.h>
#include <byteswap.h>
#define USE_BSD
#include <endian.h>
#include <regex.h>
void die(char *fmt, ...);
/*
* Introduced for MIPSr6
*/
#ifndef R_MIPS_PC21_S2
#define R_MIPS_PC21_S2 60
#endif
#ifndef R_MIPS_PC26_S2
#define R_MIPS_PC26_S2 61
#endif
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
enum symtype {
S_ABS,
S_REL,
S_SEG,
S_LIN,
S_NSYMTYPES
};
void process_32(FILE *fp, int as_text, int as_bin,
int show_reloc_info, int keep_relocs);
void process_64(FILE *fp, int as_text, int as_bin,
int show_reloc_info, int keep_relocs);
#endif /* RELOCS_H */
arch/mips/boot/tools/relocs_32.c 0 → 100644
View file @ 07b75260
#include "relocs.h"
#define ELF_BITS 32
#define ELF_MACHINE EM_MIPS
#define ELF_MACHINE_NAME "MIPS"
#define SHT_REL_TYPE SHT_REL
#define Elf_Rel ElfW(Rel)
#define ELF_CLASS ELFCLASS32
#define ELF_R_SYM(val) ELF32_R_SYM(val)
#define ELF_R_TYPE(val) ELF32_R_TYPE(val)
#define ELF_ST_TYPE(o) ELF32_ST_TYPE(o)
#define ELF_ST_BIND(o) ELF32_ST_BIND(o)
#define ELF_ST_VISIBILITY(o) ELF32_ST_VISIBILITY(o)
#include "relocs.c"
arch/mips/boot/tools/relocs_64.c 0 → 100644
View file @ 07b75260
#include "relocs.h"
#define ELF_BITS 64
#define ELF_MACHINE EM_MIPS
#define ELF_MACHINE_NAME "MIPS64"
#define SHT_REL_TYPE SHT_RELA
#define Elf_Rel Elf64_Rela
typedef uint8_t Elf64_Byte;
typedef struct {
Elf64_Word r_sym; /* Symbol index. */
Elf64_Byte r_ssym; /* Special symbol. */
Elf64_Byte r_type3; /* Third relocation. */
Elf64_Byte r_type2; /* Second relocation. */
Elf64_Byte r_type; /* First relocation. */
} Elf64_Mips_Rela;
#define ELF_CLASS ELFCLASS64
#define ELF_R_SYM(val) (((Elf64_Mips_Rela *)(&val))->r_sym)
#define ELF_R_TYPE(val) (((Elf64_Mips_Rela *)(&val))->r_type)
#define ELF_ST_TYPE(o) ELF64_ST_TYPE(o)
#define ELF_ST_BIND(o) ELF64_ST_BIND(o)
#define ELF_ST_VISIBILITY(o) ELF64_ST_VISIBILITY(o)
#include "relocs.c"
arch/mips/boot/tools/relocs_main.c 0 → 100644
View file @ 07b75260
#include <stdio.h>
#include <stdint.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <endian.h>
#include <elf.h>
#include "relocs.h"
void die(char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
vfprintf(stderr, fmt, ap);
va_end(ap);
exit(1);
}
static void usage(void)
{
die("relocs [--reloc-info|--text|--bin|--keep] vmlinux\n");
}
int main(int argc, char **argv)
{
int show_reloc_info, as_text, as_bin, keep_relocs;
const char *fname;
FILE *fp;
int i;
unsigned char e_ident[EI_NIDENT];
show_reloc_info = 0;
as_text = 0;
as_bin = 0;
keep_relocs = 0;
fname = NULL;
for (i = 1; i < argc; i++) {
char *arg = argv[i];
if (*arg == '-') {
if (strcmp(arg, "--reloc-info") == 0) {
show_reloc_info = 1;
continue;
}
if (strcmp(arg, "--text") == 0) {
as_text = 1;
continue;
}
if (strcmp(arg, "--bin") == 0) {
as_bin = 1;
continue;
}
if (strcmp(arg, "--keep") == 0) {
keep_relocs = 1;
continue;
}
} else if (!fname) {
fname = arg;
continue;
}
usage();
}
if (!fname)
usage();
fp = fopen(fname, "r+");
if (!fp)
die("Cannot open %s: %s\n", fname, strerror(errno));
if (fread(&e_ident, 1, EI_NIDENT, fp) != EI_NIDENT)
die("Cannot read %s: %s", fname, strerror(errno));
rewind(fp);
if (e_ident[EI_CLASS] == ELFCLASS64)
process_64(fp, as_text, as_bin, show_reloc_info, keep_relocs);
else
process_32(fp, as_text, as_bin, show_reloc_info, keep_relocs);
fclose(fp);
return 0;
}
arch/mips/cavium-octeon/csrc-octeon.c
View file @ 07b75260
......@@ -19,6 +19,7 @@
#include <asm/octeon/cvmx-ipd-defs.h>
#include <asm/octeon/cvmx-mio-defs.h>
#include <asm/octeon/cvmx-rst-defs.h>
#include <asm/octeon/cvmx-fpa-defs.h>
static u64 f;
static u64 rdiv;
......@@ -65,9 +66,13 @@ void __init octeon_setup_delays(void)
*/
void octeon_init_cvmcount(void)
{
u64 clk_reg;
unsigned long flags;
unsigned loops = 2;
clk_reg = octeon_has_feature(OCTEON_FEATURE_FPA3) ?
CVMX_FPA_CLK_COUNT : CVMX_IPD_CLK_COUNT;
/* Clobber loops so GCC will not unroll the following while loop. */
asm("" : "+r" (loops));
......@@ -77,18 +82,18 @@ void octeon_init_cvmcount(void)
* which should give more deterministic timing.
*/
while (loops--) {
u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
u64 clk_count = cvmx_read_csr(clk_reg);
if (rdiv != 0) {
ipd_clk_count *= rdiv;
clk_count *= rdiv;
if (f != 0) {
asm("dmultu\t%[cnt],%[f]\n\t"
"mfhi\t%[cnt]"
: [cnt] "+r" (ipd_clk_count)
: [cnt] "+r" (clk_count)
: [f] "r" (f)
: "hi", "lo");
}
}
write_c0_cvmcount(ipd_clk_count);
write_c0_cvmcount(clk_count);
}
local_irq_restore(flags);
}
......
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fs/proc/vmcore.c
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include/asm-generic/seccomp.h
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include/asm-generic/siginfo.h
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include/linux/crash_dump.h
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include/linux/irqchip/mips-gic.h
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scripts/ld-version.sh
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