Skip to content

L
linux
Commit 0818c527 authored by Rajeshwari Shinde's avatar Rajeshwari Shinde Committed by Kukjin Kim
Browse files
Options

ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names 

Add support for lookup of sdhci-s3c controller clocks using generic
names for S5P64X0 SoCs.
Signed-off-by: default avatarRajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent ebc433c2
Hide whitespace changes
Inline Side-by-side
Showing with 84 additions and 60 deletions
arch/arm/mach-s5p64x0/clock-s5p6440.c
View file @ 0818c527
...@@ -378,36 +378,6 @@ static struct clksrc_sources clkset_audio = { ...@@ -378,36 +378,6 @@ static struct clksrc_sources clkset_audio = {
static struct clksrc_clk clksrcs[] = { static struct clksrc_clk clksrcs[] = {
{ {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk = { .clk = {
.name = "sclk_post", .name = "sclk_post",
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
...@@ -446,6 +416,42 @@ static struct clksrc_clk clksrcs[] = { ...@@ -446,6 +416,42 @@ static struct clksrc_clk clksrcs[] = {
}, },
}; };
static struct clksrc_clk clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
};
static struct clksrc_clk clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
};
static struct clksrc_clk clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_sclk_uclk = { static struct clksrc_clk clk_sclk_uclk = {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
...@@ -503,6 +509,9 @@ static struct clksrc_clk *clksrc_cdev[] = { ...@@ -503,6 +509,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uclk, &clk_sclk_uclk,
&clk_sclk_spi0, &clk_sclk_spi0,
&clk_sclk_spi1, &clk_sclk_spi1,
&clk_sclk_mmc0,
&clk_sclk_mmc1,
&clk_sclk_mmc2
}; };
static struct clk_lookup s5p6440_clk_lookup[] = { static struct clk_lookup s5p6440_clk_lookup[] = {
...@@ -511,6 +520,9 @@ static struct clk_lookup s5p6440_clk_lookup[] = { ...@@ -511,6 +520,9 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
}; };
void __init_or_cpufreq s5p6440_setup_clocks(void) void __init_or_cpufreq s5p6440_setup_clocks(void)
......
arch/arm/mach-s5p64x0/clock-s5p6450.c
View file @ 0818c527
...@@ -412,36 +412,6 @@ static struct clksrc_clk clk_sclk_audio0 = { ...@@ -412,36 +412,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
static struct clksrc_clk clksrcs[] = { static struct clksrc_clk clksrcs[] = {
{ {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
}, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
...@@ -507,6 +477,42 @@ static struct clksrc_clk clksrcs[] = { ...@@ -507,6 +477,42 @@ static struct clksrc_clk clksrcs[] = {
}, },
}; };
static struct clksrc_clk clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
};
static struct clksrc_clk clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
};
static struct clksrc_clk clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
.sources = &clkset_group2,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_sclk_uclk = { static struct clksrc_clk clk_sclk_uclk = {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
...@@ -546,6 +552,9 @@ static struct clksrc_clk *clksrc_cdev[] = { ...@@ -546,6 +552,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uclk, &clk_sclk_uclk,
&clk_sclk_spi0, &clk_sclk_spi0,
&clk_sclk_spi1, &clk_sclk_spi1,
&clk_sclk_mmc0,
&clk_sclk_mmc1,
&clk_sclk_mmc2,
}; };
static struct clk_lookup s5p6450_clk_lookup[] = { static struct clk_lookup s5p6450_clk_lookup[] = {
...@@ -554,6 +563,9 @@ static struct clk_lookup s5p6450_clk_lookup[] = { ...@@ -554,6 +563,9 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
}; };
/* Clock initialization code */ /* Clock initialization code */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7