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Commit 0921f1ef authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'cris-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris 

Pull CRIS changes from Jesper Nilsson:
 "Mostly another batch of code removal due to move to standard
  frameworks for CRISv32, initial devicetree configuration for a couple
  of boards, and some small fixes for kgdb and time handling"

* tag 'cris-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper/cris:
  cris: Drop reference to get_cmos_time()
  CRIS: Drop code related to obsolete or unused kconfigs
  cris: time: Cleanup of persistent clock stuff
  cris: re-use helpers to dump data in hex format
  CRIS v32: remove old GPIO and LEDs code
  CRIS v32: remove I2C bitbanging driver
  CRIS v32: add ARTPEC-3 and P1343 device trees
  CRIS v32: dev88: add GPIO, LEDs, RTC, temp sensor
  CRIS: add dt-bindings symlink
  CRIS v32: increase NR_IRQS
  cris: arch-v10: kgdb: Add '__used' for static variable is_dyn_brkp
  cris: arch-v10: kgdb: Use BAR instead of DTP0 for register P12
  cris: kgdb: use native hex2bin
parents 15f93405 4247896f
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arch/cris/Kconfig
View file @ 0921f1ef
......@@ -57,7 +57,6 @@ config CRIS
select ARCH_WANT_IPC_PARSE_VERSION
select GENERIC_IRQ_SHOW
select GENERIC_IOMAP
select GENERIC_CMOS_UPDATE
select MODULES_USE_ELF_RELA
select CLONE_BACKWARDS2
select OLD_SIGSUSPEND
......
arch/cris/arch-v10/kernel/head.S
View file @ 0921f1ef
......@@ -354,63 +354,6 @@ no_command_line:
blo 1b
nop
#ifdef CONFIG_BLK_DEV_ETRAXIDE
;; disable ATA before enabling it in genconfig below
moveq 0,$r0
move.d $r0,[R_ATA_CTRL_DATA]
move.d $r0,[R_ATA_TRANSFER_CNT]
move.d $r0,[R_ATA_CONFIG]
#if 0
move.d R_PORT_G_DATA, $r1
move.d $r0, [$r1]; assert ATA bus-reset
nop
nop
nop
nop
nop
nop
move.d 0x08000000,$r0
move.d $r0,[$r1]
#endif
#endif
#ifdef CONFIG_JULIETTE
;; configure external DMA channel 0 before enabling it in genconfig
moveq 0,$r0
move.d $r0,[R_EXT_DMA_0_ADDR]
; cnt enable, word size, output, stop, size 0
move.d IO_STATE (R_EXT_DMA_0_CMD, cnt, enable) \
| IO_STATE (R_EXT_DMA_0_CMD, rqpol, ahigh) \
| IO_STATE (R_EXT_DMA_0_CMD, apol, ahigh) \
| IO_STATE (R_EXT_DMA_0_CMD, rq_ack, burst) \
| IO_STATE (R_EXT_DMA_0_CMD, wid, word) \
| IO_STATE (R_EXT_DMA_0_CMD, dir, output) \
| IO_STATE (R_EXT_DMA_0_CMD, run, stop) \
| IO_FIELD (R_EXT_DMA_0_CMD, trf_count, 0),$r0
move.d $r0,[R_EXT_DMA_0_CMD]
;; reset dma4 and wait for completion
moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
move.b $r0,[R_DMA_CH4_CMD]
1: move.b [R_DMA_CH4_CMD],$r0
and.b IO_MASK (R_DMA_CH4_CMD, cmd),$r0
cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
beq 1b
nop
;; reset dma5 and wait for completion
moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
move.b $r0,[R_DMA_CH5_CMD]
1: move.b [R_DMA_CH5_CMD],$r0
and.b IO_MASK (R_DMA_CH5_CMD, cmd),$r0
cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
beq 1b
nop
#endif
;; Etrax product HW genconfig setup
moveq 0,$r0
......@@ -447,21 +390,6 @@ no_command_line:
| IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
#if defined(CONFIG_ETRAX_DEF_R_PORT_G0_DIR_OUT)
or.d IO_STATE (R_GEN_CONFIG, g0dir, out),$r0
#endif
#if defined(CONFIG_ETRAX_DEF_R_PORT_G8_15_DIR_OUT)
or.d IO_STATE (R_GEN_CONFIG, g8_15dir, out),$r0
#endif
#if defined(CONFIG_ETRAX_DEF_R_PORT_G16_23_DIR_OUT)
or.d IO_STATE (R_GEN_CONFIG, g16_23dir, out),$r0
#endif
#if defined(CONFIG_ETRAX_DEF_R_PORT_G24_DIR_OUT)
or.d IO_STATE (R_GEN_CONFIG, g24dir, out),$r0
#endif
move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG
move.d $r0,[R_GEN_CONFIG]
......@@ -500,19 +428,9 @@ no_command_line:
;; including their shadow registers
move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0
#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7)
or.b IO_STATE (R_PORT_PA_DIR, dir7, output),$r0
#endif
move.b $r0,[port_pa_dir_shadow]
move.b $r0,[R_PORT_PA_DIR]
move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0
#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PA7)
#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
and.b ~(1 << 7),$r0
#else
or.b (1 << 7),$r0
#endif
#endif
move.b $r0,[port_pa_data_shadow]
move.b $r0,[R_PORT_PA_DATA]
......@@ -520,19 +438,9 @@ no_command_line:
move.b $r0,[port_pb_config_shadow]
move.b $r0,[R_PORT_PB_CONFIG]
move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0
#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5)
or.b IO_STATE (R_PORT_PB_DIR, dir5, output),$r0
#endif
move.b $r0,[port_pb_dir_shadow]
move.b $r0,[R_PORT_PB_DIR]
move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0
#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_PB5)
#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
and.b ~(1 << 5),$r0
#else
or.b (1 << 5),$r0
#endif
#endif
move.b $r0,[port_pb_data_shadow]
move.b $r0,[R_PORT_PB_DATA]
......@@ -541,20 +449,6 @@ no_command_line:
move.d $r0, [R_PORT_PB_I2C]
moveq 0,$r0
#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G10)
#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
and.d ~(1 << 10),$r0
#else
or.d (1 << 10),$r0
#endif
#endif
#if defined(CONFIG_BLUETOOTH) && defined(CONFIG_BLUETOOTH_RESET_G11)
#if defined(CONFIG_BLUETOOTH_RESET_ACTIVE_HIGH)
and.d ~(1 << 11),$r0
#else
or.d (1 << 11),$r0
#endif
#endif
move.d $r0,[port_g_data_shadow]
move.d $r0,[R_PORT_G_DATA]
......
arch/cris/arch-v10/kernel/kgdb.c
View file @ 0921f1ef
......@@ -275,7 +275,7 @@ static char remcomOutBuffer[BUFMAX];
/* Error and warning messages. */
enum error_type
{
SUCCESS, E01, E02, E03, E04, E05, E06, E07
SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
};
static char *error_message[] =
{
......@@ -286,7 +286,8 @@ static char *error_message[] =
"E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
"E05 Change register content - P - the register is not implemented..",
"E06 Change memory content - M - internal error.",
"E07 Change register content - P - the register is not stored on the stack"
"E07 Change register content - P - the register is not stored on the stack",
"E08 Invalid parameter"
};
/********************************* Register image ****************************/
/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's
......@@ -351,7 +352,7 @@ char internal_stack[INTERNAL_STACK_SIZE];
breakpoint to be handled. A static breakpoint uses the content of register
BRP as it is whereas a dynamic breakpoint requires subtraction with 2
in order to execute the instruction. The first breakpoint is static. */
static unsigned char is_dyn_brkp = 0;
static unsigned char __used is_dyn_brkp;
/********************************* String library ****************************/
/* Single-step over library functions creates trap loops. */
......@@ -413,18 +414,6 @@ gdb_cris_strtol (const char *s, char **endptr, int base)
}
/********************************** Packet I/O ******************************/
/* Returns the integer equivalent of a hexadecimal character. */
static int
hex (char ch)
{
if ((ch >= 'a') && (ch <= 'f'))
return (ch - 'a' + 10);
if ((ch >= '0') && (ch <= '9'))
return (ch - '0');
if ((ch >= 'A') && (ch <= 'F'))
return (ch - 'A' + 10);
return (-1);
}
/* Convert the memory, pointed to by mem into hexadecimal representation.
Put the result in buf, and return a pointer to the last character
......@@ -455,22 +444,6 @@ mem2hex(char *buf, unsigned char *mem, int count)
return (buf);
}
/* Convert the array, in hexadecimal representation, pointed to by buf into
binary representation. Put the result in mem, and return a pointer to
the character after the last byte written. */
static unsigned char*
hex2mem (unsigned char *mem, char *buf, int count)
{
int i;
unsigned char ch;
for (i = 0; i < count; i++) {
ch = hex (*buf++) << 4;
ch = ch + hex (*buf++);
*mem++ = ch;
}
return (mem);
}
/* Put the content of the array, in binary representation, pointed to by buf
into memory pointed to by mem, and return a pointer to the character after
the last byte written.
......@@ -524,8 +497,8 @@ getpacket (char *buffer)
buffer[count] = '\0';
if (ch == '#') {
xmitcsum = hex (getDebugChar ()) << 4;
xmitcsum += hex (getDebugChar ());
xmitcsum = hex_to_bin(getDebugChar()) << 4;
xmitcsum += hex_to_bin(getDebugChar());
if (checksum != xmitcsum) {
/* Wrong checksum */
putDebugChar ('-');
......@@ -599,7 +572,7 @@ putDebugString (const unsigned char *str, int length)
/********************************* Register image ****************************/
/* Write a value to a specified register in the register image of the current
thread. Returns status code SUCCESS, E02 or E05. */
thread. Returns status code SUCCESS, E02, E05 or E08. */
static int
write_register (int regno, char *val)
{
......@@ -608,8 +581,9 @@ write_register (int regno, char *val)
if (regno >= R0 && regno <= PC) {
/* 32-bit register with simple offset. */
hex2mem ((unsigned char *)current_reg + regno * sizeof(unsigned int),
val, sizeof(unsigned int));
if (hex2bin((unsigned char *)current_reg + regno * sizeof(unsigned int),
val, sizeof(unsigned int)))
status = E08;
}
else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
/* Do not support read-only registers. */
......@@ -618,13 +592,15 @@ write_register (int regno, char *val)
else if (regno == CCR) {
/* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented,
and P7 (MOF) is 32 bits in ETRAX 100LX. */
hex2mem ((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short),
val, sizeof(unsigned short));
if (hex2bin((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short),
val, sizeof(unsigned short)))
status = E08;
}
else if (regno >= MOF && regno <= USP) {
/* 32 bit register with complex offset. (P8 has been taken care of.) */
hex2mem ((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int),
val, sizeof(unsigned int));
if (hex2bin((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int),
val, sizeof(unsigned int)))
status = E08;
}
else {
/* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
......@@ -759,9 +735,11 @@ handle_exception (int sigval)
/* Write registers. GXX..XX
Each byte of register data is described by two hex digits.
Success: OK
Failure: void. */
hex2mem((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers));
gdb_cris_strcpy (remcomOutBuffer, "OK");
Failure: E08. */
if (hex2bin((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers)))
gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
else
gdb_cris_strcpy (remcomOutBuffer, "OK");
break;
case 'P':
......@@ -771,7 +749,7 @@ handle_exception (int sigval)
for each byte in the register (target byte order). P1f=11223344 means
set register 31 to 44332211.
Success: OK
Failure: E02, E05 */
Failure: E02, E05, E08 */
{
char *suffix;
int regno = gdb_cris_strtol (&remcomInBuffer[1], &suffix, 16);
......@@ -791,6 +769,10 @@ handle_exception (int sigval)
/* Do not support non-existing registers on the stack. */
gdb_cris_strcpy (remcomOutBuffer, error_message[E07]);
break;
case E08:
/* Invalid parameter. */
gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
break;
default:
/* Valid register number. */
gdb_cris_strcpy (remcomOutBuffer, "OK");
......@@ -826,7 +808,7 @@ handle_exception (int sigval)
AA..AA is the start address, LLLL is the number of bytes, and
XX..XX is the hexadecimal data.
Success: OK
Failure: void. */
Failure: E08. */
{
char *lenptr;
char *dataptr;
......@@ -835,14 +817,15 @@ handle_exception (int sigval)
int length = gdb_cris_strtol(lenptr+1, &dataptr, 16);
if (*lenptr == ',' && *dataptr == ':') {
if (remcomInBuffer[0] == 'M') {
hex2mem(addr, dataptr + 1, length);
}
else /* X */ {
if (hex2bin(addr, dataptr + 1, length))
gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
else
gdb_cris_strcpy (remcomOutBuffer, "OK");
} else /* X */ {
bin2mem(addr, dataptr + 1, length);
gdb_cris_strcpy (remcomOutBuffer, "OK");
}
gdb_cris_strcpy (remcomOutBuffer, "OK");
}
else {
} else {
gdb_cris_strcpy (remcomOutBuffer, error_message[E06]);
}
}
......@@ -970,7 +953,7 @@ asm ("\n"
" move $ibr,[cris_reg+0x4E] ; P9,\n"
" move $irp,[cris_reg+0x52] ; P10,\n"
" move $srp,[cris_reg+0x56] ; P11,\n"
" move $dtp0,[cris_reg+0x5A] ; P12, register BAR, assembler might not know BAR\n"
" move $bar,[cris_reg+0x5A] ; P12,\n"
" ; P13, register DCCR already saved\n"
";; Due to the old assembler-versions BRP might not be recognized\n"
" .word 0xE670 ; move brp,r0\n"
......@@ -1063,7 +1046,7 @@ asm ("\n"
" move $ibr,[cris_reg+0x4E] ; P9,\n"
" move $irp,[cris_reg+0x52] ; P10,\n"
" move $srp,[cris_reg+0x56] ; P11,\n"
" move $dtp0,[cris_reg+0x5A] ; P12, register BAR, assembler might not know BAR\n"
" move $bar,[cris_reg+0x5A] ; P12,\n"
" ; P13, register DCCR already saved\n"
";; Due to the old assembler-versions BRP might not be recognized\n"
" .word 0xE670 ; move brp,r0\n"
......
arch/cris/arch-v10/mm/init.c
View file @ 0921f1ef
......@@ -68,14 +68,10 @@ paging_init(void)
*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */
IO_STATE(R_MMU_KSEG, seg_e, page ) |
IO_STATE(R_MMU_KSEG, seg_d, page ) |
IO_STATE(R_MMU_KSEG, seg_c, page ) |
IO_STATE(R_MMU_KSEG, seg_d, page ) |
IO_STATE(R_MMU_KSEG, seg_c, page ) |
IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
#ifdef CONFIG_JULIETTE
IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */
#else
IO_STATE(R_MMU_KSEG, seg_a, page ) |
#endif
IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
......@@ -92,14 +88,10 @@ paging_init(void)
IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
#ifdef CONFIG_JULIETTE
IO_FIELD(R_MMU_KBASE_HI, base_a, 0xa ) |
#else
IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
#endif
IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
*R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) |
IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
......
arch/cris/arch-v32/Kconfig
View file @ 0921f1ef
......@@ -10,95 +10,6 @@ config ETRAX_DRAM_VIRTUAL_BASE
depends on ETRAX_ARCH_V32
default "c0000000"
choice
prompt "Nbr of Ethernet LED groups"
depends on ETRAX_ARCH_V32
default ETRAX_NBR_LED_GRP_ONE
help
Select how many Ethernet LED groups that can be used. Usually one per Ethernet
interface is a good choice.
config ETRAX_NBR_LED_GRP_ZERO
bool "Use zero LED groups"
help
Select this if you do not want any Ethernet LEDs.
config ETRAX_NBR_LED_GRP_ONE
bool "Use one LED group"
help
Select this if you want one Ethernet LED group. This LED group
can be used for one or more Ethernet interfaces. However, it is
recommended that each Ethernet interface use a dedicated LED group.
config ETRAX_NBR_LED_GRP_TWO
bool "Use two LED groups"
help
Select this if you want two Ethernet LED groups. This is the
best choice if you have more than one Ethernet interface and
would like to have separate LEDs for the interfaces.
endchoice
config ETRAX_LED_G_NET0
string "Ethernet LED group 0 green LED bit"
depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
default "PA3"
help
Bit to use for the green LED in Ethernet LED group 0.
config ETRAX_LED_R_NET0
string "Ethernet LED group 0 red LED bit"
depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
default "PA4"
help
Bit to use for the red LED in Ethernet LED group 0.
config ETRAX_LED_G_NET1
string "Ethernet group 1 green LED bit"
depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
default ""
help
Bit to use for the green LED in Ethernet LED group 1.
config ETRAX_LED_R_NET1
string "Ethernet group 1 red LED bit"
depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
default ""
help
Bit to use for the red LED in Ethernet LED group 1.
config ETRAX_V32_LED2G
string "Second green LED bit"
depends on ETRAX_ARCH_V32
default "PA5"
help
Bit to use for the first green LED (status LED).
Most Axis products use bit A5 here.
config ETRAX_V32_LED2R
string "Second red LED bit"
depends on ETRAX_ARCH_V32
default "PA6"
help
Bit to use for the first red LED (network LED).
Most Axis products use bit A6 here.
config ETRAX_V32_LED3G
string "Third green LED bit"
depends on ETRAX_ARCH_V32
default "PA7"
help
Bit to use for the first green LED (drive/power LED).
Most Axis products use bit A7 here.
config ETRAX_V32_LED3R
string "Third red LED bit"
depends on ETRAX_ARCH_V32
default "PA7"
help
Bit to use for the first red LED (drive/power LED).
Most Axis products use bit A7 here.
choice
prompt "Kernel GDB port"
depends on ETRAX_KGDB
......
arch/cris/arch-v32/drivers/Kconfig
View file @ 0921f1ef
......@@ -149,173 +149,6 @@ config ETRAX_NANDBOOT
Say Y if your boot code, kernel and root file system is in
NAND flash. Say N if they are in NOR flash.
config ETRAX_I2C
bool "I2C driver"
depends on ETRAX_ARCH_V32
help
This option enables the I2C driver used by e.g. the RTC driver.
config ETRAX_V32_I2C_DATA_PORT
string "I2C data pin"
depends on ETRAX_I2C
help
The pin to use for I2C data.
config ETRAX_V32_I2C_CLK_PORT
string "I2C clock pin"
depends on ETRAX_I2C
help
The pin to use for I2C clock.
config ETRAX_GPIO
bool "GPIO support"
depends on ETRAX_ARCH_V32
---help---
Enables the ETRAX general port device (major 120, minors 0-4).
You can use this driver to access the general port bits. It supports
these ioctl's:
#include <linux/etraxgpio.h>
fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
err = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READ_INBITS), &val);
Remember that you need to setup the port directions appropriately in
the General configuration.
config ETRAX_VIRTUAL_GPIO
bool "Virtual GPIO support"
depends on ETRAX_GPIO
help
Enables the virtual Etrax general port device (major 120, minor 6).
It uses an I/O expander for the I2C-bus.
config ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN
int "Virtual GPIO interrupt pin on PA pin"
range 0 7
depends on ETRAX_VIRTUAL_GPIO
help
The pin to use on PA for virtual gpio interrupt.
config ETRAX_PA_CHANGEABLE_DIR
hex "PA user changeable dir mask"
depends on ETRAX_GPIO
default "0x00" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PA that a
user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0 here, but it depends on your hardware.
config ETRAX_PA_CHANGEABLE_BITS
hex "PA user changeable bits mask"
depends on ETRAX_GPIO
default "0x00" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PA
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PB_CHANGEABLE_DIR
hex "PB user changeable dir mask"
depends on ETRAX_GPIO
default "0x00000" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PB
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0 here, but it depends on your hardware.
config ETRAX_PB_CHANGEABLE_BITS
hex "PB user changeable bits mask"
depends on ETRAX_GPIO
default "0x00000" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PB
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PC_CHANGEABLE_DIR
hex "PC user changeable dir mask"
depends on ETRAX_GPIO
default "0x00000" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PC
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0 here, but it depends on your hardware.
config ETRAX_PC_CHANGEABLE_BITS
hex "PC user changeable bits mask"
depends on ETRAX_GPIO
default "0x00000" if ETRAXFS
default "0x00000000" if !ETRAXFS
help
This is a bitmask with information of what bits in PC
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PD_CHANGEABLE_DIR
hex "PD user changeable dir mask"
depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask with information of what bits in PD
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0x00000 here, but it depends on your hardware.
config ETRAX_PD_CHANGEABLE_BITS
hex "PD user changeable bits mask"
depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PD
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PE_CHANGEABLE_DIR
hex "PE user changeable dir mask"
depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PE
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0x00000 here, but it depends on your hardware.
config ETRAX_PE_CHANGEABLE_BITS
hex "PE user changeable bits mask"
depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PE
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_PV_CHANGEABLE_DIR
hex "PV user changeable dir mask"
depends on ETRAX_VIRTUAL_GPIO
default "0x0000"
help
This is a bitmask (16 bits) with information of what bits in PV
that a user can change direction on using ioctl's.
Bit set = changeable.
You probably want 0x0000 here, but it depends on your hardware.
config ETRAX_PV_CHANGEABLE_BITS
hex "PV user changeable bits mask"
depends on ETRAX_VIRTUAL_GPIO
default "0x0000"
help
This is a bitmask (16 bits) with information of what bits in PV
that a user can change the value on using ioctl's.
Bit set = changeable.
config ETRAX_CARDBUS
bool "Cardbus support"
depends on ETRAX_ARCH_V32
......
arch/cris/arch-v32/drivers/Makefile
View file @ 0921f1ef
......@@ -7,6 +7,5 @@ obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
obj-$(CONFIG_ETRAXFS) += mach-fs/
obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/
obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o
obj-$(CONFIG_ETRAX_I2C) += i2c.o
obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
obj-$(CONFIG_PCI) += pci/
arch/cris/arch-v32/drivers/axisflashmap.c
View file @ 0921f1ef
......@@ -361,7 +361,7 @@ static int __init init_axis_flash(void)
#if 0 /* Dump flash memory so we can see what is going on */
if (main_mtd) {
int sectoraddr, i;
int sectoraddr;
for (sectoraddr = 0; sectoraddr < 2*65536+4096;
sectoraddr += PAGESIZE) {
main_mtd->read(main_mtd, sectoraddr, PAGESIZE, &len,
......@@ -369,21 +369,7 @@ static int __init init_axis_flash(void)
printk(KERN_INFO
"Sector at %d (length %d):\n",
sectoraddr, len);
for (i = 0; i < PAGESIZE; i += 16) {
printk(KERN_INFO
"%02x %02x %02x %02x "
"%02x %02x %02x %02x "
"%02x %02x %02x %02x "
"%02x %02x %02x %02x\n",
page[i] & 255, page[i+1] & 255,
page[i+2] & 255, page[i+3] & 255,
page[i+4] & 255, page[i+5] & 255,
page[i+6] & 255, page[i+7] & 255,
page[i+8] & 255, page[i+9] & 255,
page[i+10] & 255, page[i+11] & 255,
page[i+12] & 255, page[i+13] & 255,
page[i+14] & 255, page[i+15] & 255);
}
print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, page, PAGESIZE, false);
}
}
#endif
......@@ -417,25 +403,11 @@ static int __init init_axis_flash(void)
#if 0 /* Dump partition table so we can see what is going on */
printk(KERN_INFO
"axisflashmap: flash read %d bytes at 0x%08x, data: "
"%02x %02x %02x %02x %02x %02x %02x %02x\n",
len, CONFIG_ETRAX_PTABLE_SECTOR,
page[0] & 255, page[1] & 255,
page[2] & 255, page[3] & 255,
page[4] & 255, page[5] & 255,
page[6] & 255, page[7] & 255);
"axisflashmap: flash read %d bytes at 0x%08x, data: %8ph\n",
len, CONFIG_ETRAX_PTABLE_SECTOR, page);
printk(KERN_INFO
"axisflashmap: partition table offset %d, data: "
"%02x %02x %02x %02x %02x %02x %02x %02x\n",
PARTITION_TABLE_OFFSET,
page[PARTITION_TABLE_OFFSET+0] & 255,
page[PARTITION_TABLE_OFFSET+1] & 255,
page[PARTITION_TABLE_OFFSET+2] & 255,
page[PARTITION_TABLE_OFFSET+3] & 255,
page[PARTITION_TABLE_OFFSET+4] & 255,
page[PARTITION_TABLE_OFFSET+5] & 255,
page[PARTITION_TABLE_OFFSET+6] & 255,
page[PARTITION_TABLE_OFFSET+7] & 255);
"axisflashmap: partition table offset %d, data: %8ph\n",
PARTITION_TABLE_OFFSET, page + PARTITION_TABLE_OFFSET);
#endif
}
......
arch/cris/arch-v32/drivers/i2c.c deleted 100644 → 0
View file @ 15f93405
This diff is collapsed.
arch/cris/arch-v32/drivers/i2c.h deleted 100644 → 0
View file @ 15f93405
#include <linux/init.h>
/* High level I2C actions */
int i2c_write(unsigned char theSlave, void *data, size_t nbytes);
int i2c_read(unsigned char theSlave, void *data, size_t nbytes);
int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
/* Low level I2C */
void i2c_start(void);
void i2c_stop(void);
void i2c_outbyte(unsigned char x);
unsigned char i2c_inbyte(void);
int i2c_getack(void);
void i2c_sendack(void);
arch/cris/arch-v32/drivers/mach-a3/Makefile
View file @ 0921f1ef
......@@ -3,4 +3,3 @@
#
obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
obj-$(CONFIG_ETRAX_GPIO) += gpio.o
arch/cris/arch-v32/drivers/mach-a3/gpio.c deleted 100644 → 0
View file @ 15f93405
This diff is collapsed.
arch/cris/arch-v32/drivers/mach-fs/Makefile
View file @ 0921f1ef
......@@ -3,4 +3,3 @@
#
obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
obj-$(CONFIG_ETRAX_GPIO) += gpio.o
arch/cris/arch-v32/drivers/mach-fs/gpio.c deleted 100644 → 0
View file @ 15f93405
This diff is collapsed.
arch/cris/arch-v32/kernel/crisksyms.c
View file @ 0921f1ef
......@@ -3,7 +3,6 @@
#include <arch/dma.h>
#include <arch/intmem.h>
#include <mach/pinmux.h>
#include <arch/io.h>
/* Functions for allocating DMA channels */
EXPORT_SYMBOL(crisv32_request_dma);
......@@ -20,8 +19,6 @@ EXPORT_SYMBOL(crisv32_pinmux_alloc);
EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed);
EXPORT_SYMBOL(crisv32_pinmux_dealloc);
EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed);
EXPORT_SYMBOL(crisv32_io_get_name);
EXPORT_SYMBOL(crisv32_io_get);
/* Functions masking/unmasking interrupts */
EXPORT_SYMBOL(crisv32_mask_irq);
......
arch/cris/arch-v32/kernel/debugport.c
View file @ 0921f1ef
......@@ -77,8 +77,6 @@ static struct dbg_port *port =
&ports[2];
#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
&ports[3];
#elif defined(CONFIG_ETRAX_DEBUG_PORT4)
&ports[4];
#else
NULL;
#endif
......
arch/cris/arch-v32/kernel/head.S
View file @ 0921f1ef
......@@ -292,11 +292,7 @@ _no_romfs_in_flash:
;; For cramfs, partition starts with magic and length.
;; For jffs2, a jhead is prepended which contains with magic and length.
;; The jhead is not part of the jffs2 partition however.
#ifndef CONFIG_ETRAXFS_SIM
move.d __bss_start, $r0
#else
move.d __end, $r0
#endif
move.d [$r0], $r1
cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic?
beq 2f ; yes, jump
......
arch/cris/arch-v32/kernel/irq.c
View file @ 0921f1ef
......@@ -37,7 +37,7 @@
#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
#elif defined(CONFIG_ETRAX_KGDB_PORT1)
#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
#elif defined(CONFIG_ETRAX_KGB_PORT2)
#elif defined(CONFIG_ETRAX_KGDB_PORT2)
#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
#elif defined(CONFIG_ETRAX_KGDB_PORT3)
#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
......@@ -464,14 +464,14 @@ init_IRQ(void)
etrax_irv->v[i] = weird_irq;
np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");
domain = irq_domain_add_legacy(np, NR_IRQS - FIRST_IRQ,
domain = irq_domain_add_legacy(np, NBR_INTR_VECT - FIRST_IRQ,
FIRST_IRQ, FIRST_IRQ,
&crisv32_irq_ops, NULL);
BUG_ON(!domain);
irq_set_default_host(domain);
of_node_put(np);
for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT; i++, j++) {
set_exception_vector(i, interrupt[j]);
}
......
arch/cris/arch-v32/kernel/kgdb.c
View file @ 0921f1ef
......@@ -384,19 +384,11 @@ int getDebugChar(void);
/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
void putDebugChar(int val);
/* Returns the integer equivalent of a hexadecimal character. */
static int hex(char ch);
/* Convert the memory, pointed to by mem into hexadecimal representation.
Put the result in buf, and return a pointer to the last character
in buf (null). */
static char *mem2hex(char *buf, unsigned char *mem, int count);
/* Convert the array, in hexadecimal representation, pointed to by buf into
binary representation. Put the result in mem, and return a pointer to
the character after the last byte written. */
static unsigned char *hex2mem(unsigned char *mem, char *buf, int count);
/* Put the content of the array, in binary representation, pointed to by buf
into memory pointed to by mem, and return a pointer to
the character after the last byte written. */
......@@ -449,7 +441,7 @@ static char output_buffer[BUFMAX];
/* Error and warning messages. */
enum error_type
{
SUCCESS, E01, E02, E03, E04, E05, E06,
SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
};
static char *error_message[] =
......@@ -461,6 +453,8 @@ static char *error_message[] =
"E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
"E05 Change register content - P - the register is not implemented..",
"E06 Change memory content - M - internal error.",
"E07 Change register content - P - the register is not stored on the stack",
"E08 Invalid parameter"
};
/********************************** Breakpoint *******************************/
......@@ -539,7 +533,7 @@ gdb_cris_strtol(const char *s, char **endptr, int base)
/********************************* Register image ****************************/
/* Write a value to a specified register in the register image of the current
thread. Returns status code SUCCESS, E02 or E05. */
thread. Returns status code SUCCESS, E02, E05 or E08. */
static int
write_register(int regno, char *val)
{
......@@ -547,8 +541,9 @@ write_register(int regno, char *val)
if (regno >= R0 && regno <= ACR) {
/* Consecutive 32-bit registers. */
hex2mem((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int),
val, sizeof(unsigned int));
if (hex2bin((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int),
val, sizeof(unsigned int)))
status = E08;
} else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
/* Read-only registers. */
......@@ -557,16 +552,19 @@ write_register(int regno, char *val)
} else if (regno == PID) {
/* 32-bit register. (Even though we already checked SRS and WZ, we cannot
combine this with the EXS - SPC write since SRS and WZ have different size.) */
hex2mem((unsigned char *)&reg.pid, val, sizeof(unsigned int));
if (hex2bin((unsigned char *)&reg.pid, val, sizeof(unsigned int)))
status = E08;
} else if (regno == SRS) {
/* 8-bit register. */
hex2mem((unsigned char *)&reg.srs, val, sizeof(unsigned char));
if (hex2bin((unsigned char *)&reg.srs, val, sizeof(unsigned char)))
status = E08;
} else if (regno >= EXS && regno <= SPC) {
/* Consecutive 32-bit registers. */
hex2mem((unsigned char *)&reg.exs + (regno - EXS) * sizeof(unsigned int),
val, sizeof(unsigned int));
if (hex2bin((unsigned char *)&reg.exs + (regno - EXS) * sizeof(unsigned int),
val, sizeof(unsigned int)))
status = E08;
} else if (regno == PC) {
/* Pseudo-register. Treat as read-only. */
......@@ -574,7 +572,9 @@ write_register(int regno, char *val)
} else if (regno >= S0 && regno <= S15) {
/* 32-bit registers. */
hex2mem((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int), val, sizeof(unsigned int));
if (hex2bin((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int),
val, sizeof(unsigned int)))
status = E08;
} else {
/* Non-existing register. */
status = E05;
......@@ -630,19 +630,6 @@ read_register(char regno, unsigned int *valptr)
}
/********************************** Packet I/O ******************************/
/* Returns the integer equivalent of a hexadecimal character. */
static int
hex(char ch)
{
if ((ch >= 'a') && (ch <= 'f'))
return (ch - 'a' + 10);
if ((ch >= '0') && (ch <= '9'))
return (ch - '0');
if ((ch >= 'A') && (ch <= 'F'))
return (ch - 'A' + 10);
return -1;
}
/* Convert the memory, pointed to by mem into hexadecimal representation.
Put the result in buf, and return a pointer to the last character
in buf (null). */
......@@ -689,22 +676,6 @@ mem2hex_nbo(char *buf, unsigned char *mem, int count)
return buf;
}
/* Convert the array, in hexadecimal representation, pointed to by buf into
binary representation. Put the result in mem, and return a pointer to
the character after the last byte written. */
static unsigned char*
hex2mem(unsigned char *mem, char *buf, int count)
{
int i;
unsigned char ch;
for (i = 0; i < count; i++) {
ch = hex (*buf++) << 4;
ch = ch + hex (*buf++);
*mem++ = ch;
}
return mem;
}
/* Put the content of the array, in binary representation, pointed to by buf
into memory pointed to by mem, and return a pointer to the character after
the last byte written.
......@@ -763,8 +734,8 @@ getpacket(char *buffer)
buffer[count] = 0;
if (ch == '#') {
xmitcsum = hex(getDebugChar()) << 4;
xmitcsum += hex(getDebugChar());
xmitcsum = hex_to_bin(getDebugChar()) << 4;
xmitcsum += hex_to_bin(getDebugChar());
if (checksum != xmitcsum) {
/* Wrong checksum */
putDebugChar('-');
......@@ -1304,14 +1275,17 @@ handle_exception(int sigval)
/* Write registers. GXX..XX
Each byte of register data is described by two hex digits.
Success: OK
Failure: void. */
Failure: E08. */
/* General and special registers. */
hex2mem((char *)&reg, &input_buffer[1], sizeof(registers));
if (hex2bin((char *)&reg, &input_buffer[1], sizeof(registers)))
gdb_cris_strcpy(output_buffer, error_message[E08]);
/* Support registers. */
hex2mem((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
else if (hex2bin((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
&input_buffer[1] + sizeof(registers),
16 * sizeof(unsigned int));
gdb_cris_strcpy(output_buffer, "OK");
16 * sizeof(unsigned int)))
gdb_cris_strcpy(output_buffer, error_message[E08]);
else
gdb_cris_strcpy(output_buffer, "OK");
break;
case 'P':
......@@ -1338,6 +1312,10 @@ handle_exception(int sigval)
/* Do not support non-existing registers. */
gdb_cris_strcpy(output_buffer, error_message[E05]);
break;
case E08:
/* Invalid parameter. */
gdb_cris_strcpy(output_buffer, error_message[E08]);
break;
default:
/* Valid register number. */
gdb_cris_strcpy(output_buffer, "OK");
......@@ -1380,7 +1358,7 @@ handle_exception(int sigval)
AA..AA is the start address, LLLL is the number of bytes, and
XX..XX is the hexadecimal data.
Success: OK
Failure: void. */
Failure: E08. */
{
char *lenptr;
char *dataptr;
......@@ -1389,13 +1367,15 @@ handle_exception(int sigval)
int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
if (*lenptr == ',' && *dataptr == ':') {
if (input_buffer[0] == 'M') {
hex2mem(addr, dataptr + 1, len);
if (hex2bin(addr, dataptr + 1, len))
gdb_cris_strcpy(output_buffer, error_message[E08]);
else
gdb_cris_strcpy(output_buffer, "OK");
} else /* X */ {
bin2mem(addr, dataptr + 1, len);
gdb_cris_strcpy(output_buffer, "OK");
}
gdb_cris_strcpy(output_buffer, "OK");
}
else {
} else {
gdb_cris_strcpy(output_buffer, error_message[E06]);
}
}
......
arch/cris/arch-v32/kernel/setup.c
View file @ 0921f1ef
......@@ -128,10 +128,6 @@ static struct i2c_board_info __initdata i2c_info[] = {
{I2C_BOARD_INFO("tmp100", 0x4E)},
#ifdef CONFIG_RTC_DRV_PCF8563
{I2C_BOARD_INFO("pcf8563", 0x51)},
#endif
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
{I2C_BOARD_INFO("vgpio", 0x20)},
{I2C_BOARD_INFO("vgpio", 0x21)},
#endif
{I2C_BOARD_INFO("pca9536", 0x41)},
{I2C_BOARD_INFO("fnp300", 0x40)},
......@@ -146,10 +142,6 @@ static struct i2c_board_info __initdata i2c_info2[] = {
{I2C_BOARD_INFO("tmp100", 0x4C)},
{I2C_BOARD_INFO("tmp100", 0x4D)},
{I2C_BOARD_INFO("tmp100", 0x4E)},
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
{I2C_BOARD_INFO("vgpio", 0x20)},
{I2C_BOARD_INFO("vgpio", 0x21)},
#endif
{I2C_BOARD_INFO("pca9536", 0x41)},
{I2C_BOARD_INFO("fnp300", 0x40)},
{I2C_BOARD_INFO("fnp300", 0x42)},
......
arch/cris/arch-v32/mach-a3/Makefile
View file @ 0921f1ef
......@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := dma.o pinmux.o io.o arbiter.o
obj-y := dma.o pinmux.o arbiter.o
clean:
arch/cris/arch-v32/mach-a3/io.c deleted 100644 → 0
View file @ 15f93405
/*
* Helper functions for I/O pins.
*
* Copyright (c) 2005-2007 Axis Communications AB.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/io.h>
#include <mach/pinmux.h>
#include <hwregs/gio_defs.h>
struct crisv32_ioport crisv32_ioports[] = {
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
32
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
32
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
16
},
};
#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
struct crisv32_iopin crisv32_led_net0_green;
struct crisv32_iopin crisv32_led_net0_red;
struct crisv32_iopin crisv32_led2_green;
struct crisv32_iopin crisv32_led2_red;
struct crisv32_iopin crisv32_led3_green;
struct crisv32_iopin crisv32_led3_red;
/* Dummy port used when green LED and red LED is on the same bit */
static unsigned long io_dummy;
static struct crisv32_ioport dummy_port = {
&io_dummy,
&io_dummy,
&io_dummy,
32
};
static struct crisv32_iopin dummy_led = {
&dummy_port,
0
};
static int __init crisv32_io_init(void)
{
int ret = 0;
u32 i;
/* Locks *should* be dynamically initialized. */
for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
spin_lock_init(&crisv32_ioports[i].lock);
spin_lock_init(&dummy_port.lock);
/* Initialize LEDs */
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
ret += crisv32_io_get_name(&crisv32_led_net0_green,
CONFIG_ETRAX_LED_G_NET0);
crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
ret += crisv32_io_get_name(&crisv32_led_net0_red,
CONFIG_ETRAX_LED_R_NET0);
crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
} else
crisv32_led_net0_red = dummy_led;
#endif
ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
return ret;
}
__initcall(crisv32_io_init);
int crisv32_io_get(struct crisv32_iopin *iopin,
unsigned int port, unsigned int pin)
{
if (port > NBR_OF_PORTS)
return -EINVAL;
if (port > crisv32_ioports[port].pin_count)
return -EINVAL;
iopin->bit = 1 << pin;
iopin->port = &crisv32_ioports[port];
if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
return -EIO;
return 0;
}
int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
{
int port;
int pin;
if (toupper(*name) == 'P')
name++;
if (toupper(*name) < 'A' || toupper(*name) > 'E')
return -EINVAL;
port = toupper(*name) - 'A';
name++;
pin = simple_strtoul(name, NULL, 10);
if (pin < 0 || pin > crisv32_ioports[port].pin_count)
return -EINVAL;
iopin->bit = 1 << pin;
iopin->port = &crisv32_ioports[port];
if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
return -EIO;
return 0;
}
#ifdef CONFIG_PCI
/* PCI I/O access stuff */
struct cris_io_operations *cris_iops = NULL;
EXPORT_SYMBOL(cris_iops);
#endif
arch/cris/arch-v32/mach-fs/Kconfig
View file @ 0921f1ef
......@@ -192,25 +192,6 @@ config ETRAX_DEF_GIO_PE_OUT
Configures the initial data for the general port E bits. Most
products should use 00000 here.
config ETRAX_DEF_GIO_PV_OE
hex "GIO_PV_OE"
depends on ETRAX_VIRTUAL_GPIO
default "0000"
help
Configures the direction of virtual general port V bits. 1 is out,
0 is in. This is often totally different depending on the product
used. These bits are used for all kinds of stuff. If you don't know
what to use, it is always safe to put all as inputs, although
floating inputs isn't good.
config ETRAX_DEF_GIO_PV_OUT
hex "GIO_PV_OUT"
depends on ETRAX_VIRTUAL_GPIO
default "0000"
help
Configures the initial data for the virtual general port V bits.
Most products should use 0000 here.
endmenu
endif
arch/cris/arch-v32/mach-fs/Makefile
View file @ 0921f1ef
......@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := dma.o pinmux.o io.o arbiter.o
obj-y := dma.o pinmux.o arbiter.o
clean:
arch/cris/arch-v32/mach-fs/io.c deleted 100644 → 0
View file @ 15f93405
/*
* Helper functions for I/O pins.
*
* Copyright (c) 2004-2007 Axis Communications AB.
*/
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/io.h>
#include <mach/pinmux.h>
#include <hwregs/gio_defs.h>
#ifndef DEBUG
#define DEBUG(x)
#endif
struct crisv32_ioport crisv32_ioports[] = {
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
8
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
18
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
18
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pd_din),
18
},
{
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_oe),
(unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_dout),
(unsigned long *)REG_ADDR(gio, regi_gio, r_pe_din),
18
}
};
#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
struct crisv32_iopin crisv32_led_net0_green;
struct crisv32_iopin crisv32_led_net0_red;
struct crisv32_iopin crisv32_led_net1_green;
struct crisv32_iopin crisv32_led_net1_red;
struct crisv32_iopin crisv32_led2_green;
struct crisv32_iopin crisv32_led2_red;
struct crisv32_iopin crisv32_led3_green;
struct crisv32_iopin crisv32_led3_red;
/* Dummy port used when green LED and red LED is on the same bit */
static unsigned long io_dummy;
static struct crisv32_ioport dummy_port = {
&io_dummy,
&io_dummy,
&io_dummy,
18
};
static struct crisv32_iopin dummy_led = {
&dummy_port,
0
};
static int __init crisv32_io_init(void)
{
int ret = 0;
u32 i;
/* Locks *should* be dynamically initialized. */
for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
spin_lock_init(&crisv32_ioports[i].lock);
spin_lock_init(&dummy_port.lock);
/* Initialize LEDs */
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
ret +=
crisv32_io_get_name(&crisv32_led_net0_green,
CONFIG_ETRAX_LED_G_NET0);
crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
ret +=
crisv32_io_get_name(&crisv32_led_net0_red,
CONFIG_ETRAX_LED_R_NET0);
crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
} else
crisv32_led_net0_red = dummy_led;
#endif
#ifdef CONFIG_ETRAX_NBR_LED_GRP_TWO
ret +=
crisv32_io_get_name(&crisv32_led_net1_green,
CONFIG_ETRAX_LED_G_NET1);
crisv32_io_set_dir(&crisv32_led_net1_green, crisv32_io_dir_out);
if (strcmp(CONFIG_ETRAX_LED_G_NET1, CONFIG_ETRAX_LED_R_NET1)) {
crisv32_io_get_name(&crisv32_led_net1_red,
CONFIG_ETRAX_LED_R_NET1);
crisv32_io_set_dir(&crisv32_led_net1_red, crisv32_io_dir_out);
} else
crisv32_led_net1_red = dummy_led;
#endif
ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
return ret;
}
__initcall(crisv32_io_init);
int crisv32_io_get(struct crisv32_iopin *iopin,
unsigned int port, unsigned int pin)
{
if (port > NBR_OF_PORTS)
return -EINVAL;
if (port > crisv32_ioports[port].pin_count)
return -EINVAL;
iopin->bit = 1 << pin;
iopin->port = &crisv32_ioports[port];
/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
return -EIO;
DEBUG(printk(KERN_DEBUG "crisv32_io_get: Allocated pin %d on port %d\n",
pin, port));
return 0;
}
int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
{
int port;
int pin;
if (toupper(*name) == 'P')
name++;
if (toupper(*name) < 'A' || toupper(*name) > 'E')
return -EINVAL;
port = toupper(*name) - 'A';
name++;
pin = simple_strtoul(name, NULL, 10);
if (pin < 0 || pin > crisv32_ioports[port].pin_count)
return -EINVAL;
iopin->bit = 1 << pin;
iopin->port = &crisv32_ioports[port];
/* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
/* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
return -EIO;
DEBUG(printk(KERN_DEBUG
"crisv32_io_get_name: Allocated pin %d on port %d\n",
pin, port));
return 0;
}
#ifdef CONFIG_PCI
/* PCI I/O access stuff */
struct cris_io_operations *cris_iops = NULL;
EXPORT_SYMBOL(cris_iops);
#endif
arch/cris/boot/dts/artpec3.dtsi 0 → 100644
View file @ 0921f1ef
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "axis,crisv32";
reg = <0>;
};
};
soc {
compatible = "simple-bus";
model = "artpec3";
#address-cells = <1>;
#size-cells = <1>;
ranges;
intc: interrupt-controller {
compatible = "axis,crisv32-intc";
reg = <0xb002a000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};
gio: gpio@b0020000 {
compatible = "axis,artpec3-gio";
reg = <0xb0020000 0x1000>;
interrupts = <61>;
gpio-controller;
#gpio-cells = <3>;
};
serial@b003e000 {
compatible = "axis,etraxfs-uart";
reg = <0xb003e000 0x1000>;
interrupts = <64>;
status = "disabled";
};
};
};
arch/cris/boot/dts/dev88.dts
View file @ 0921f1ef
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
/include/ "etraxfs.dtsi"
/ {
......@@ -15,4 +17,51 @@ uart0: serial@b00260000 {
status = "okay";
};
};
spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
gpio-sck = <&gio 1 0 0xd>;
gpio-miso = <&gio 4 0 0xd>;
gpio-mosi = <&gio 0 0 0xd>;
cs-gpios = <&gio 3 0 0xd>;
num-chipselects = <1>;
temp-sensor@0 {
compatible = "ti,lm70";
reg = <0>;
spi-max-frequency = <100000>;
};
};
i2c {
compatible = "i2c-gpio";
gpios = <&gio 5 0 0xd>, <&gio 6 0 0xd>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
leds {
compatible = "gpio-leds";
network {
label = "network";
gpios = <&gio 2 GPIO_ACTIVE_LOW 0xa>;
};
status {
label = "status";
gpios = <&gio 3 GPIO_ACTIVE_LOW 0xa>;
linux,default-trigger = "heartbeat";
};
};
};
arch/cris/boot/dts/etraxfs.dtsi
View file @ 0921f1ef
......@@ -28,6 +28,14 @@ intc: interrupt-controller {
#interrupt-cells = <1>;
};
gio: gpio@b001a000 {
compatible = "axis,etraxfs-gio";
reg = <0xb001a000 0x1000>;
interrupts = <50>;
gpio-controller;
#gpio-cells = <3>;
};
serial@b00260000 {
compatible = "axis,etraxfs-uart";
reg = <0xb0026000 0x1000>;
......
arch/cris/boot/dts/include/dt-bindings 0 → 120000
View file @ 0921f1ef
../../../../../include/dt-bindings
\ No newline at end of file
arch/cris/boot/dts/p1343.dts 0 → 100644
View file @ 0921f1ef
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/include/ "artpec3.dtsi"
/ {
model = "Axis P1343 Network Camera";
compatible = "axis,p1343";
aliases {
serial0 = &uart0;
};
soc {
uart0: serial@b003e000 {
status = "okay";
};
};
i2c {
compatible = "i2c-gpio";
gpios = <&gio 3 0 0xa>, <&gio 2 0 0xa>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
leds {
compatible = "gpio-leds";
status_green {
label = "status:green";
gpios = <&gio 0 GPIO_ACTIVE_LOW 0xc>;
linux,default-trigger = "heartbeat";
};
status_red {
label = "status:red";
gpios = <&gio 1 GPIO_ACTIVE_LOW 0xc>;
};
network_green {
label = "network:green";
gpios = <&gio 2 GPIO_ACTIVE_LOW 0xc>;
};
network_red {
label = "network:red";
gpios = <&gio 3 GPIO_ACTIVE_LOW 0xc>;
};
power_red {
label = "power:red";
gpios = <&gio 4 GPIO_ACTIVE_LOW 0xc>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
activity-button@0 {
label = "Activity Button";
linux,code = <KEY_FN>;
gpios = <&gio 13 GPIO_ACTIVE_LOW 0xd>;
};
};
};
arch/cris/boot/rescue/head_v10.S
View file @ 0921f1ef
......@@ -281,9 +281,6 @@ wait_ser:
#ifdef CONFIG_ETRAX_PB_LEDS
move.b $r2, [R_PORT_PB_DATA]
#endif
#ifdef CONFIG_ETRAX_90000000_LEDS
move.b $r2, [0x90000000]
#endif
#endif
;; check if we got something on the serial port
......
arch/cris/include/arch-v32/arch/io.h deleted 100644 → 0
View file @ 15f93405
#ifndef _ASM_ARCH_CRIS_IO_H
#define _ASM_ARCH_CRIS_IO_H
#include <linux/spinlock.h>
#include <hwregs/reg_map.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/gio_defs.h>
enum crisv32_io_dir
{
crisv32_io_dir_in = 0,
crisv32_io_dir_out = 1
};
struct crisv32_ioport
{
volatile unsigned long *oe;
volatile unsigned long *data;
volatile unsigned long *data_in;
unsigned int pin_count;
spinlock_t lock;
};
struct crisv32_iopin
{
struct crisv32_ioport* port;
int bit;
};
extern struct crisv32_ioport crisv32_ioports[];
extern struct crisv32_iopin crisv32_led1_green;
extern struct crisv32_iopin crisv32_led1_red;
extern struct crisv32_iopin crisv32_led2_green;
extern struct crisv32_iopin crisv32_led2_red;
extern struct crisv32_iopin crisv32_led3_green;
extern struct crisv32_iopin crisv32_led3_red;
extern struct crisv32_iopin crisv32_led_net0_green;
extern struct crisv32_iopin crisv32_led_net0_red;
extern struct crisv32_iopin crisv32_led_net1_green;
extern struct crisv32_iopin crisv32_led_net1_red;
static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
{
unsigned long flags;
spin_lock_irqsave(&iopin->port->lock, flags);
if (iopin->port->data) {
if (val)
*iopin->port->data |= iopin->bit;
else
*iopin->port->data &= ~iopin->bit;
}
spin_unlock_irqrestore(&iopin->port->lock, flags);
}
static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
enum crisv32_io_dir dir)
{
unsigned long flags;
spin_lock_irqsave(&iopin->port->lock, flags);
if (iopin->port->oe) {
if (dir == crisv32_io_dir_in)
*iopin->port->oe &= ~iopin->bit;
else
*iopin->port->oe |= iopin->bit;
}
spin_unlock_irqrestore(&iopin->port->lock, flags);
}
static inline int crisv32_io_rd(struct crisv32_iopin* iopin)
{
return ((*iopin->port->data_in & iopin->bit) ? 1 : 0);
}
int crisv32_io_get(struct crisv32_iopin* iopin,
unsigned int port, unsigned int pin);
int crisv32_io_get_name(struct crisv32_iopin* iopin,
const char *name);
#define CRIS_LED_OFF 0x00
#define CRIS_LED_GREEN 0x01
#define CRIS_LED_RED 0x02
#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
#define CRIS_LED_NETWORK_GRP0_SET(x) \
do { \
CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \
CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \
} while (0)
#else
#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {}
#endif
#define CRIS_LED_NETWORK_GRP0_SET_G(x) \
crisv32_io_set(&crisv32_led_net0_green, !(x));
#define CRIS_LED_NETWORK_GRP0_SET_R(x) \
crisv32_io_set(&crisv32_led_net0_red, !(x));
#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
#define CRIS_LED_NETWORK_GRP1_SET(x) \
do { \
CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \
CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \
} while (0)
#else
#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {}
#endif
#define CRIS_LED_NETWORK_GRP1_SET_G(x) \
crisv32_io_set(&crisv32_led_net1_green, !(x));
#define CRIS_LED_NETWORK_GRP1_SET_R(x) \
crisv32_io_set(&crisv32_led_net1_red, !(x));
#define CRIS_LED_ACTIVE_SET(x) \
do { \
CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
} while (0)
#define CRIS_LED_ACTIVE_SET_G(x) \
crisv32_io_set(&crisv32_led2_green, !(x));
#define CRIS_LED_ACTIVE_SET_R(x) \
crisv32_io_set(&crisv32_led2_red, !(x));
#define CRIS_LED_DISK_WRITE(x) \
do{\
crisv32_io_set(&crisv32_led3_green, !(x)); \
crisv32_io_set(&crisv32_led3_red, !(x)); \
}while(0)
#define CRIS_LED_DISK_READ(x) \
crisv32_io_set(&crisv32_led3_green, !(x));
#endif
arch/cris/include/arch-v32/arch/irq.h
View file @ 0921f1ef
......@@ -4,7 +4,7 @@
#include <hwregs/intr_vect.h>
/* Number of non-cpu interrupts. */
#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */
#define NR_IRQS (NBR_INTR_VECT + 256) /* Exceptions + IRQs */
#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */
#if NR_REAL_IRQS > 32
......
arch/cris/include/asm/eshlibld.h
View file @ 0921f1ef
......@@ -45,8 +45,7 @@
assumed that we want to share code when debugging (exposes more
trouble). */
#ifndef SHARE_LIB_CORE
# if (defined(__KERNEL__) || !defined(RELOC_DEBUG)) \
&& !defined(CONFIG_SHARE_SHLIB_CORE)
# if (defined(__KERNEL__) || !defined(RELOC_DEBUG))
# define SHARE_LIB_CORE 0
# else
# define SHARE_LIB_CORE 1
......
arch/cris/include/asm/io.h
View file @ 0921f1ef
......@@ -2,7 +2,9 @@
#define _ASM_CRIS_IO_H
#include <asm/page.h> /* for __va, __pa */
#ifdef CONFIG_ETRAX_ARCH_V10
#include <arch/io.h>
#endif
#include <asm-generic/iomap.h>
#include <linux/kernel.h>
......
arch/cris/include/uapi/asm/etraxgpio.h
View file @ 0921f1ef
......@@ -11,26 +11,6 @@
* g1-g7 and g25-g31 is both input and outputs but on different pins
* Also note that some bits change pins depending on what interfaces
* are enabled.
*
* For ETRAX FS (CONFIG_ETRAXFS):
* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
* /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
* /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
* /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction
* /dev/leds minor 2, Access to leds depending on kernelconfig
*
* For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
* /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction
* /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction
* /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction
* /dev/gpiod minor 4, 32 bit GPIO, input only
* /dev/leds minor 2, Access to leds depending on kernelconfig
* /dev/pwm0 minor 16, PWM channel 0 on PA30
* /dev/pwm1 minor 17, PWM channel 1 on PA31
* /dev/pwm2 minor 18, PWM channel 2 on PB26
* /dev/ppwm minor 19, PPWM channel
*
*/
#ifndef _ASM_ETRAXGPIO_H
#define _ASM_ETRAXGPIO_H
......@@ -40,52 +20,12 @@
#define ETRAXGPIO_IOCTYPE 43
/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
#ifdef CONFIG_ETRAX_ARCH_V10
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
#define GPIO_MINOR_G 3
#define GPIO_MINOR_LAST 3
#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
#endif
#ifdef CONFIG_ETRAXFS
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
#define GPIO_MINOR_C 3
#define GPIO_MINOR_D 4
#define GPIO_MINOR_E 5
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
#define GPIO_MINOR_V 6
#define GPIO_MINOR_LAST 6
#else
#define GPIO_MINOR_LAST 5
#endif
#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
#endif
#ifdef CONFIG_CRIS_MACH_ARTPEC3
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_LEDS 2
#define GPIO_MINOR_C 3
#define GPIO_MINOR_D 4
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
#define GPIO_MINOR_V 6
#define GPIO_MINOR_LAST 6
#else
#define GPIO_MINOR_LAST 4
#endif
#define GPIO_MINOR_FIRST_PWM 16
#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0)
#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1)
#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2)
#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3)
#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM
#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM
#endif
/* supported ioctl _IOC_NR's */
......@@ -139,101 +79,4 @@
#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
/* *arg updated with current output pins. */
/* The following ioctl's are applicable to the PWM channels only */
#define IO_PWM_SET_MODE 0x20
enum io_pwm_mode {
PWM_OFF = 0, /* disabled, deallocated */
PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
PWM_VARFREQ = 3, /* individually configurable high/low periods */
PWM_SOFT = 4 /* software generated */
};
struct io_pwm_set_mode {
enum io_pwm_mode mode;
};
/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns
* from 10ns (value = 0) to 81920ns (value = 8191)
* (Resulting frequencies range from 50 MHz (10ns + 10ns) down to
* 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty
* cycle (81920 + 10ns or 10ns + 81920ns, respectively).)
*/
#define IO_PWM_SET_PERIOD 0x21
struct io_pwm_set_period {
unsigned int lo; /* 0..8191 */
unsigned int hi; /* 0..8191 */
};
/* Only for modes PWM_STANDARD and PWM_FAST.
* For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from
* 0 (value = 0) to 255/256 (value = 255).
* For PWM_FAST, set duty cycle of PWM output signal from
* 0% (value = 0) to 100% (value = 255). Output signal in this mode
* is a 10ns pulse surrounded by a high or low level depending on duty
* cycle (except for 0% and 100% which result in a constant output).
* Resulting output frequency varies from 50 MHz at 50% duty cycle,
* down to 390 kHz at min/max duty cycle.
*/
#define IO_PWM_SET_DUTY 0x22
struct io_pwm_set_duty {
int duty; /* 0..255 */
};
/* Returns information about the latest PWM pulse.
* lo: Length of the latest low period, in units of 10ns.
* hi: Length of the latest high period, in units of 10ns.
* cnt: Time since last detected edge, in units of 10ns.
*
* The input source to PWM is decied by IO_PWM_SET_INPUT_SRC.
*
* NOTE: All PWM devices is connected to the same input source.
*/
#define IO_PWM_GET_PERIOD 0x23
struct io_pwm_get_period {
unsigned int lo;
unsigned int hi;
unsigned int cnt;
};
/* Sets the input source for the PWM input. For the src value see the
* register description for gio:rw_pwm_in_cfg.
*
* NOTE: All PWM devices is connected to the same input source.
*/
#define IO_PWM_SET_INPUT_SRC 0x24
struct io_pwm_set_input_src {
unsigned int src; /* 0..7 */
};
/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */
#define IO_PPWM_SET_DUTY 0x25
struct io_ppwm_set_duty {
int duty; /* 0..255 */
};
/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure
* PWM capable gpio pins:
*/
#define IO_PWMCLK_SETGET_CONFIG 0x26
struct gpio_pwmclk_conf {
unsigned int gpiopin; /* The pin number based on the opened device */
unsigned int baseclk; /* The base clock to use, or sw will select one close*/
unsigned int low; /* The number of low periods of the baseclk */
unsigned int high; /* The number of high periods of the baseclk */
};
/* Examples:
* To get a symmetric 12 MHz clock without knowing anything about the hardware:
* baseclk = 12000000, low = 0, high = 0
* To just get info of current setting:
* baseclk = 0, low = 0, high = 0, the values will be updated by driver.
*/
#endif
arch/cris/kernel/crisksyms.c
View file @ 0921f1ef
......@@ -18,7 +18,6 @@
#include <asm/pgtable.h>
#include <asm/fasttimer.h>
extern unsigned long get_cmos_time(void);
extern void __Udiv(void);
extern void __Umod(void);
extern void __Div(void);
......@@ -30,7 +29,6 @@ extern void __negdi2(void);
extern void iounmap(volatile void * __iomem);
/* Platform dependent support */
EXPORT_SYMBOL(get_cmos_time);
EXPORT_SYMBOL(loops_per_usec);
/* Math functions */
......
arch/cris/kernel/time.c
View file @ 0921f1ef
......@@ -39,31 +39,6 @@
extern unsigned long loops_per_jiffy; /* init/main.c */
unsigned long loops_per_usec;
int set_rtc_mmss(unsigned long nowtime)
{
D(printk(KERN_DEBUG "set_rtc_mmss(%lu)\n", nowtime));
return 0;
}
/* grab the time from the RTC chip */
unsigned long get_cmos_time(void)
{
return 0;
}
int update_persistent_clock(struct timespec now)
{
return set_rtc_mmss(now.tv_sec);
}
void read_persistent_clock(struct timespec *ts)
{
ts->tv_sec = 0;
ts->tv_nsec = 0;
}
extern void cris_profile_sample(struct pt_regs* regs);
void
......
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