Commit 0b0c1dbd authored by Linus Walleij's avatar Linus Walleij Committed by Russell King

ARM: 9006/1: uncompress: Wait for ready and busy in debug prints

For some platforms such as Qualcomm we need to wait for the
UART to be ready before writing characters to the UART
in the same manner as the macro in debug.S used with the
main "Uncompressing Linux ..." text. Pass an extra temporary
variable to writeb and make it call waituarttxrdy and
busyuart just like the other decomression messages.

Optionally it will also call waituartcts if and only if
CONFIG_DEBUG_UART_FLOW_CONTROL is selected.

After this the decompression debug messages work fine on
Qualcomm platforms if you compile head.S with -DDEBUG.

Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 4df24fef
...@@ -28,19 +28,19 @@ ...@@ -28,19 +28,19 @@
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
.macro loadsp, rb, tmp1, tmp2 .macro loadsp, rb, tmp1, tmp2
.endm .endm
.macro writeb, ch, rb .macro writeb, ch, rb, tmp
mcr p14, 0, \ch, c0, c5, 0 mcr p14, 0, \ch, c0, c5, 0
.endm .endm
#elif defined(CONFIG_CPU_XSCALE) #elif defined(CONFIG_CPU_XSCALE)
.macro loadsp, rb, tmp1, tmp2 .macro loadsp, rb, tmp1, tmp2
.endm .endm
.macro writeb, ch, rb .macro writeb, ch, rb, tmp
mcr p14, 0, \ch, c8, c0, 0 mcr p14, 0, \ch, c8, c0, 0
.endm .endm
#else #else
.macro loadsp, rb, tmp1, tmp2 .macro loadsp, rb, tmp1, tmp2
.endm .endm
.macro writeb, ch, rb .macro writeb, ch, rb, tmp
mcr p14, 0, \ch, c1, c0, 0 mcr p14, 0, \ch, c1, c0, 0
.endm .endm
#endif #endif
...@@ -49,8 +49,13 @@ ...@@ -49,8 +49,13 @@
#include CONFIG_DEBUG_LL_INCLUDE #include CONFIG_DEBUG_LL_INCLUDE
.macro writeb, ch, rb .macro writeb, ch, rb, tmp
#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL
waituartcts \tmp, \rb
#endif
waituarttxrdy \tmp, \rb
senduart \ch, \rb senduart \ch, \rb
busyuart \tmp, \rb
.endm .endm
#if defined(CONFIG_ARCH_SA1100) #if defined(CONFIG_ARCH_SA1100)
...@@ -1326,7 +1331,7 @@ puts: loadsp r3, r2, r1 ...@@ -1326,7 +1331,7 @@ puts: loadsp r3, r2, r1
1: ldrb r2, [r0], #1 1: ldrb r2, [r0], #1
teq r2, #0 teq r2, #0
moveq pc, lr moveq pc, lr
2: writeb r2, r3 2: writeb r2, r3, r1
mov r1, #0x00020000 mov r1, #0x00020000
3: subs r1, r1, #1 3: subs r1, r1, #1
bne 3b bne 3b
......
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