Commit 0bc5680a authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown

ASoC: fsl_spdif: spba clk is needed by spdif device

SPDIF need to enable the spba clock, when sdma is using share peripheral
script. In this case, there is two spba master port is used, if don't
enable the clock, the spba bus will have arbitration issue, which may
cause read/write wrong data from/to SPDIF registers.
Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@freescale.com>
Acked-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 8005c49d
...@@ -27,6 +27,11 @@ Required properties: ...@@ -27,6 +27,11 @@ Required properties:
Transceiver Clock Diagram" of SoC reference manual. Transceiver Clock Diagram" of SoC reference manual.
It can also be referred to TxClk_Source bit of It can also be referred to TxClk_Source bit of
register SPDIF_STC. register SPDIF_STC.
"spba" The spba clock is required when SPDIF is placed as a
bus slave of the Shared Peripheral Bus and when two
or more bus masters (CPU, DMA or DSP) try to access
it. This property is optional depending on the SoC
design.
- big-endian : If this property is absent, the native endian mode - big-endian : If this property is absent, the native endian mode
will be in use as default, or the big endian mode will be in use as default, or the big endian mode
......
...@@ -88,6 +88,7 @@ struct spdif_mixer_control { ...@@ -88,6 +88,7 @@ struct spdif_mixer_control {
* @rxclk: rx clock sources for capture * @rxclk: rx clock sources for capture
* @coreclk: core clock for register access via DMA * @coreclk: core clock for register access via DMA
* @sysclk: system clock for rx clock rate measurement * @sysclk: system clock for rx clock rate measurement
* @spbaclk: SPBA clock (optional, depending on SoC design)
* @dma_params_tx: DMA parameters for transmit channel * @dma_params_tx: DMA parameters for transmit channel
* @dma_params_rx: DMA parameters for receive channel * @dma_params_rx: DMA parameters for receive channel
*/ */
...@@ -106,6 +107,7 @@ struct fsl_spdif_priv { ...@@ -106,6 +107,7 @@ struct fsl_spdif_priv {
struct clk *rxclk; struct clk *rxclk;
struct clk *coreclk; struct clk *coreclk;
struct clk *sysclk; struct clk *sysclk;
struct clk *spbaclk;
struct snd_dmaengine_dai_dma_data dma_params_tx; struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_dai_dma_data dma_params_rx; struct snd_dmaengine_dai_dma_data dma_params_rx;
/* regcache for SRPC */ /* regcache for SRPC */
...@@ -474,6 +476,14 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream, ...@@ -474,6 +476,14 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream,
return ret; return ret;
} }
if (!IS_ERR(spdif_priv->spbaclk)) {
ret = clk_prepare_enable(spdif_priv->spbaclk);
if (ret) {
dev_err(&pdev->dev, "failed to enable spba clock\n");
goto err_spbaclk;
}
}
ret = spdif_softreset(spdif_priv); ret = spdif_softreset(spdif_priv);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to soft reset\n"); dev_err(&pdev->dev, "failed to soft reset\n");
...@@ -515,6 +525,9 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream, ...@@ -515,6 +525,9 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream,
for (i--; i >= 0; i--) for (i--; i >= 0; i--)
clk_disable_unprepare(spdif_priv->txclk[i]); clk_disable_unprepare(spdif_priv->txclk[i]);
err: err:
if (!IS_ERR(spdif_priv->spbaclk))
clk_disable_unprepare(spdif_priv->spbaclk);
err_spbaclk:
clk_disable_unprepare(spdif_priv->coreclk); clk_disable_unprepare(spdif_priv->coreclk);
return ret; return ret;
...@@ -548,6 +561,8 @@ static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, ...@@ -548,6 +561,8 @@ static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
spdif_intr_status_clear(spdif_priv); spdif_intr_status_clear(spdif_priv);
regmap_update_bits(regmap, REG_SPDIF_SCR, regmap_update_bits(regmap, REG_SPDIF_SCR,
SCR_LOW_POWER, SCR_LOW_POWER); SCR_LOW_POWER, SCR_LOW_POWER);
if (!IS_ERR(spdif_priv->spbaclk))
clk_disable_unprepare(spdif_priv->spbaclk);
clk_disable_unprepare(spdif_priv->coreclk); clk_disable_unprepare(spdif_priv->coreclk);
} }
} }
...@@ -1261,6 +1276,10 @@ static int fsl_spdif_probe(struct platform_device *pdev) ...@@ -1261,6 +1276,10 @@ static int fsl_spdif_probe(struct platform_device *pdev)
return PTR_ERR(spdif_priv->coreclk); return PTR_ERR(spdif_priv->coreclk);
} }
spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
if (IS_ERR(spdif_priv->spbaclk))
dev_warn(&pdev->dev, "no spba clock in devicetree\n");
/* Select clock source for rx/tx clock */ /* Select clock source for rx/tx clock */
spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
if (IS_ERR(spdif_priv->rxclk)) { if (IS_ERR(spdif_priv->rxclk)) {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment