Commit 0e3d4373 authored by Minghuan Lian's avatar Minghuan Lian Committed by Scott Wood

powerpc/dts: fix sRIO error interrupt for b4860

For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.
Signed-off-by: default avatarMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 682775b8
......@@ -41,7 +41,7 @@ &pci0 {
&rio {
compatible = "fsl,srio";
interrupts = <16 2 1 11>;
interrupts = <16 2 1 20>;
#address-cells = <2>;
#size-cells = <2>;
fsl,iommu-parent = <&pamu0>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment