Skip to content

L
linux
Commit 0f5c2ac5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge branch 'irq-cleanup-for-linus' of... 

Merge branch 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (37 commits)
  um: Use generic irq Kconfig
  tile: Use generic irq Kconfig
  sparc: Use generic irq Kconfig
  score: Use generic irq Kconfig
  powerpc: Use generic irq Kconfig
  parisc: Use generic irq Kconfig
  mn10300: Use generic irq Kconfig
  microblaze: Use generic irq Kconfig
  m68knommu: Use generic irq Kconfig
  ia64: Use generic irq Kconfig
  frv: Use generic irq Kconfig
  blackfin: Use generic irq Kconfig
  alpha: Use generic irq Kconfig
  genirq: Remove __do_IRQ
  m32r: Convert to generic irq Kconfig
  m32r: Convert usrv platform irq handling
  m32r: Convert opsput_lcdpld irq chip
  m32r: Convert opsput lanpld irq chip
  m32r: Convert opsput pld irq chip
  m32r: Convert opsput irq chip
  ...
parents cfd74486 dfff95c3
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 428 additions and 1048 deletions
Documentation/feature-removal-schedule.txt
View file @ 0f5c2ac5
...@@ -357,14 +357,6 @@ Who: Dave Jones <davej@redhat.com>, Matthew Garrett <mjg@redhat.com> ...@@ -357,14 +357,6 @@ Who: Dave Jones <davej@redhat.com>, Matthew Garrett <mjg@redhat.com>
----------------------------- -----------------------------
What: __do_IRQ all in one fits nothing interrupt handler
When: 2.6.32
Why: __do_IRQ was kept for easy migration to the type flow handlers.
More than two years of migration time is enough.
Who: Thomas Gleixner <tglx@linutronix.de>
-----------------------------
What: fakephp and associated sysfs files in /sys/bus/pci/slots/ What: fakephp and associated sysfs files in /sys/bus/pci/slots/
When: 2011 When: 2011
Why: In 2.6.27, the semantics of /sys/bus/pci/slots was redefined to Why: In 2.6.27, the semantics of /sys/bus/pci/slots was redefined to
......
arch/alpha/Kconfig
View file @ 0f5c2ac5
...@@ -8,6 +8,9 @@ config ALPHA ...@@ -8,6 +8,9 @@ config ALPHA
select HAVE_IRQ_WORK select HAVE_IRQ_WORK
select HAVE_PERF_EVENTS select HAVE_PERF_EVENTS
select HAVE_DMA_ATTRS select HAVE_DMA_ATTRS
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
select AUTO_IRQ_AFFINITY if SMP
help help
The Alpha is a 64-bit general-purpose processor designed and The Alpha is a 64-bit general-purpose processor designed and
marketed by the Digital Equipment Corporation of blessed memory, marketed by the Digital Equipment Corporation of blessed memory,
...@@ -68,22 +71,6 @@ config GENERIC_IOMAP ...@@ -68,22 +71,6 @@ config GENERIC_IOMAP
bool bool
default n default n
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config GENERIC_HARDIRQS
bool
default y
config GENERIC_IRQ_PROBE
bool
default y
config AUTO_IRQ_AFFINITY
bool
depends on SMP
default y
source "init/Kconfig" source "init/Kconfig"
source "kernel/Kconfig.freezer" source "kernel/Kconfig.freezer"
......
arch/blackfin/Kconfig
View file @ 0f5c2ac5
...@@ -30,6 +30,9 @@ config BLACKFIN ...@@ -30,6 +30,9 @@ config BLACKFIN
select HAVE_KERNEL_LZO if RAMKERNEL select HAVE_KERNEL_LZO if RAMKERNEL
select HAVE_OPROFILE select HAVE_OPROFILE
select ARCH_WANT_OPTIONAL_GPIOLIB select ARCH_WANT_OPTIONAL_GPIOLIB
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
select IRQ_PER_CPU if SMP
config GENERIC_CSUM config GENERIC_CSUM
def_bool y def_bool y
...@@ -44,15 +47,6 @@ config ZONE_DMA ...@@ -44,15 +47,6 @@ config ZONE_DMA
config GENERIC_FIND_NEXT_BIT config GENERIC_FIND_NEXT_BIT
def_bool y def_bool y
config GENERIC_HARDIRQS
def_bool y
config GENERIC_IRQ_PROBE
def_bool y
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config GENERIC_GPIO config GENERIC_GPIO
def_bool y def_bool y
...@@ -254,11 +248,6 @@ config HOTPLUG_CPU ...@@ -254,11 +248,6 @@ config HOTPLUG_CPU
depends on SMP && HOTPLUG depends on SMP && HOTPLUG
default y default y
config IRQ_PER_CPU
bool
depends on SMP
default y
config HAVE_LEGACY_PER_CPU_AREA config HAVE_LEGACY_PER_CPU_AREA
def_bool y def_bool y
depends on SMP depends on SMP
......
arch/cris/Kconfig
View file @ 0f5c2ac5
...@@ -54,6 +54,8 @@ config CRIS ...@@ -54,6 +54,8 @@ config CRIS
bool bool
default y default y
select HAVE_IDE select HAVE_IDE
select HAVE_GENERIC_HARDIRQS
select GENERIC_HARDIRQS_NO_DEPRECATED
config HZ config HZ
int int
...@@ -67,10 +69,6 @@ menu "General setup" ...@@ -67,10 +69,6 @@ menu "General setup"
source "fs/Kconfig.binfmt" source "fs/Kconfig.binfmt"
config GENERIC_HARDIRQS
bool
default y
config ETRAX_CMDLINE config ETRAX_CMDLINE
string "Kernel command line" string "Kernel command line"
default "root=/dev/mtdblock3" default "root=/dev/mtdblock3"
......
arch/cris/arch-v10/kernel/irq.c
View file @ 0f5c2ac5
...@@ -104,43 +104,21 @@ static void (*interrupt[NR_IRQS])(void) = { ...@@ -104,43 +104,21 @@ static void (*interrupt[NR_IRQS])(void) = {
IRQ31_interrupt IRQ31_interrupt
}; };
static void enable_crisv10_irq(unsigned int irq); static void enable_crisv10_irq(struct irq_data *data)
static unsigned int startup_crisv10_irq(unsigned int irq)
{
enable_crisv10_irq(irq);
return 0;
}
#define shutdown_crisv10_irq disable_crisv10_irq
static void enable_crisv10_irq(unsigned int irq)
{
crisv10_unmask_irq(irq);
}
static void disable_crisv10_irq(unsigned int irq)
{
crisv10_mask_irq(irq);
}
static void ack_crisv10_irq(unsigned int irq)
{ {
crisv10_unmask_irq(data->irq);
} }
static void end_crisv10_irq(unsigned int irq) static void disable_crisv10_irq(struct irq_data *data)
{ {
crisv10_mask_irq(data->irq);
} }
static struct irq_chip crisv10_irq_type = { static struct irq_chip crisv10_irq_type = {
.name = "CRISv10", .name = "CRISv10",
.startup = startup_crisv10_irq, .irq_shutdown = disable_crisv10_irq,
.shutdown = shutdown_crisv10_irq, .irq_enable = enable_crisv10_irq,
.enable = enable_crisv10_irq, .irq_disable = disable_crisv10_irq,
.disable = disable_crisv10_irq,
.ack = ack_crisv10_irq,
.end = end_crisv10_irq,
.set_affinity = NULL
}; };
void weird_irq(void); void weird_irq(void);
...@@ -221,7 +199,8 @@ init_IRQ(void) ...@@ -221,7 +199,8 @@ init_IRQ(void)
/* Initialize IRQ handler descriptors. */ /* Initialize IRQ handler descriptors. */
for(i = 2; i < NR_IRQS; i++) { for(i = 2; i < NR_IRQS; i++) {
irq_desc[i].chip = &crisv10_irq_type; set_irq_desc_and_handler(i, &crisv10_irq_type,
handle_simple_irq);
set_int_vector(i, interrupt[i]); set_int_vector(i, interrupt[i]);
} }
......
arch/cris/arch-v32/kernel/irq.c
View file @ 0f5c2ac5
...@@ -291,54 +291,33 @@ void crisv32_unmask_irq(int irq) ...@@ -291,54 +291,33 @@ void crisv32_unmask_irq(int irq)
} }
static unsigned int startup_crisv32_irq(unsigned int irq) static void enable_crisv32_irq(struct irq_data *data)
{ {
crisv32_unmask_irq(irq); crisv32_unmask_irq(data->irq);
return 0;
}
static void shutdown_crisv32_irq(unsigned int irq)
{
crisv32_mask_irq(irq);
} }
static void enable_crisv32_irq(unsigned int irq) static void disable_crisv32_irq(struct irq_data *data)
{ {
crisv32_unmask_irq(irq); crisv32_mask_irq(data->irq);
} }
static void disable_crisv32_irq(unsigned int irq) static int set_affinity_crisv32_irq(struct irq_data *data,
{ const struct cpumask *dest, bool force)
crisv32_mask_irq(irq);
}
static void ack_crisv32_irq(unsigned int irq)
{
}
static void end_crisv32_irq(unsigned int irq)
{
}
int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest)
{ {
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&irq_lock, flags); spin_lock_irqsave(&irq_lock, flags);
irq_allocations[irq - FIRST_IRQ].mask = *dest; irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
spin_unlock_irqrestore(&irq_lock, flags); spin_unlock_irqrestore(&irq_lock, flags);
return 0; return 0;
} }
static struct irq_chip crisv32_irq_type = { static struct irq_chip crisv32_irq_type = {
.name = "CRISv32", .name = "CRISv32",
.startup = startup_crisv32_irq, .irq_shutdown = disable_crisv32_irq,
.shutdown = shutdown_crisv32_irq, .irq_enable = enable_crisv32_irq,
.enable = enable_crisv32_irq, .irq_disable = disable_crisv32_irq,
.disable = disable_crisv32_irq, .irq_set_affinity = set_affinity_crisv32_irq,
.ack = ack_crisv32_irq,
.end = end_crisv32_irq,
.set_affinity = set_affinity_crisv32_irq
}; };
void void
...@@ -472,7 +451,8 @@ init_IRQ(void) ...@@ -472,7 +451,8 @@ init_IRQ(void)
/* Point all IRQ's to bad handlers. */ /* Point all IRQ's to bad handlers. */
for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
irq_desc[j].chip = &crisv32_irq_type; set_irq_chip_and_handler(j, &crisv32_irq_type,
handle_simple_irq);
set_exception_vector(i, interrupt[j]); set_exception_vector(i, interrupt[j]);
} }
......
arch/cris/kernel/irq.c
View file @ 0f5c2ac5
...@@ -62,7 +62,7 @@ int show_interrupts(struct seq_file *p, void *v) ...@@ -62,7 +62,7 @@ int show_interrupts(struct seq_file *p, void *v)
for_each_online_cpu(j) for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#endif #endif
seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
seq_printf(p, " %s", action->name); seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next) for (action=action->next; action; action = action->next)
...@@ -93,8 +93,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs) ...@@ -93,8 +93,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
printk("do_IRQ: stack overflow: %lX\n", sp); printk("do_IRQ: stack overflow: %lX\n", sp);
show_stack(NULL, (unsigned long *)sp); show_stack(NULL, (unsigned long *)sp);
} }
__do_IRQ(irq); generic_handle_irq(irq);
irq_exit(); irq_exit();
set_irq_regs(old_regs); set_irq_regs(old_regs);
} }
......
arch/frv/Kconfig
View file @ 0f5c2ac5
...@@ -5,6 +5,7 @@ config FRV ...@@ -5,6 +5,7 @@ config FRV
select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRACEHOOK
select HAVE_IRQ_WORK select HAVE_IRQ_WORK
select HAVE_PERF_EVENTS select HAVE_PERF_EVENTS
select HAVE_GENERIC_HARDIRQS
config ZONE_DMA config ZONE_DMA
bool bool
...@@ -29,14 +30,6 @@ config GENERIC_CALIBRATE_DELAY ...@@ -29,14 +30,6 @@ config GENERIC_CALIBRATE_DELAY
bool bool
default n default n
config GENERIC_HARDIRQS
bool
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
bool
default y
config TIME_LOW_RES config TIME_LOW_RES
bool bool
default y default y
......
arch/h8300/Kconfig
View file @ 0f5c2ac5
...@@ -2,6 +2,8 @@ config H8300 ...@@ -2,6 +2,8 @@ config H8300
bool bool
default y default y
select HAVE_IDE select HAVE_IDE
select HAVE_GENERIC_HARDIRQS
select GENERIC_HARDIRQS_NO_DEPRECATED
config SYMBOL_PREFIX config SYMBOL_PREFIX
string string
...@@ -47,10 +49,6 @@ config GENERIC_HWEIGHT ...@@ -47,10 +49,6 @@ config GENERIC_HWEIGHT
bool bool
default y default y
config GENERIC_HARDIRQS
bool
default y
config GENERIC_CALIBRATE_DELAY config GENERIC_CALIBRATE_DELAY
bool bool
default y default y
......
arch/h8300/kernel/irq.c
View file @ 0f5c2ac5
...@@ -38,34 +38,30 @@ static inline int is_ext_irq(unsigned int irq) ...@@ -38,34 +38,30 @@ static inline int is_ext_irq(unsigned int irq)
return (irq >= EXT_IRQ0 && irq <= (EXT_IRQ0 + EXT_IRQS)); return (irq >= EXT_IRQ0 && irq <= (EXT_IRQ0 + EXT_IRQS));
} }
static void h8300_enable_irq(unsigned int irq) static void h8300_enable_irq(struct irq_data *data)
{ {
if (is_ext_irq(irq)) if (is_ext_irq(data->irq))
IER_REGS |= 1 << (irq - EXT_IRQ0); IER_REGS |= 1 << (data->irq - EXT_IRQ0);
} }
static void h8300_disable_irq(unsigned int irq) static void h8300_disable_irq(struct irq_data *data)
{ {
if (is_ext_irq(irq)) if (is_ext_irq(data->irq))
IER_REGS &= ~(1 << (irq - EXT_IRQ0)); IER_REGS &= ~(1 << (data->irq - EXT_IRQ0));
} }
static void h8300_end_irq(unsigned int irq) static unsigned int h8300_startup_irq(struct irq_data *data)
{ {
} if (is_ext_irq(data->irq))
return h8300_enable_irq_pin(data->irq);
static unsigned int h8300_startup_irq(unsigned int irq)
{
if (is_ext_irq(irq))
return h8300_enable_irq_pin(irq);
else else
return 0; return 0;
} }
static void h8300_shutdown_irq(unsigned int irq) static void h8300_shutdown_irq(struct irq_data *data)
{ {
if (is_ext_irq(irq)) if (is_ext_irq(data->irq))
h8300_disable_irq_pin(irq); h8300_disable_irq_pin(data->irq);
} }
/* /*
...@@ -73,12 +69,10 @@ static void h8300_shutdown_irq(unsigned int irq) ...@@ -73,12 +69,10 @@ static void h8300_shutdown_irq(unsigned int irq)
*/ */
struct irq_chip h8300irq_chip = { struct irq_chip h8300irq_chip = {
.name = "H8300-INTC", .name = "H8300-INTC",
.startup = h8300_startup_irq, .irq_startup = h8300_startup_irq,
.shutdown = h8300_shutdown_irq, .irq_shutdown = h8300_shutdown_irq,
.enable = h8300_enable_irq, .irq_enable = h8300_enable_irq,
.disable = h8300_disable_irq, .irq_disable = h8300_disable_irq,
.ack = NULL,
.end = h8300_end_irq,
}; };
#if defined(CONFIG_RAMKERNEL) #if defined(CONFIG_RAMKERNEL)
...@@ -160,18 +154,14 @@ void __init init_IRQ(void) ...@@ -160,18 +154,14 @@ void __init init_IRQ(void)
setup_vector(); setup_vector();
for (c = 0; c < NR_IRQS; c++) { for (c = 0; c < NR_IRQS; c++)
irq_desc[c].status = IRQ_DISABLED; set_irq_chip_and_handler(c, &h8300irq_chip, handle_simple_irq);
irq_desc[c].action = NULL;
irq_desc[c].depth = 1;
irq_desc[c].chip = &h8300irq_chip;
}
} }
asmlinkage void do_IRQ(int irq) asmlinkage void do_IRQ(int irq)
{ {
irq_enter(); irq_enter();
__do_IRQ(irq); generic_handle_irq(irq);
irq_exit(); irq_exit();
} }
...@@ -192,7 +182,7 @@ int show_interrupts(struct seq_file *p, void *v) ...@@ -192,7 +182,7 @@ int show_interrupts(struct seq_file *p, void *v)
goto unlock; goto unlock;
seq_printf(p, "%3d: ",i); seq_printf(p, "%3d: ",i);
seq_printf(p, "%10u ", kstat_irqs(i)); seq_printf(p, "%10u ", kstat_irqs(i));
seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
seq_printf(p, "-%-8s", irq_desc[i].name); seq_printf(p, "-%-8s", irq_desc[i].name);
seq_printf(p, " %s", action->name); seq_printf(p, " %s", action->name);
......
arch/ia64/Kconfig
View file @ 0f5c2ac5
...@@ -22,6 +22,10 @@ config IA64 ...@@ -22,6 +22,10 @@ config IA64
select HAVE_KVM select HAVE_KVM
select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG select HAVE_DMA_API_DEBUG
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
select GENERIC_PENDING_IRQ if SMP
select IRQ_PER_CPU
default y default y
help help
The Itanium Processor Family is Intel's 64-bit successor to The Itanium Processor Family is Intel's 64-bit successor to
...@@ -678,28 +682,6 @@ source "arch/ia64/kvm/Kconfig" ...@@ -678,28 +682,6 @@ source "arch/ia64/kvm/Kconfig"
source "lib/Kconfig" source "lib/Kconfig"
#
# Use the generic interrupt handling code in kernel/irq/:
#
config GENERIC_HARDIRQS
def_bool y
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config GENERIC_IRQ_PROBE
bool
default y
config GENERIC_PENDING_IRQ
bool
depends on GENERIC_HARDIRQS && SMP
default y
config IRQ_PER_CPU
bool
default y
config IOMMU_HELPER config IOMMU_HELPER
def_bool (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC || SWIOTLB) def_bool (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC || SWIOTLB)
......
arch/m32r/Kconfig
View file @ 0f5c2ac5
...@@ -7,6 +7,9 @@ config M32R ...@@ -7,6 +7,9 @@ config M32R
select HAVE_KERNEL_GZIP select HAVE_KERNEL_GZIP
select HAVE_KERNEL_BZIP2 select HAVE_KERNEL_BZIP2
select HAVE_KERNEL_LZMA select HAVE_KERNEL_LZMA
select HAVE_GENERIC_HARDIRQS
select GENERIC_HARDIRQS_NO_DEPRECATED
select GENERIC_IRQ_PROBE
config SBUS config SBUS
bool bool
...@@ -19,14 +22,6 @@ config ZONE_DMA ...@@ -19,14 +22,6 @@ config ZONE_DMA
bool bool
default y default y
config GENERIC_HARDIRQS
bool
default y
config GENERIC_IRQ_PROBE
bool
default y
config NO_IOPORT config NO_IOPORT
def_bool y def_bool y
......
arch/m32r/kernel/irq.c
View file @ 0f5c2ac5
...@@ -40,8 +40,10 @@ int show_interrupts(struct seq_file *p, void *v) ...@@ -40,8 +40,10 @@ int show_interrupts(struct seq_file *p, void *v)
} }
if (i < NR_IRQS) { if (i < NR_IRQS) {
raw_spin_lock_irqsave(&irq_desc[i].lock, flags); struct irq_desc *desc = irq_to_desc(i);
action = irq_desc[i].action;
raw_spin_lock_irqsave(&desc->lock, flags);
action = desc->action;
if (!action) if (!action)
goto skip; goto skip;
seq_printf(p, "%3d: ",i); seq_printf(p, "%3d: ",i);
...@@ -51,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v) ...@@ -51,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v)
for_each_online_cpu(j) for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#endif #endif
seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %14s", desc->irq_data.chip->name);
seq_printf(p, " %s", action->name); seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next) for (action=action->next; action; action = action->next)
...@@ -59,7 +61,7 @@ int show_interrupts(struct seq_file *p, void *v) ...@@ -59,7 +61,7 @@ int show_interrupts(struct seq_file *p, void *v)
seq_putc(p, '\n'); seq_putc(p, '\n');
skip: skip:
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); raw_spin_unlock_irqrestore(&desc->lock, flags);
} }
return 0; return 0;
} }
......
arch/m32r/platforms/m32104ut/setup.c
View file @ 0f5c2ac5
...@@ -39,39 +39,30 @@ static void enable_m32104ut_irq(unsigned int irq) ...@@ -39,39 +39,30 @@ static void enable_m32104ut_irq(unsigned int irq)
outl(data, port); outl(data, port);
} }
static void mask_and_ack_m32104ut(unsigned int irq) static void mask_m32104ut_irq(struct irq_data *data)
{ {
disable_m32104ut_irq(irq); disable_m32104ut_irq(data->irq);
} }
static void end_m32104ut_irq(unsigned int irq) static void unmask_m32104ut_irq(struct irq_data *data)
{ {
enable_m32104ut_irq(irq); enable_m32104ut_irq(data->irq);
} }
static unsigned int startup_m32104ut_irq(unsigned int irq) static void shutdown_m32104ut_irq(struct irq_data *data)
{ {
enable_m32104ut_irq(irq); unsigned int irq = data->irq;
return (0); unsigned long port = irq2port(irq);
}
static void shutdown_m32104ut_irq(unsigned int irq)
{
unsigned long port;
port = irq2port(irq);
outl(M32R_ICUCR_ILEVEL7, port); outl(M32R_ICUCR_ILEVEL7, port);
} }
static struct irq_chip m32104ut_irq_type = static struct irq_chip m32104ut_irq_type =
{ {
.name = "M32104UT-IRQ", .name = "M32104UT-IRQ",
.startup = startup_m32104ut_irq, .irq_shutdown = shutdown_m32104ut_irq,
.shutdown = shutdown_m32104ut_irq, .irq_unmask = unmask_m32104ut_irq,
.enable = enable_m32104ut_irq, .irq_mask = mask_m32104ut_irq,
.disable = disable_m32104ut_irq,
.ack = mask_and_ack_m32104ut,
.end = end_m32104ut_irq
}; };
void __init init_IRQ(void) void __init init_IRQ(void)
...@@ -85,36 +76,29 @@ void __init init_IRQ(void) ...@@ -85,36 +76,29 @@ void __init init_IRQ(void)
#if defined(CONFIG_SMC91X) #if defined(CONFIG_SMC91X)
/* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT0].action = 0; /* "H" level sense */
irq_desc[M32R_IRQ_INT0].depth = 1; cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11;
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
disable_m32104ut_irq(M32R_IRQ_INT0); disable_m32104ut_irq(M32R_IRQ_INT0);
#endif /* CONFIG_SMC91X */ #endif /* CONFIG_SMC91X */
/* MFT2 : system timer */ /* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_m32104ut_irq(M32R_IRQ_MFT2); disable_m32104ut_irq(M32R_IRQ_MFT2);
#ifdef CONFIG_SERIAL_M32R_SIO #ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */ /* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
disable_m32104ut_irq(M32R_IRQ_SIO0_R); disable_m32104ut_irq(M32R_IRQ_SIO0_R);
/* SIO0_S : uart send data */ /* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
disable_m32104ut_irq(M32R_IRQ_SIO0_S); disable_m32104ut_irq(M32R_IRQ_SIO0_S);
#endif /* CONFIG_SERIAL_M32R_SIO */ #endif /* CONFIG_SERIAL_M32R_SIO */
......
arch/m32r/platforms/m32700ut/setup.c
View file @ 0f5c2ac5
This diff is collapsed.
arch/m32r/platforms/mappi/setup.c
View file @ 0f5c2ac5
...@@ -38,40 +38,30 @@ static void enable_mappi_irq(unsigned int irq) ...@@ -38,40 +38,30 @@ static void enable_mappi_irq(unsigned int irq)
outl(data, port); outl(data, port);
} }
static void mask_and_ack_mappi(unsigned int irq) static void mask_mappi(struct irq_data *data)
{ {
disable_mappi_irq(irq); disable_mappi_irq(data->irq);
} }
static void end_mappi_irq(unsigned int irq) static void unmask_mappi(struct irq_data *data)
{ {
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) enable_mappi_irq(data->irq);
enable_mappi_irq(irq);
} }
static unsigned int startup_mappi_irq(unsigned int irq) static void shutdown_mappi(struct irq_data *data)
{
enable_mappi_irq(irq);
return (0);
}
static void shutdown_mappi_irq(unsigned int irq)
{ {
unsigned long port; unsigned long port;
port = irq2port(irq); port = irq2port(data->irq);
outl(M32R_ICUCR_ILEVEL7, port); outl(M32R_ICUCR_ILEVEL7, port);
} }
static struct irq_chip mappi_irq_type = static struct irq_chip mappi_irq_type =
{ {
.name = "MAPPI-IRQ", .name = "MAPPI-IRQ",
.startup = startup_mappi_irq, .irq_shutdown = shutdown_mappi,
.shutdown = shutdown_mappi_irq, .irq_mask = mask_mappi,
.enable = enable_mappi_irq, .irq_unmask = unmask_mappi,
.disable = disable_mappi_irq,
.ack = mask_and_ack_mappi,
.end = end_mappi_irq
}; };
void __init init_IRQ(void) void __init init_IRQ(void)
...@@ -85,70 +75,54 @@ void __init init_IRQ(void) ...@@ -85,70 +75,54 @@ void __init init_IRQ(void)
#ifdef CONFIG_NE2000 #ifdef CONFIG_NE2000
/* INT0 : LAN controller (RTL8019AS) */ /* INT0 : LAN controller (RTL8019AS) */
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT0].action = NULL;
irq_desc[M32R_IRQ_INT0].depth = 1;
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
disable_mappi_irq(M32R_IRQ_INT0); disable_mappi_irq(M32R_IRQ_INT0);
#endif /* CONFIG_M32R_NE2000 */ #endif /* CONFIG_M32R_NE2000 */
/* MFT2 : system timer */ /* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_MFT2].action = NULL;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_mappi_irq(M32R_IRQ_MFT2); disable_mappi_irq(M32R_IRQ_MFT2);
#ifdef CONFIG_SERIAL_M32R_SIO #ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */ /* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_R].action = NULL;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0; icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO0_R); disable_mappi_irq(M32R_IRQ_SIO0_R);
/* SIO0_S : uart send data */ /* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_S].action = NULL;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0; icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO0_S); disable_mappi_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */ /* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_R].action = NULL;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0; icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO1_R); disable_mappi_irq(M32R_IRQ_SIO1_R);
/* SIO1_S : uart send data */ /* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_S].action = NULL;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0; icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO1_S); disable_mappi_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_SERIAL_M32R_SIO */ #endif /* CONFIG_SERIAL_M32R_SIO */
#if defined(CONFIG_M32R_PCC) #if defined(CONFIG_M32R_PCC)
/* INT1 : pccard0 interrupt */ /* INT1 : pccard0 interrupt */
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT1].action = NULL;
irq_desc[M32R_IRQ_INT1].depth = 1;
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
disable_mappi_irq(M32R_IRQ_INT1); disable_mappi_irq(M32R_IRQ_INT1);
/* INT2 : pccard1 interrupt */ /* INT2 : pccard1 interrupt */
irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT2].action = NULL;
irq_desc[M32R_IRQ_INT2].depth = 1;
icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
disable_mappi_irq(M32R_IRQ_INT2); disable_mappi_irq(M32R_IRQ_INT2);
#endif /* CONFIG_M32RPCC */ #endif /* CONFIG_M32RPCC */
......
arch/m32r/platforms/mappi2/setup.c
View file @ 0f5c2ac5
...@@ -46,126 +46,97 @@ static void enable_mappi2_irq(unsigned int irq) ...@@ -46,126 +46,97 @@ static void enable_mappi2_irq(unsigned int irq)
outl(data, port); outl(data, port);
} }
static void mask_and_ack_mappi2(unsigned int irq) static void mask_mappi2(struct irq_data *data)
{ {
disable_mappi2_irq(irq); disable_mappi2_irq(data->irq);
} }
static void end_mappi2_irq(unsigned int irq) static void unmask_mappi2(struct irq_data *data)
{ {
enable_mappi2_irq(irq); enable_mappi2_irq(data->irq);
} }
static unsigned int startup_mappi2_irq(unsigned int irq) static void shutdown_mappi2(struct irq_data *data)
{
enable_mappi2_irq(irq);
return (0);
}
static void shutdown_mappi2_irq(unsigned int irq)
{ {
unsigned long port; unsigned long port;
port = irq2port(irq); port = irq2port(data->irq);
outl(M32R_ICUCR_ILEVEL7, port); outl(M32R_ICUCR_ILEVEL7, port);
} }
static struct irq_chip mappi2_irq_type = static struct irq_chip mappi2_irq_type =
{ {
.name = "MAPPI2-IRQ", .name = "MAPPI2-IRQ",
.startup = startup_mappi2_irq, .irq_shutdown = shutdown_mappi2,
.shutdown = shutdown_mappi2_irq, .irq_mask = mask_mappi2,
.enable = enable_mappi2_irq, .irq_unmask = unmask_mappi2,
.disable = disable_mappi2_irq,
.ack = mask_and_ack_mappi2,
.end = end_mappi2_irq
}; };
void __init init_IRQ(void) void __init init_IRQ(void)
{ {
#if defined(CONFIG_SMC91X) #if defined(CONFIG_SMC91X)
/* INT0 : LAN controller (SMC91111) */ /* INT0 : LAN controller (SMC91111) */
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT0].action = 0;
irq_desc[M32R_IRQ_INT0].depth = 1;
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_mappi2_irq(M32R_IRQ_INT0); disable_mappi2_irq(M32R_IRQ_INT0);
#endif /* CONFIG_SMC91X */ #endif /* CONFIG_SMC91X */
/* MFT2 : system timer */ /* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_mappi2_irq(M32R_IRQ_MFT2); disable_mappi2_irq(M32R_IRQ_MFT2);
#ifdef CONFIG_SERIAL_M32R_SIO #ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */ /* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0; icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO0_R); disable_mappi2_irq(M32R_IRQ_SIO0_R);
/* SIO0_S : uart send data */ /* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0; icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO0_S); disable_mappi2_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */ /* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0; icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO1_R); disable_mappi2_irq(M32R_IRQ_SIO1_R);
/* SIO1_S : uart send data */ /* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0; icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_mappi2_irq(M32R_IRQ_SIO1_S); disable_mappi2_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ #endif /* CONFIG_M32R_USE_DBG_CONSOLE */
#if defined(CONFIG_USB) #if defined(CONFIG_USB)
/* INT1 : USB Host controller interrupt */ /* INT1 : USB Host controller interrupt */
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT1].action = 0;
irq_desc[M32R_IRQ_INT1].depth = 1;
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
disable_mappi2_irq(M32R_IRQ_INT1); disable_mappi2_irq(M32R_IRQ_INT1);
#endif /* CONFIG_USB */ #endif /* CONFIG_USB */
/* ICUCR40: CFC IREQ */ /* ICUCR40: CFC IREQ */
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_CFIREQ].action = 0;
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
disable_mappi2_irq(PLD_IRQ_CFIREQ); disable_mappi2_irq(PLD_IRQ_CFIREQ);
#if defined(CONFIG_M32R_CFC) #if defined(CONFIG_M32R_CFC)
/* ICUCR41: CFC Insert */ /* ICUCR41: CFC Insert */
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
disable_mappi2_irq(PLD_IRQ_CFC_INSERT); disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
/* ICUCR42: CFC Eject */ /* ICUCR42: CFC Eject */
irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_mappi2_irq(PLD_IRQ_CFC_EJECT); disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
#endif /* CONFIG_MAPPI2_CFC */ #endif /* CONFIG_MAPPI2_CFC */
......
arch/m32r/platforms/mappi3/setup.c
View file @ 0f5c2ac5
...@@ -46,128 +46,98 @@ static void enable_mappi3_irq(unsigned int irq) ...@@ -46,128 +46,98 @@ static void enable_mappi3_irq(unsigned int irq)
outl(data, port); outl(data, port);
} }
static void mask_and_ack_mappi3(unsigned int irq) static void mask_mappi3(struct irq_data *data)
{ {
disable_mappi3_irq(irq); disable_mappi3_irq(data->irq);
} }
static void end_mappi3_irq(unsigned int irq) static void unmask_mappi3(struct irq_data *data)
{ {
enable_mappi3_irq(irq); enable_mappi3_irq(data->irq);
} }
static unsigned int startup_mappi3_irq(unsigned int irq) static void shutdown_mappi3(struct irq_data *data)
{
enable_mappi3_irq(irq);
return (0);
}
static void shutdown_mappi3_irq(unsigned int irq)
{ {
unsigned long port; unsigned long port;
port = irq2port(irq); port = irq2port(data->irq);
outl(M32R_ICUCR_ILEVEL7, port); outl(M32R_ICUCR_ILEVEL7, port);
} }
static struct irq_chip mappi3_irq_type = static struct irq_chip mappi3_irq_type = {
{ .name = "MAPPI3-IRQ",
.name = "MAPPI3-IRQ", .irq_shutdown = shutdown_mappi3,
.startup = startup_mappi3_irq, .irq_mask = mask_mappi3,
.shutdown = shutdown_mappi3_irq, .irq_unmask = unmask_mappi3,
.enable = enable_mappi3_irq,
.disable = disable_mappi3_irq,
.ack = mask_and_ack_mappi3,
.end = end_mappi3_irq
}; };
void __init init_IRQ(void) void __init init_IRQ(void)
{ {
#if defined(CONFIG_SMC91X) #if defined(CONFIG_SMC91X)
/* INT0 : LAN controller (SMC91111) */ /* INT0 : LAN controller (SMC91111) */
irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT0].action = 0;
irq_desc[M32R_IRQ_INT0].depth = 1;
icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_mappi3_irq(M32R_IRQ_INT0); disable_mappi3_irq(M32R_IRQ_INT0);
#endif /* CONFIG_SMC91X */ #endif /* CONFIG_SMC91X */
/* MFT2 : system timer */ /* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_mappi3_irq(M32R_IRQ_MFT2); disable_mappi3_irq(M32R_IRQ_MFT2);
#ifdef CONFIG_SERIAL_M32R_SIO #ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */ /* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0; icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO0_R); disable_mappi3_irq(M32R_IRQ_SIO0_R);
/* SIO0_S : uart send data */ /* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0; icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO0_S); disable_mappi3_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */ /* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0; icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO1_R); disable_mappi3_irq(M32R_IRQ_SIO1_R);
/* SIO1_S : uart send data */ /* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0; icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_mappi3_irq(M32R_IRQ_SIO1_S); disable_mappi3_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ #endif /* CONFIG_M32R_USE_DBG_CONSOLE */
#if defined(CONFIG_USB) #if defined(CONFIG_USB)
/* INT1 : USB Host controller interrupt */ /* INT1 : USB Host controller interrupt */
irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT1].action = 0;
irq_desc[M32R_IRQ_INT1].depth = 1;
icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
disable_mappi3_irq(M32R_IRQ_INT1); disable_mappi3_irq(M32R_IRQ_INT1);
#endif /* CONFIG_USB */ #endif /* CONFIG_USB */
/* CFC IREQ */ /* CFC IREQ */
irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_CFIREQ].action = 0;
irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
disable_mappi3_irq(PLD_IRQ_CFIREQ); disable_mappi3_irq(PLD_IRQ_CFIREQ);
#if defined(CONFIG_M32R_CFC) #if defined(CONFIG_M32R_CFC)
/* ICUCR41: CFC Insert & eject */ /* ICUCR41: CFC Insert & eject */
irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
disable_mappi3_irq(PLD_IRQ_CFC_INSERT); disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
#endif /* CONFIG_M32R_CFC */ #endif /* CONFIG_M32R_CFC */
/* IDE IREQ */ /* IDE IREQ */
irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_IDEIREQ].action = 0;
irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_mappi3_irq(PLD_IRQ_IDEIREQ); disable_mappi3_irq(PLD_IRQ_IDEIREQ);
......
arch/m32r/platforms/oaks32r/setup.c
View file @ 0f5c2ac5
...@@ -37,39 +37,30 @@ static void enable_oaks32r_irq(unsigned int irq) ...@@ -37,39 +37,30 @@ static void enable_oaks32r_irq(unsigned int irq)
outl(data, port); outl(data, port);
} }
static void mask_and_ack_mappi(unsigned int irq) static void mask_oaks32r(struct irq_data *data)
{ {
disable_oaks32r_irq(irq); disable_oaks32r_irq(data->irq);
} }
static void end_oaks32r_irq(unsigned int irq) static void unmask_oaks32r(struct irq_data *data)
{ {
enable_oaks32r_irq(irq); enable_oaks32r_irq(data->irq);
} }
static unsigned int startup_oaks32r_irq(unsigned int irq) static void shutdown_oaks32r(struct irq_data *data)
{
enable_oaks32r_irq(irq);
return (0);
}
static void shutdown_oaks32r_irq(unsigned int irq)
{ {
unsigned long port; unsigned long port;
port = irq2port(irq); port = irq2port(data->irq);
outl(M32R_ICUCR_ILEVEL7, port); outl(M32R_ICUCR_ILEVEL7, port);
} }
static struct irq_chip oaks32r_irq_type = static struct irq_chip oaks32r_irq_type =
{ {
.name = "OAKS32R-IRQ", .name = "OAKS32R-IRQ",
.startup = startup_oaks32r_irq, .irq_shutdown = shutdown_oaks32r,
.shutdown = shutdown_oaks32r_irq, .irq_mask = mask_oaks32r,
.enable = enable_oaks32r_irq, .irq_unmask = unmask_oaks32r,
.disable = disable_oaks32r_irq,
.ack = mask_and_ack_mappi,
.end = end_oaks32r_irq
}; };
void __init init_IRQ(void) void __init init_IRQ(void)
...@@ -83,52 +74,40 @@ void __init init_IRQ(void) ...@@ -83,52 +74,40 @@ void __init init_IRQ(void)
#ifdef CONFIG_NE2000 #ifdef CONFIG_NE2000
/* INT3 : LAN controller (RTL8019AS) */ /* INT3 : LAN controller (RTL8019AS) */
irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_INT3].action = 0;
irq_desc[M32R_IRQ_INT3].depth = 1;
icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
disable_oaks32r_irq(M32R_IRQ_INT3); disable_oaks32r_irq(M32R_IRQ_INT3);
#endif /* CONFIG_M32R_NE2000 */ #endif /* CONFIG_M32R_NE2000 */
/* MFT2 : system timer */ /* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_oaks32r_irq(M32R_IRQ_MFT2); disable_oaks32r_irq(M32R_IRQ_MFT2);
#ifdef CONFIG_SERIAL_M32R_SIO #ifdef CONFIG_SERIAL_M32R_SIO
/* SIO0_R : uart receive data */ /* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0; icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_oaks32r_irq(M32R_IRQ_SIO0_R); disable_oaks32r_irq(M32R_IRQ_SIO0_R);
/* SIO0_S : uart send data */ /* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0; icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_oaks32r_irq(M32R_IRQ_SIO0_S); disable_oaks32r_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */ /* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0; icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_oaks32r_irq(M32R_IRQ_SIO1_R); disable_oaks32r_irq(M32R_IRQ_SIO1_R);
/* SIO1_S : uart send data */ /* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0; icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_oaks32r_irq(M32R_IRQ_SIO1_S); disable_oaks32r_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_SERIAL_M32R_SIO */ #endif /* CONFIG_SERIAL_M32R_SIO */
......
arch/m32r/platforms/opsput/setup.c
View file @ 0f5c2ac5
This diff is collapsed.
arch/m32r/platforms/usrv/setup.c
View file @ 0f5c2ac5
...@@ -37,39 +37,30 @@ static void enable_mappi_irq(unsigned int irq) ...@@ -37,39 +37,30 @@ static void enable_mappi_irq(unsigned int irq)
outl(data, port); outl(data, port);
} }
static void mask_and_ack_mappi(unsigned int irq) static void mask_mappi(struct irq_data *data)
{ {
disable_mappi_irq(irq); disable_mappi_irq(data->irq);
} }
static void end_mappi_irq(unsigned int irq) static void unmask_mappi(struct irq_data *data)
{ {
enable_mappi_irq(irq); enable_mappi_irq(data->irq);
} }
static unsigned int startup_mappi_irq(unsigned int irq) static void shutdown_mappi(struct irq_data *data)
{
enable_mappi_irq(irq);
return 0;
}
static void shutdown_mappi_irq(unsigned int irq)
{ {
unsigned long port; unsigned long port;
port = irq2port(irq); port = irq2port(data->irq);
outl(M32R_ICUCR_ILEVEL7, port); outl(M32R_ICUCR_ILEVEL7, port);
} }
static struct irq_chip mappi_irq_type = static struct irq_chip mappi_irq_type =
{ {
.name = "M32700-IRQ", .name = "M32700-IRQ",
.startup = startup_mappi_irq, .irq_shutdown = shutdown_mappi,
.shutdown = shutdown_mappi_irq, .irq_mask = mask_mappi,
.enable = enable_mappi_irq, .irq_unmask = unmask_mappi,
.disable = disable_mappi_irq,
.ack = mask_and_ack_mappi,
.end = end_mappi_irq
}; };
/* /*
...@@ -107,42 +98,33 @@ static void enable_m32700ut_pld_irq(unsigned int irq) ...@@ -107,42 +98,33 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
outw(data, port); outw(data, port);
} }
static void mask_and_ack_m32700ut_pld(unsigned int irq) static void mask_m32700ut_pld(struct irq_data *data)
{ {
disable_m32700ut_pld_irq(irq); disable_m32700ut_pld_irq(data->irq);
} }
static void end_m32700ut_pld_irq(unsigned int irq) static void unmask_m32700ut_pld(struct irq_data *data)
{ {
enable_m32700ut_pld_irq(irq); enable_m32700ut_pld_irq(data->irq);
end_mappi_irq(M32R_IRQ_INT1); enable_mappi_irq(M32R_IRQ_INT1);
}
static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
{
enable_m32700ut_pld_irq(irq);
return 0;
} }
static void shutdown_m32700ut_pld_irq(unsigned int irq) static void shutdown_m32700ut_pld(struct irq_data *data)
{ {
unsigned long port; unsigned long port;
unsigned int pldirq; unsigned int pldirq;
pldirq = irq2pldirq(irq); pldirq = irq2pldirq(data->irq);
port = pldirq2port(pldirq); port = pldirq2port(pldirq);
outw(PLD_ICUCR_ILEVEL7, port); outw(PLD_ICUCR_ILEVEL7, port);
} }
static struct irq_chip m32700ut_pld_irq_type = static struct irq_chip m32700ut_pld_irq_type =
{ {
.name = "USRV-PLD-IRQ", .name = "USRV-PLD-IRQ",
.startup = startup_m32700ut_pld_irq, .irq_shutdown = shutdown_m32700ut_pld,
.shutdown = shutdown_m32700ut_pld_irq, .irq_mask = mask_m32700ut_pld,
.enable = enable_m32700ut_pld_irq, .irq_unmask = unmask_m32700ut_pld,
.disable = disable_m32700ut_pld_irq,
.ack = mask_and_ack_m32700ut_pld,
.end = end_m32700ut_pld_irq
}; };
void __init init_IRQ(void) void __init init_IRQ(void)
...@@ -156,53 +138,42 @@ void __init init_IRQ(void) ...@@ -156,53 +138,42 @@ void __init init_IRQ(void)
once++; once++;
/* MFT2 : system timer */ /* MFT2 : system timer */
irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_MFT2].action = 0;
irq_desc[M32R_IRQ_MFT2].depth = 1;
icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
disable_mappi_irq(M32R_IRQ_MFT2); disable_mappi_irq(M32R_IRQ_MFT2);
#if defined(CONFIG_SERIAL_M32R_SIO) #if defined(CONFIG_SERIAL_M32R_SIO)
/* SIO0_R : uart receive data */ /* SIO0_R : uart receive data */
irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_R].action = 0;
irq_desc[M32R_IRQ_SIO0_R].depth = 1;
icu_data[M32R_IRQ_SIO0_R].icucr = 0; icu_data[M32R_IRQ_SIO0_R].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO0_R); disable_mappi_irq(M32R_IRQ_SIO0_R);
/* SIO0_S : uart send data */ /* SIO0_S : uart send data */
irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO0_S].action = 0;
irq_desc[M32R_IRQ_SIO0_S].depth = 1;
icu_data[M32R_IRQ_SIO0_S].icucr = 0; icu_data[M32R_IRQ_SIO0_S].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO0_S); disable_mappi_irq(M32R_IRQ_SIO0_S);
/* SIO1_R : uart receive data */ /* SIO1_R : uart receive data */
irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_R].action = 0;
irq_desc[M32R_IRQ_SIO1_R].depth = 1;
icu_data[M32R_IRQ_SIO1_R].icucr = 0; icu_data[M32R_IRQ_SIO1_R].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO1_R); disable_mappi_irq(M32R_IRQ_SIO1_R);
/* SIO1_S : uart send data */ /* SIO1_S : uart send data */
irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; handle_level_irq);
irq_desc[M32R_IRQ_SIO1_S].action = 0;
irq_desc[M32R_IRQ_SIO1_S].depth = 1;
icu_data[M32R_IRQ_SIO1_S].icucr = 0; icu_data[M32R_IRQ_SIO1_S].icucr = 0;
disable_mappi_irq(M32R_IRQ_SIO1_S); disable_mappi_irq(M32R_IRQ_SIO1_S);
#endif /* CONFIG_SERIAL_M32R_SIO */ #endif /* CONFIG_SERIAL_M32R_SIO */
/* INT#67-#71: CFC#0 IREQ on PLD */ /* INT#67-#71: CFC#0 IREQ on PLD */
for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_CF0 + i,
irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; &m32700ut_pld_irq_type,
irq_desc[PLD_IRQ_CF0 + i].action = 0; handle_level_irq);
irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
= PLD_ICUCR_ISMOD01; /* 'L' level sense */ = PLD_ICUCR_ISMOD01; /* 'L' level sense */
disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
...@@ -210,19 +181,15 @@ void __init init_IRQ(void) ...@@ -210,19 +181,15 @@ void __init init_IRQ(void)
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/* INT#76: 16552D#0 IREQ on PLD */ /* INT#76: 16552D#0 IREQ on PLD */
irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_UART0].action = 0;
irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
= PLD_ICUCR_ISMOD03; /* 'H' level sense */ = PLD_ICUCR_ISMOD03; /* 'H' level sense */
disable_m32700ut_pld_irq(PLD_IRQ_UART0); disable_m32700ut_pld_irq(PLD_IRQ_UART0);
/* INT#77: 16552D#1 IREQ on PLD */ /* INT#77: 16552D#1 IREQ on PLD */
irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_UART1].action = 0;
irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
= PLD_ICUCR_ISMOD03; /* 'H' level sense */ = PLD_ICUCR_ISMOD03; /* 'H' level sense */
disable_m32700ut_pld_irq(PLD_IRQ_UART1); disable_m32700ut_pld_irq(PLD_IRQ_UART1);
...@@ -230,10 +197,8 @@ void __init init_IRQ(void) ...@@ -230,10 +197,8 @@ void __init init_IRQ(void)
#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
/* INT#80: AK4524 IREQ on PLD */ /* INT#80: AK4524 IREQ on PLD */
irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; handle_level_irq);
irq_desc[PLD_IRQ_SNDINT].action = 0;
irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
= PLD_ICUCR_ISMOD01; /* 'L' level sense */ = PLD_ICUCR_ISMOD01; /* 'L' level sense */
disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
......
arch/m68knommu/Kconfig
View file @ 0f5c2ac5
...@@ -2,6 +2,7 @@ config M68K ...@@ -2,6 +2,7 @@ config M68K
bool bool
default y default y
select HAVE_IDE select HAVE_IDE
select HAVE_GENERIC_HARDIRQS
config MMU config MMU
bool bool
...@@ -48,14 +49,6 @@ config GENERIC_HWEIGHT ...@@ -48,14 +49,6 @@ config GENERIC_HWEIGHT
bool bool
default y default y
config GENERIC_HARDIRQS
bool
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
bool
default y
config GENERIC_CALIBRATE_DELAY config GENERIC_CALIBRATE_DELAY
bool bool
default y default y
......
arch/microblaze/Kconfig
View file @ 0f5c2ac5
...@@ -15,6 +15,8 @@ config MICROBLAZE ...@@ -15,6 +15,8 @@ config MICROBLAZE
select TRACING_SUPPORT select TRACING_SUPPORT
select OF select OF
select OF_EARLY_FLATTREE select OF_EARLY_FLATTREE
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
config SWAP config SWAP
def_bool n def_bool n
...@@ -37,12 +39,6 @@ config GENERIC_FIND_NEXT_BIT ...@@ -37,12 +39,6 @@ config GENERIC_FIND_NEXT_BIT
config GENERIC_HWEIGHT config GENERIC_HWEIGHT
def_bool y def_bool y
config GENERIC_HARDIRQS
def_bool y
config GENERIC_IRQ_PROBE
def_bool y
config GENERIC_CALIBRATE_DELAY config GENERIC_CALIBRATE_DELAY
def_bool y def_bool y
...@@ -52,9 +48,6 @@ config GENERIC_TIME_VSYSCALL ...@@ -52,9 +48,6 @@ config GENERIC_TIME_VSYSCALL
config GENERIC_CLOCKEVENTS config GENERIC_CLOCKEVENTS
def_bool y def_bool y
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config GENERIC_GPIO config GENERIC_GPIO
def_bool y def_bool y
......
arch/mips/Kconfig
View file @ 0f5c2ac5
...@@ -793,9 +793,6 @@ config SCHED_OMIT_FRAME_POINTER ...@@ -793,9 +793,6 @@ config SCHED_OMIT_FRAME_POINTER
bool bool
default y default y
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
# #
# Select some configuration options automatically based on user selections. # Select some configuration options automatically based on user selections.
# #
......
arch/mn10300/Kconfig
View file @ 0f5c2ac5
config MN10300 config MN10300
def_bool y def_bool y
select HAVE_OPROFILE select HAVE_OPROFILE
select GENERIC_HARDIRQS
config AM33_2 config AM33_2
def_bool n def_bool n
...@@ -34,9 +35,6 @@ config RWSEM_GENERIC_SPINLOCK ...@@ -34,9 +35,6 @@ config RWSEM_GENERIC_SPINLOCK
config RWSEM_XCHGADD_ALGORITHM config RWSEM_XCHGADD_ALGORITHM
bool bool
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config GENERIC_CALIBRATE_DELAY config GENERIC_CALIBRATE_DELAY
def_bool y def_bool y
...@@ -79,10 +77,6 @@ config QUICKLIST ...@@ -79,10 +77,6 @@ config QUICKLIST
config ARCH_HAS_ILOG2_U32 config ARCH_HAS_ILOG2_U32
def_bool y def_bool y
# Use the generic interrupt handling code in kernel/irq/
config GENERIC_HARDIRQS
def_bool y
config HOTPLUG_CPU config HOTPLUG_CPU
def_bool n def_bool n
......
arch/parisc/Kconfig
View file @ 0f5c2ac5
...@@ -12,7 +12,10 @@ config PARISC ...@@ -12,7 +12,10 @@ config PARISC
select HAVE_IRQ_WORK select HAVE_IRQ_WORK
select HAVE_PERF_EVENTS select HAVE_PERF_EVENTS
select GENERIC_ATOMIC64 if !64BIT select GENERIC_ATOMIC64 if !64BIT
select GENERIC_HARDIRQS_NO__DO_IRQ select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
select IRQ_PER_CPU
help help
The PA-RISC microprocessor is designed by Hewlett-Packard and used The PA-RISC microprocessor is designed by Hewlett-Packard and used
in many of their workstations & servers (HP9000 700 and 800 series, in many of their workstations & servers (HP9000 700 and 800 series,
...@@ -66,22 +69,9 @@ config TIME_LOW_RES ...@@ -66,22 +69,9 @@ config TIME_LOW_RES
depends on SMP depends on SMP
default y default y
config GENERIC_HARDIRQS
def_bool y
config GENERIC_IRQ_PROBE
def_bool y
config HAVE_LATENCYTOP_SUPPORT config HAVE_LATENCYTOP_SUPPORT
def_bool y def_bool y
config IRQ_PER_CPU
bool
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
# unless you want to implement ACPI on PA-RISC ... ;-) # unless you want to implement ACPI on PA-RISC ... ;-)
config PM config PM
bool bool
......
arch/powerpc/Kconfig
View file @ 0f5c2ac5
...@@ -36,24 +36,12 @@ config GENERIC_TIME_VSYSCALL ...@@ -36,24 +36,12 @@ config GENERIC_TIME_VSYSCALL
config GENERIC_CLOCKEVENTS config GENERIC_CLOCKEVENTS
def_bool y def_bool y
config GENERIC_HARDIRQS
bool
default y
config GENERIC_HARDIRQS_NO__DO_IRQ
bool
default y
config HAVE_SETUP_PER_CPU_AREA config HAVE_SETUP_PER_CPU_AREA
def_bool PPC64 def_bool PPC64
config NEED_PER_CPU_EMBED_FIRST_CHUNK config NEED_PER_CPU_EMBED_FIRST_CHUNK
def_bool PPC64 def_bool PPC64
config IRQ_PER_CPU
bool
default y
config NR_IRQS config NR_IRQS
int "Number of virtual interrupt numbers" int "Number of virtual interrupt numbers"
range 32 32768 range 32 32768
...@@ -143,6 +131,9 @@ config PPC ...@@ -143,6 +131,9 @@ config PPC
select HAVE_PERF_EVENTS select HAVE_PERF_EVENTS
select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64 select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
select HAVE_GENERIC_HARDIRQS
select HAVE_SPARSE_IRQ
select IRQ_PER_CPU
config EARLY_PRINTK config EARLY_PRINTK
bool bool
...@@ -392,19 +383,6 @@ config IRQ_ALL_CPUS ...@@ -392,19 +383,6 @@ config IRQ_ALL_CPUS
CPU. Generally saying Y is safe, although some problems have been CPU. Generally saying Y is safe, although some problems have been
reported with SMP Power Macintoshes with this option enabled. reported with SMP Power Macintoshes with this option enabled.
config SPARSE_IRQ
bool "Support sparse irq numbering"
default n
help
This enables support for sparse irqs. This is useful for distro
kernels that want to define a high CONFIG_NR_CPUS value but still
want to have low kernel memory footprint on smaller machines.
( Sparse IRQs can also be beneficial on NUMA boxes, as they spread
out the irq_desc[] array in a more NUMA-friendly way. )
If you don't know what to do here, say N.
config NUMA config NUMA
bool "NUMA support" bool "NUMA support"
depends on PPC64 depends on PPC64
......
arch/score/Kconfig
View file @ 0f5c2ac5
menu "Machine selection" menu "Machine selection"
config SCORE
def_bool y
select HAVE_GENERIC_HARDIRQS
choice choice
prompt "System type" prompt "System type"
default MACH_SPCT6600 default MACH_SPCT6600
...@@ -53,9 +57,6 @@ config GENERIC_CLOCKEVENTS ...@@ -53,9 +57,6 @@ config GENERIC_CLOCKEVENTS
config SCHED_NO_NO_OMIT_FRAME_POINTER config SCHED_NO_NO_OMIT_FRAME_POINTER
def_bool y def_bool y
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config GENERIC_SYSCALL_TABLE config GENERIC_SYSCALL_TABLE
def_bool y def_bool y
...@@ -68,9 +69,6 @@ menu "Kernel type" ...@@ -68,9 +69,6 @@ menu "Kernel type"
config 32BIT config 32BIT
def_bool y def_bool y
config GENERIC_HARDIRQS
def_bool y
config ARCH_FLATMEM_ENABLE config ARCH_FLATMEM_ENABLE
def_bool y def_bool y
......
arch/sparc/Kconfig
View file @ 0f5c2ac5
...@@ -50,6 +50,7 @@ config SPARC64 ...@@ -50,6 +50,7 @@ config SPARC64
select RTC_DRV_STARFIRE select RTC_DRV_STARFIRE
select HAVE_PERF_EVENTS select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC select PERF_USE_VMALLOC
select HAVE_GENERIC_HARDIRQS
config ARCH_DEFCONFIG config ARCH_DEFCONFIG
string string
...@@ -107,10 +108,6 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK ...@@ -107,10 +108,6 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
config NEED_PER_CPU_PAGE_FIRST_CHUNK config NEED_PER_CPU_PAGE_FIRST_CHUNK
def_bool y if SPARC64 def_bool y if SPARC64
config GENERIC_HARDIRQS_NO__DO_IRQ
bool
def_bool y if SPARC64
config MMU config MMU
bool bool
default y default y
...@@ -276,10 +273,6 @@ config HOTPLUG_CPU ...@@ -276,10 +273,6 @@ config HOTPLUG_CPU
can be controlled through /sys/devices/system/cpu/cpu#. can be controlled through /sys/devices/system/cpu/cpu#.
Say N if you want to disable CPU hotplug. Say N if you want to disable CPU hotplug.
config GENERIC_HARDIRQS
bool
default y if SPARC64
source "kernel/time/Kconfig" source "kernel/time/Kconfig"
if SPARC64 if SPARC64
......
arch/tile/Kconfig
View file @ 0f5c2ac5
# For a description of the syntax of this configuration file, # For a description of the syntax of this configuration file,
# see Documentation/kbuild/config-language.txt. # see Documentation/kbuild/config-language.txt.
config MMU config TILE
def_bool y
config GENERIC_CSUM
def_bool y
config GENERIC_HARDIRQS
def_bool y def_bool y
select HAVE_KVM if !TILEGX
select GENERIC_FIND_FIRST_BIT
select GENERIC_FIND_NEXT_BIT
select USE_GENERIC_SMP_HELPERS
select CC_OPTIMIZE_FOR_SIZE
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
select GENERIC_PENDING_IRQ if SMP
config GENERIC_HARDIRQS_NO__DO_IRQ # FIXME: investigate whether we need/want these options.
def_bool y # select HAVE_IOREMAP_PROT
# select HAVE_OPTPROBES
# select HAVE_REGS_AND_STACK_ACCESS_API
# select HAVE_HW_BREAKPOINT
# select PERF_EVENTS
# select HAVE_USER_RETURN_NOTIFIER
# config NO_BOOTMEM
# config ARCH_SUPPORTS_DEBUG_PAGEALLOC
# config HUGETLB_PAGE_SIZE_VARIABLE
config GENERIC_IRQ_PROBE config MMU
def_bool y def_bool y
config GENERIC_PENDING_IRQ config GENERIC_CSUM
def_bool y def_bool y
depends on GENERIC_HARDIRQS && SMP
config SEMAPHORE_SLEEPERS config SEMAPHORE_SLEEPERS
def_bool y def_bool y
...@@ -97,26 +106,6 @@ config HVC_TILE ...@@ -97,26 +106,6 @@ config HVC_TILE
select HVC_DRIVER select HVC_DRIVER
def_bool y def_bool y
config TILE
def_bool y
select HAVE_KVM if !TILEGX
select GENERIC_FIND_FIRST_BIT
select GENERIC_FIND_NEXT_BIT
select USE_GENERIC_SMP_HELPERS
select CC_OPTIMIZE_FOR_SIZE
# FIXME: investigate whether we need/want these options.
# select HAVE_IOREMAP_PROT
# select HAVE_OPTPROBES
# select HAVE_REGS_AND_STACK_ACCESS_API
# select HAVE_HW_BREAKPOINT
# select PERF_EVENTS
# select HAVE_USER_RETURN_NOTIFIER
# config NO_BOOTMEM
# config ARCH_SUPPORTS_DEBUG_PAGEALLOC
# config HUGETLB_PAGE_SIZE_VARIABLE
# Please note: TILE-Gx support is not yet finalized; this is # Please note: TILE-Gx support is not yet finalized; this is
# the preliminary support. TILE-Gx drivers are only provided # the preliminary support. TILE-Gx drivers are only provided
# with the alpha or beta test versions for Tilera customers. # with the alpha or beta test versions for Tilera customers.
......
arch/um/Kconfig.common
View file @ 0f5c2ac5
...@@ -3,14 +3,10 @@ config DEFCONFIG_LIST ...@@ -3,14 +3,10 @@ config DEFCONFIG_LIST
option defconfig_list option defconfig_list
default "arch/$ARCH/defconfig" default "arch/$ARCH/defconfig"
# UML uses the generic IRQ subsystem
config GENERIC_HARDIRQS
bool
default y
config UML config UML
bool bool
default y default y
select HAVE_GENERIC_HARDIRQS
config MMU config MMU
bool bool
......
arch/um/Kconfig.um
View file @ 0f5c2ac5
...@@ -120,9 +120,6 @@ config SMP ...@@ -120,9 +120,6 @@ config SMP
If you don't know what to do, say N. If you don't know what to do, say N.
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
config NR_CPUS config NR_CPUS
int "Maximum number of CPUs (2-32)" int "Maximum number of CPUs (2-32)"
range 2 32 range 2 32
......
include/linux/irqdesc.h
View file @ 0f5c2ac5
...@@ -100,13 +100,6 @@ static inline struct irq_desc *move_irq_desc(struct irq_desc *desc, int node) ...@@ -100,13 +100,6 @@ static inline struct irq_desc *move_irq_desc(struct irq_desc *desc, int node)
#define get_irq_desc_data(desc) ((desc)->irq_data.handler_data) #define get_irq_desc_data(desc) ((desc)->irq_data.handler_data)
#define get_irq_desc_msi(desc) ((desc)->irq_data.msi_desc) #define get_irq_desc_msi(desc) ((desc)->irq_data.msi_desc)
/*
* Monolithic do_IRQ implementation.
*/
#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
extern unsigned int __do_IRQ(unsigned int irq);
#endif
/* /*
* Architectures call this to let the generic IRQ layer * Architectures call this to let the generic IRQ layer
* handle an interrupt. If the descriptor is attached to an * handle an interrupt. If the descriptor is attached to an
...@@ -115,14 +108,7 @@ extern unsigned int __do_IRQ(unsigned int irq); ...@@ -115,14 +108,7 @@ extern unsigned int __do_IRQ(unsigned int irq);
*/ */
static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc) static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
{ {
#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
desc->handle_irq(irq, desc); desc->handle_irq(irq, desc);
#else
if (likely(desc->handle_irq))
desc->handle_irq(irq, desc);
else
__do_IRQ(irq);
#endif
} }
static inline void generic_handle_irq(unsigned int irq) static inline void generic_handle_irq(unsigned int irq)
......
kernel/irq/Kconfig
View file @ 0f5c2ac5
...@@ -9,9 +9,6 @@ menu "IRQ subsystem" ...@@ -9,9 +9,6 @@ menu "IRQ subsystem"
config GENERIC_HARDIRQS config GENERIC_HARDIRQS
def_bool y def_bool y
config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
# Select this to disable the deprecated stuff # Select this to disable the deprecated stuff
config GENERIC_HARDIRQS_NO_DEPRECATED config GENERIC_HARDIRQS_NO_DEPRECATED
def_bool n def_bool n
......
kernel/irq/handle.c
View file @ 0f5c2ac5
...@@ -118,114 +118,3 @@ irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action) ...@@ -118,114 +118,3 @@ irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action)
return retval; return retval;
} }
#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
#ifdef CONFIG_ENABLE_WARN_DEPRECATED
# warning __do_IRQ is deprecated. Please convert to proper flow handlers
#endif
/**
* __do_IRQ - original all in one highlevel IRQ handler
* @irq: the interrupt number
*
* __do_IRQ handles all normal device IRQ's (the special
* SMP cross-CPU interrupts have their own specific
* handlers).
*
* This is the original x86 implementation which is used for every
* interrupt type.
*/
unsigned int __do_IRQ(unsigned int irq)
{
struct irq_desc *desc = irq_to_desc(irq);
struct irqaction *action;
unsigned int status;
kstat_incr_irqs_this_cpu(irq, desc);
if (CHECK_IRQ_PER_CPU(desc->status)) {
irqreturn_t action_ret;
/*
* No locking required for CPU-local interrupts:
*/
if (desc->irq_data.chip->ack)
desc->irq_data.chip->ack(irq);
if (likely(!(desc->status & IRQ_DISABLED))) {
action_ret = handle_IRQ_event(irq, desc->action);
if (!noirqdebug)
note_interrupt(irq, desc, action_ret);
}
desc->irq_data.chip->end(irq);
return 1;
}
raw_spin_lock(&desc->lock);
if (desc->irq_data.chip->ack)
desc->irq_data.chip->ack(irq);
/*
* REPLAY is when Linux resends an IRQ that was dropped earlier
* WAITING is used by probe to mark irqs that are being tested
*/
status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING);
status |= IRQ_PENDING; /* we _want_ to handle it */
/*
* If the IRQ is disabled for whatever reason, we cannot
* use the action we have.
*/
action = NULL;
if (likely(!(status & (IRQ_DISABLED | IRQ_INPROGRESS)))) {
action = desc->action;
status &= ~IRQ_PENDING; /* we commit to handling */
status |= IRQ_INPROGRESS; /* we are handling it */
}
desc->status = status;
/*
* If there is no IRQ handler or it was disabled, exit early.
* Since we set PENDING, if another processor is handling
* a different instance of this same irq, the other processor
* will take care of it.
*/
if (unlikely(!action))
goto out;
/*
* Edge triggered interrupts need to remember
* pending events.
* This applies to any hw interrupts that allow a second
* instance of the same irq to arrive while we are in do_IRQ
* or in the handler. But the code here only handles the _second_
* instance of the irq, not the third or fourth. So it is mostly
* useful for irq hardware that does not mask cleanly in an
* SMP environment.
*/
for (;;) {
irqreturn_t action_ret;
raw_spin_unlock(&desc->lock);
action_ret = handle_IRQ_event(irq, action);
if (!noirqdebug)
note_interrupt(irq, desc, action_ret);
raw_spin_lock(&desc->lock);
if (likely(!(desc->status & IRQ_PENDING)))
break;
desc->status &= ~IRQ_PENDING;
}
desc->status &= ~IRQ_INPROGRESS;
out:
/*
* The ->end() handler has to deal with interrupts which got
* disabled while the handler was running.
*/
desc->irq_data.chip->end(irq);
raw_spin_unlock(&desc->lock);
return 1;
}
#endif
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7