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Commit 10217810 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC driver updates from Olof Johansson:
 "Some releases this branch is nearly empty, others we have more stuff.
  It tends to gather drivers that need SoC modification or dependencies
  such that they have to (also) go in through our tree.

  For this release, we have merged in part of the reset controller tree
  (with handshake that the parts we have merged in will remain stable),
  as well as dependencies on a few clock branches.

  In general, new items here are:

   - Qualcomm driver for SMM/SMD, which is how they communicate with the
     coprocessors on (some) of their platforms

   - memory controller work for ARM's PL172 memory controller

   - reset drivers for various platforms

   - PMU power domain support for Marvell platforms

   - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller
     per-SoC support"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits)
  ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze()
  ARM: tegra: Disable cpuidle if PSCI is available
  soc/tegra: pmc: Use existing pclk reference
  soc/tegra: pmc: Remove unnecessary return statement
  soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile
  memory: tegra: Add Tegra210 support
  memory: tegra: Add support for a variable-size client ID bitfield
  clk: shmobile: rz: Add CPG/MSTP Clock Domain support
  clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
  clk: shmobile: Add CPG/MSTP Clock Domain support
  ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets
  reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
  docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
  MIPS: ath79: Add the reset controller to the AR9132 dtsi
  reset: Add a driver for the reset controller on the AR71XX/AR9XXX
  devicetree: Add bindings for the ATH79 reset controller
  reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property
  doc: dt: add documentation for lpc1850-rgu reset driver
  ...
parents 50686e8a 21815b9a
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Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
View file @ 10217810
* Renesas R8A7778 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7778. It includes two PLLs and
several fixed ratio dividers
several fixed ratio dividers.
The CPG also provides a Clock Domain for SoC devices, in combination with the
CPG Module Stop (MSTP) Clocks.
Required Properties:
......@@ -10,10 +12,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are
"plla", "pllb", "b", "out", "p", "s", and "s1".
- #power-domain-cells: Must be 0
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
through an MSTP clock should refer to the CPG device node in their
"power-domains" property, as documented by the generic PM domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
Example
-------
Examples
--------
- CPG device node:
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7778-cpg-clocks";
......@@ -22,4 +32,17 @@ Example
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
#power-domain-cells = <0>;
};
- CPG/MSTP Clock Domain member device node:
sdhi0: sd@ffe4c000 {
compatible = "renesas,sdhi-r8a7778";
reg = <0xffe4c000 0x100>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
power-domains = <&cpg_clocks>;
status = "disabled";
};
Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
View file @ 10217810
* Renesas R8A7779 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7779. It includes one PLL and
several fixed ratio dividers
several fixed ratio dividers.
The CPG also provides a Clock Domain for SoC devices, in combination with the
CPG Module Stop (MSTP) Clocks.
Required Properties:
......@@ -12,16 +14,36 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "plla",
"z", "zs", "s", "s1", "p", "b", "out".
- #power-domain-cells: Must be 0
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
through an MSTP clock should refer to the CPG device node in their
"power-domains" property, as documented by the generic PM domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
Example
-------
Examples
--------
- CPG device node:
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks";
reg = <0 0xffc80000 0 0x30>;
reg = <0xffc80000 0x30>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
"b", "out";
#power-domain-cells = <0>;
};
- CPG/MSTP Clock Domain member device node:
sata: sata@fc600000 {
compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
reg = <0xfc600000 0x2000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
power-domains = <&cpg_clocks>;
};
Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
View file @ 10217810
......@@ -2,6 +2,8 @@
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.
The CPG also provides a Clock Domain for SoC devices, in combination with the
CPG Module Stop (MSTP) Clocks.
Required Properties:
......@@ -20,10 +22,18 @@ Required Properties:
- clock-output-names: The names of the clocks. Supported clocks are "main",
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
"adsp"
- #power-domain-cells: Must be 0
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
through an MSTP clock should refer to the CPG device node in their
"power-domains" property, as documented by the generic PM domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
Example
-------
Examples
--------
- CPG device node:
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7790-cpg-clocks",
......@@ -34,4 +44,16 @@ Example
clock-output-names = "main", "pll0, "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1", "z",
"rcan", "adsp";
#power-domain-cells = <0>;
};
- CPG/MSTP Clock Domain member device node:
thermal@e61f0000 {
compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
power-domains = <&cpg_clocks>;
};
Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
View file @ 10217810
......@@ -2,6 +2,8 @@
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
The CPG also provides a Clock Domain for SoC devices, in combination with the
CPG Module Stop (MSTP) Clocks.
Required Properties:
......@@ -14,10 +16,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "pll",
"i", and "g"
- #power-domain-cells: Must be 0
SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
through an MSTP clock should refer to the CPG device node in their
"power-domains" property, as documented by the generic PM domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
Example
-------
Examples
--------
- CPG device node:
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
......@@ -26,4 +36,19 @@ Example
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
#power-domain-cells = <0>;
};
- CPG/MSTP Clock Domain member device node:
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
status = "disabled";
};
Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt 0 → 100644
View file @ 10217810
Tegra124 CPU frequency scaling driver bindings
----------------------------------------------
Both required and optional properties listed below must be defined
under node /cpus/cpu@0.
Required properties:
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- cpu_g: Clock mux for the fast CPU cluster.
- cpu_lp: Clock mux for the low-power CPU cluster.
- pll_x: Fast PLL clocksource.
- pll_p: Auxiliary PLL used during fast PLL rate changes.
- dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
- vdd-cpu-supply: Regulator for CPU voltage
Optional properties:
- clock-latency: Specify the possible maximum transition latency for clock,
in unit of nanoseconds.
Example:
--------
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
<&tegra_car TEGRA124_CLK_CCLK_LP>,
<&tegra_car TEGRA124_CLK_PLL_X>,
<&tegra_car TEGRA124_CLK_PLL_P>,
<&dfll>;
clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
clock-latency = <300000>;
vdd-cpu-supply: <&vdd_cpu>;
};
<...>
};
Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt 0 → 100644
View file @ 10217810
* Device tree bindings for ARM PL172 MultiPort Memory Controller
Required properties:
- compatible: "arm,pl172", "arm,primecell"
- reg: Must contains offset/length value for controller.
- #address-cells: Must be 2. The partition number has to be encoded in the
first address cell and it may accept values 0..N-1
(N - total number of partitions). The second cell is the
offset into the partition.
- #size-cells: Must be set to 1.
- ranges: Must contain one or more chip select memory regions.
- clocks: Must contain references to controller clocks.
- clock-names: Must contain "mpmcclk" and "apb_pclk".
- clock-ranges: Empty property indicating that child nodes can inherit
named clocks. Required only if clock tree data present
in device tree.
See clock-bindings.txt
Child chip-select (cs) nodes contain the memory devices nodes connected to
such as NOR (e.g. cfi-flash) and NAND.
Required child cs node properties:
- #address-cells: Must be 2.
- #size-cells: Must be 1.
- ranges: Empty property indicating that child nodes can inherit
memory layout.
- clock-ranges: Empty property indicating that child nodes can inherit
named clocks. Required only if clock tree data present
in device tree.
- mpmc,cs: Chip select number. Indicates to the pl0172 driver
which chipselect is used for accessing the memory.
- mpmc,memory-width: Width of the chip select memory. Must be equal to
either 8, 16 or 32.
Optional child cs node config properties:
- mpmc,async-page-mode: Enable asynchronous page mode.
- mpmc,cs-active-high: Set chip select polarity to active high.
- mpmc,byte-lane-low: Set byte lane state to low.
- mpmc,extended-wait: Enable extended wait.
- mpmc,buffer-enable: Enable write buffer.
- mpmc,write-protect: Enable write protect.
Optional child cs node timing properties:
- mpmc,write-enable-delay: Delay from chip select assertion to write
enable (WE signal) in nano seconds.
- mpmc,output-enable-delay: Delay from chip select assertion to output
enable (OE signal) in nano seconds.
- mpmc,write-access-delay: Delay from chip select assertion to write
access in nano seconds.
- mpmc,read-access-delay: Delay from chip select assertion to read
access in nano seconds.
- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
accesses in nano seconds.
- mpmc,turn-round-delay: Delay between access to memory banks in nano
seconds.
If any of the above timing parameters are absent, current parameter value will
be taken from the corresponding HW reg.
Example for pl172 with nor flash on chip select 0 shown below.
emc: memory-controller@40005000 {
compatible = "arm,pl172", "arm,primecell";
reg = <0x40005000 0x1000>;
clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
clock-names = "mpmcclk", "apb_pclk";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x1c000000 0x1000000
1 0 0x1d000000 0x1000000
2 0 0x1e000000 0x1000000
3 0 0x1f000000 0x1000000>;
cs0 {
#address-cells = <2>;
#size-cells = <1>;
ranges;
mpmc,cs = <0>;
mpmc,memory-width = <16>;
mpmc,byte-lane-low;
mpmc,write-enable-delay = <0>;
mpmc,output-enable-delay = <0>;
mpmc,read-enable-delay = <70>;
mpmc,page-mode-read-delay = <70>;
flash@0,0 {
compatible = "sst,sst39vf320", "cfi-flash";
reg = <0 0 0x400000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "data";
reg = <0 0x400000>;
};
};
};
};
Documentation/devicetree/bindings/reset/ath79-reset.txt 0 → 100644
View file @ 10217810
Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required Properties:
- compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"
as fallback
- reg: Base address and size of the controllers memory area
- #reset-cells : Specifies the number of cells needed to encode reset
line, should be 1
Example:
reset-controller@1806001c {
compatible = "qca,ar9132-reset", "qca,ar7100-reset";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt 0 → 100644
View file @ 10217810
NXP LPC1850 Reset Generation Unit (RGU)
========================================
Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
- compatible: Should be "nxp,lpc1850-rgu"
- reg: register base and length
- clocks: phandle and clock specifier to RGU clocks
- clock-names: should contain "delay" and "reg"
- #reset-cells: should be 1
See table below for valid peripheral reset numbers. Numbers not
in the table below are either reserved or not applicable for
normal operation.
Reset Peripheral
9 System control unit (SCU)
12 ARM Cortex-M0 subsystem core (LPC43xx only)
13 CPU core
16 LCD controller
17 USB0
18 USB1
19 DMA
20 SDIO
21 External memory controller (EMC)
22 Ethernet
25 Flash bank A
27 EEPROM
28 GPIO
29 Flash bank B
32 Timer0
33 Timer1
34 Timer2
35 Timer3
36 Repetitive Interrupt timer (RIT)
37 State Configurable Timer (SCT)
38 Motor control PWM (MCPWM)
39 QEI
40 ADC0
41 ADC1
42 DAC
44 USART0
45 UART1
46 USART2
47 USART3
48 I2C0
49 I2C1
50 SSP0
51 SSP1
52 I2S0 and I2S1
53 Serial Flash Interface (SPIFI)
54 C_CAN1
55 C_CAN0
56 ARM Cortex-M0 application core (LPC4370 only)
57 SGPIO (LPC43xx only)
58 SPI (LPC43xx only)
60 ADCHS (12-bit ADC) (LPC4370 only)
Refer to NXP LPC18xx or LPC43xx user manual for more details about
the reset signals and the connected block/peripheral.
Reset provider example:
rgu: reset-controller@40053000 {
compatible = "nxp,lpc1850-rgu";
reg = <0x40053000 0x1000>;
clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
clock-names = "delay", "reg";
#reset-cells = <1>;
};
Reset consumer example:
mac: ethernet@40010000 {
compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
reg = <0x40010000 0x2000>;
interrupts = <5>;
interrupt-names = "macirq";
clocks = <&ccu1 CLK_CPU_ETHERNET>;
clock-names = "stmmaceth";
resets = <&rgu 22>;
reset-names = "stmmaceth";
status = "disabled";
};
Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt
View file @ 10217810
......@@ -39,4 +39,4 @@ Example:
};
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset-controller/stih407-resets.h
include/dt-bindings/reset/stih407-resets.h
Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
View file @ 10217810
......@@ -43,5 +43,5 @@ example:
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset-controller/stih415-resets.h
include/dt-bindings/reset-controller/stih416-resets.h
include/dt-bindings/reset/stih415-resets.h
include/dt-bindings/reset/stih416-resets.h
Documentation/devicetree/bindings/reset/st,sti-softreset.txt
View file @ 10217810
......@@ -42,5 +42,5 @@ example:
Macro definitions for the supported reset channels can be found in:
include/dt-bindings/reset-controller/stih415-resets.h
include/dt-bindings/reset-controller/stih416-resets.h
include/dt-bindings/reset/stih415-resets.h
include/dt-bindings/reset/stih416-resets.h
Documentation/devicetree/bindings/reset/zynq-reset.txt 0 → 100644
View file @ 10217810
Xilinx Zynq Reset Manager
The Zynq AP-SoC has several different resets.
See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
Required properties:
- compatible: "xlnx,zynq-reset"
- reg: SLCR offset and size taken via syscon <0x200 0x48>
- syscon: <&slcr>
This should be a phandle to the Zynq's SLCR registers.
- #reset-cells: Must be 1
The Zynq Reset Manager needs to be a childnode of the SLCR.
Example:
rstc: rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <1>;
syscon = <&slcr>;
};
Reset outputs:
0 : soft reset
32 : ddr reset
64 : topsw reset
96 : dmac reset
128: usb0 reset
129: usb1 reset
160: gem0 reset
161: gem1 reset
164: gem0 rx reset
165: gem1 rx reset
166: gem0 ref reset
167: gem1 ref reset
192: sdio0 reset
193: sdio1 reset
196: sdio0 ref reset
197: sdio1 ref reset
224: spi0 reset
225: spi1 reset
226: spi0 ref reset
227: spi1 ref reset
256: can0 reset
257: can1 reset
258: can0 ref reset
259: can1 ref reset
288: i2c0 reset
289: i2c1 reset
320: uart0 reset
321: uart1 reset
322: uart0 ref reset
323: uart1 ref reset
352: gpio reset
384: lqspi reset
385: qspi ref reset
416: smc reset
417: smc ref reset
448: ocm reset
512: fpga0 out reset
513: fpga1 out reset
514: fpga2 out reset
515: fpga3 out reset
544: a9 reset 0
545: a9 reset 1
552: peri reset
Documentation/devicetree/bindings/soc/qcom,smd-rpm.txt 0 → 100644
View file @ 10217810
Qualcomm Resource Power Manager (RPM) over SMD
This driver is used to interface with the Resource Power Manager (RPM) found in
various Qualcomm platforms. The RPM allows each component in the system to vote
for state of the system resources, such as clocks, regulators and bus
frequencies.
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,rpm-msm8974"
- qcom,smd-channels:
Usage: required
Value type: <stringlist>
Definition: Shared Memory channel used for communication with the RPM
= SUBDEVICES
The RPM exposes resources to its subnodes. The below bindings specify the set
of valid subnodes that can operate on these resources.
== Regulators
Regulator nodes are identified by their compatible:
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,rpm-pm8841-regulators"
"qcom,rpm-pm8941-regulators"
- vdd_s1-supply:
- vdd_s2-supply:
- vdd_s3-supply:
- vdd_s4-supply:
- vdd_s5-supply:
- vdd_s6-supply:
- vdd_s7-supply:
- vdd_s8-supply:
Usage: optional (pm8841 only)
Value type: <phandle>
Definition: reference to regulator supplying the input pin, as
described in the data sheet
- vdd_s1-supply:
- vdd_s2-supply:
- vdd_s3-supply:
- vdd_l1_l3-supply:
- vdd_l2_lvs1_2_3-supply:
- vdd_l4_l11-supply:
- vdd_l5_l7-supply:
- vdd_l6_l12_l14_l15-supply:
- vdd_l8_l16_l18_l19-supply:
- vdd_l9_l10_l17_l22-supply:
- vdd_l13_l20_l23_l24-supply:
- vdd_l21-supply:
- vin_5vs-supply:
Usage: optional (pm8941 only)
Value type: <phandle>
Definition: reference to regulator supplying the input pin, as
described in the data sheet
The regulator node houses sub-nodes for each regulator within the device. Each
sub-node is identified using the node's name, with valid values listed for each
of the pmics below.
pm8841:
s1, s2, s3, s4, s5, s6, s7, s8
pm8941:
s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2,
lvs3, 5vs1, 5vs2
The content of each sub-node is defined by the standard binding for regulators -
see regulator.txt.
= EXAMPLE
smd {
compatible = "qcom,smd";
rpm {
interrupts = <0 168 1>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests {
compatible = "qcom,rpm-msm8974";
qcom,smd-channels = "rpm_requests";
pm8941-regulators {
compatible = "qcom,rpm-pm8941-regulators";
vdd_l13_l20_l23_l24-supply = <&pm8941_boost>;
pm8941_s3: s3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8941_boost: s4 {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
pm8941_l20: l20 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
};
};
};
};
};
Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt 0 → 100644
View file @ 10217810
Qualcomm Shared Memory Driver (SMD) binding
This binding describes the Qualcomm Shared Memory Driver, a fifo based
communication channel for sending data between the various subsystems in
Qualcomm platforms.
- compatible:
Usage: required
Value type: <stringlist>
Definition: must be "qcom,smd"
= EDGES
Each subnode of the SMD node represents a remote subsystem or a remote
processor of some sort - or in SMD language an "edge". The name of the edges
are not important.
The edge is described by the following properties:
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the IRQ used by the remote processor to
signal this processor about communication related updates
- qcom,ipc:
Usage: required
Value type: <prop-encoded-array>
Definition: three entries specifying the outgoing ipc bit used for
signaling the remote processor:
- phandle to a syscon node representing the apcs registers
- u32 representing offset to the register within the syscon
- u32 representing the ipc bit within the register
- qcom,smd-edge:
Usage: required
Value type: <u32>
Definition: the identifier of the remote processor in the smd channel
allocation table
= SMD DEVICES
In turn, subnodes of the "edges" represent devices tied to SMD channels on that
"edge". The names of the devices are not important. The properties of these
nodes are defined by the individual bindings for the SMD devices - but must
contain the following property:
- qcom,smd-channels:
Usage: required
Value type: <stringlist>
Definition: a list of channels tied to this device, used for matching
the device to channels
= EXAMPLE
The following example represents a smd node, with one edge representing the
"rpm" subsystem. For the "rpm" subsystem we have a device tied to the
"rpm_request" channel.
apcs: syscon@f9011000 {
compatible = "syscon";
reg = <0xf9011000 0x1000>;
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <0 168 1>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests {
compatible = "qcom,rpm-msm8974";
qcom,smd-channels = "rpm_requests";
...
};
};
};
MAINTAINERS
View file @ 10217810
......@@ -8613,6 +8613,7 @@ M: Philipp Zabel <p.zabel@pengutronix.de>
S: Maintained
F: drivers/reset/
F: Documentation/devicetree/bindings/reset/
F: include/dt-bindings/reset/
F: include/linux/reset.h
F: include/linux/reset-controller.h
......
arch/arm/boot/dts/stih407-family.dtsi
View file @ 10217810
......@@ -9,7 +9,7 @@
#include "stih407-pinctrl.dtsi"
#include <dt-bindings/mfd/st-lpc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset-controller/stih407-resets.h>
#include <dt-bindings/reset/stih407-resets.h>
#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
#address-cells = <1>;
......
arch/arm/boot/dts/stih415.dtsi
View file @ 10217810
......@@ -10,7 +10,7 @@
#include "stih415-clock.dtsi"
#include "stih415-pinctrl.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/stih415-resets.h>
#include <dt-bindings/reset/stih415-resets.h>
/ {
L2: cache-controller {
......
arch/arm/boot/dts/stih416.dtsi
View file @ 10217810
......@@ -12,7 +12,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset-controller/stih416-resets.h>
#include <dt-bindings/reset/stih416-resets.h>
#include <dt-bindings/interrupt-controller/irq-st.h>
/ {
L2: cache-controller {
......
arch/arm/mach-mvebu/Kconfig
View file @ 10217810
......@@ -96,6 +96,7 @@ config MACH_DOVE
select MACH_MVEBU_ANY
select ORION_IRQCHIP
select ORION_TIMER
select PM_GENERIC_DOMAINS if PM
select PINCTRL_DOVE
help
Say 'Y' here if you want your kernel to support the
......
arch/arm/mach-mvebu/dove.c
View file @ 10217810
......@@ -12,6 +12,7 @@
#include <linux/mbus.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/soc/dove/pmu.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/arch.h>
#include "common.h"
......@@ -24,6 +25,7 @@ static void __init dove_init(void)
tauros2_init(0);
#endif
BUG_ON(mvebu_mbus_dt_init(false));
dove_init_pmu();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
......
arch/arm/mach-shmobile/Kconfig
View file @ 10217810
......@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
config PM_RCAR
bool
select PM_GENERIC_DOMAINS if PM
config PM_RMOBILE
bool
......@@ -50,6 +51,7 @@ config ARCH_EMEV2
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
select PM_GENERIC_DOMAINS if PM
select SYS_SUPPORTS_SH_MTU2
config ARCH_R8A73A4
......
arch/arm/mach-tegra/cpuidle-tegra114.c
View file @ 10217810
......@@ -24,6 +24,7 @@
#include <asm/cpuidle.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/psci.h>
#include "pm.h"
#include "sleep.h"
......@@ -44,16 +45,12 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
tegra_set_cpu_in_lp2();
cpu_pm_enter();
tick_broadcast_enter();
call_firmware_op(prepare_idle);
/* Do suspend by ourselves if the firmware does not implement it */
if (call_firmware_op(do_idle, 0) == -ENOSYS)
cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
tick_broadcast_exit();
cpu_pm_exit();
tegra_clear_cpu_in_lp2();
......@@ -61,6 +58,13 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
return index;
}
static void tegra114_idle_enter_freeze(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
tegra114_idle_power_down(dev, drv, index);
}
#endif
static struct cpuidle_driver tegra_idle_driver = {
......@@ -72,8 +76,10 @@ static struct cpuidle_driver tegra_idle_driver = {
#ifdef CONFIG_PM_SLEEP
[1] = {
.enter = tegra114_idle_power_down,
.enter_freeze = tegra114_idle_enter_freeze,
.exit_latency = 500,
.target_residency = 1000,
.flags = CPUIDLE_FLAG_TIMER_STOP,
.power_usage = 0,
.name = "powered-down",
.desc = "CPU power gated",
......@@ -84,5 +90,8 @@ static struct cpuidle_driver tegra_idle_driver = {
int __init tegra114_cpuidle_init(void)
{
return cpuidle_register(&tegra_idle_driver, NULL);
if (!psci_smp_available())
return cpuidle_register(&tegra_idle_driver, NULL);
return 0;
}
arch/arm/mach-tegra/iomap.h
View file @ 10217810
......@@ -82,9 +82,6 @@
#define TEGRA_EMC_BASE 0x7000F400
#define TEGRA_EMC_SIZE SZ_1K
#define TEGRA_FUSE_BASE 0x7000F800
#define TEGRA_FUSE_SIZE SZ_1K
#define TEGRA_EMC0_BASE 0x7001A000
#define TEGRA_EMC0_SIZE SZ_2K
......
arch/mips/Kconfig
View file @ 10217810
......@@ -118,6 +118,7 @@ config ATH25
config ATH79
bool "Atheros AR71XX/AR724X/AR913X based boards"
select ARCH_HAS_RESET_CONTROLLER
select ARCH_REQUIRE_GPIOLIB
select BOOT_RAW
select CEVT_R4K
......
arch/mips/boot/dts/qca/ar9132.dtsi
View file @ 10217810
......@@ -115,6 +115,14 @@ miscintc: interrupt-controller@18060010 {
interrupt-controller;
#interrupt-cells = <1>;
};
rst: reset-controller@1806001c {
compatible = "qca,ar9132-reset",
"qca,ar7100-reset";
reg = <0x1806001c 0x4>;
#reset-cells = <1>;
};
};
spi@1f000000 {
......
drivers/clk/shmobile/clk-mstp.c
View file @ 10217810
......@@ -2,6 +2,7 @@
* R-Car MSTP clocks
*
* Copyright (C) 2013 Ideas On Board SPRL
* Copyright (C) 2015 Glider bvba
*
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*
......@@ -10,11 +11,16 @@
* the Free Software Foundation; version 2 of the License.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/shmobile.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/spinlock.h>
/*
......@@ -236,3 +242,84 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
}
CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
struct clk *clk;
int i = 0;
int error;
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
&clkspec)) {
if (of_device_is_compatible(clkspec.np,
"renesas,cpg-mstp-clocks"))
goto found;
of_node_put(clkspec.np);
i++;
}
return 0;
found:
clk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(clk))
return PTR_ERR(clk);
error = pm_clk_create(dev);
if (error) {
dev_err(dev, "pm_clk_create failed %d\n", error);
goto fail_put;
}
error = pm_clk_add_clk(dev, clk);
if (error) {
dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
goto fail_destroy;
}
return 0;
fail_destroy:
pm_clk_destroy(dev);
fail_put:
clk_put(clk);
return error;
}
void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
{
if (!list_empty(&dev->power.subsys_data->clock_list))
pm_clk_destroy(dev);
}
void __init cpg_mstp_add_clk_domain(struct device_node *np)
{
struct generic_pm_domain *pd;
u32 ncells;
if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
pr_warn("%s lacks #power-domain-cells\n", np->full_name);
return;
}
pd = kzalloc(sizeof(*pd), GFP_KERNEL);
if (!pd)
return;
pd->name = np->name;
pd->flags = GENPD_FLAG_PM_CLK;
pm_genpd_init(pd, &simple_qos_governor, false);
pd->attach_dev = cpg_mstp_attach_dev;
pd->detach_dev = cpg_mstp_detach_dev;
of_genpd_add_provider_simple(np, pd);
}
#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
drivers/clk/shmobile/clk-r8a7778.c
View file @ 10217810
......@@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
......
drivers/clk/shmobile/clk-r8a7779.c
View file @ 10217810
......@@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
r8a7779_cpg_clocks_init);
......
drivers/clk/shmobile/clk-rcar-gen2.c
View file @ 10217810
......@@ -415,6 +415,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
rcar_gen2_cpg_clocks_init);
......
drivers/clk/shmobile/clk-rz.c
View file @ 10217810
......@@ -10,6 +10,7 @@
*/
#include <linux/clk-provider.h>
#include <linux/clk/shmobile.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
......@@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
drivers/cpufreq/Kconfig.arm
View file @ 10217810
......@@ -247,12 +247,19 @@ config ARM_SPEAR_CPUFREQ
help
This adds the CPUFreq driver support for SPEAr SOCs.
config ARM_TEGRA_CPUFREQ
bool "TEGRA CPUFreq support"
config ARM_TEGRA20_CPUFREQ
bool "Tegra20 CPUFreq support"
depends on ARCH_TEGRA
default y
help
This adds the CPUFreq driver support for TEGRA SOCs.
This adds the CPUFreq driver support for Tegra20 SOCs.
config ARM_TEGRA124_CPUFREQ
tristate "Tegra124 CPUFreq support"
depends on ARCH_TEGRA && CPUFREQ_DT
default y
help
This adds the CPUFreq driver support for Tegra124 SOCs.
config ARM_PXA2xx_CPUFREQ
tristate "Intel PXA2xx CPUfreq driver"
......
drivers/cpufreq/Makefile
View file @ 10217810
......@@ -76,7 +76,8 @@ obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o
obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o
obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o
obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o
obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
##################################################################################
......
drivers/cpufreq/tegra124-cpufreq.c 0 → 100644
View file @ 10217810
/*
* Tegra 124 cpufreq driver
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/clk.h>
#include <linux/cpufreq-dt.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
#include <linux/types.h>
struct tegra124_cpufreq_priv {
struct regulator *vdd_cpu_reg;
struct clk *cpu_clk;
struct clk *pllp_clk;
struct clk *pllx_clk;
struct clk *dfll_clk;
struct platform_device *cpufreq_dt_pdev;
};
static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv)
{
struct clk *orig_parent;
int ret;
ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk));
if (ret)
return ret;
orig_parent = clk_get_parent(priv->cpu_clk);
clk_set_parent(priv->cpu_clk, priv->pllp_clk);
ret = clk_prepare_enable(priv->dfll_clk);
if (ret)
goto out;
clk_set_parent(priv->cpu_clk, priv->dfll_clk);
return 0;
out:
clk_set_parent(priv->cpu_clk, orig_parent);
return ret;
}
static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv)
{
clk_set_parent(priv->cpu_clk, priv->pllp_clk);
clk_disable_unprepare(priv->dfll_clk);
regulator_sync_voltage(priv->vdd_cpu_reg);
clk_set_parent(priv->cpu_clk, priv->pllx_clk);
}
static struct cpufreq_dt_platform_data cpufreq_dt_pd = {
.independent_clocks = false,
};
static int tegra124_cpufreq_probe(struct platform_device *pdev)
{
struct tegra124_cpufreq_priv *priv;
struct device_node *np;
struct device *cpu_dev;
struct platform_device_info cpufreq_dt_devinfo = {};
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
cpu_dev = get_cpu_device(0);
if (!cpu_dev)
return -ENODEV;
np = of_cpu_device_node_get(0);
if (!np)
return -ENODEV;
priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu");
if (IS_ERR(priv->vdd_cpu_reg)) {
ret = PTR_ERR(priv->vdd_cpu_reg);
goto out_put_np;
}
priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
if (IS_ERR(priv->cpu_clk)) {
ret = PTR_ERR(priv->cpu_clk);
goto out_put_vdd_cpu_reg;
}
priv->dfll_clk = of_clk_get_by_name(np, "dfll");
if (IS_ERR(priv->dfll_clk)) {
ret = PTR_ERR(priv->dfll_clk);
goto out_put_cpu_clk;
}
priv->pllx_clk = of_clk_get_by_name(np, "pll_x");
if (IS_ERR(priv->pllx_clk)) {
ret = PTR_ERR(priv->pllx_clk);
goto out_put_dfll_clk;
}
priv->pllp_clk = of_clk_get_by_name(np, "pll_p");
if (IS_ERR(priv->pllp_clk)) {
ret = PTR_ERR(priv->pllp_clk);
goto out_put_pllx_clk;
}
ret = tegra124_cpu_switch_to_dfll(priv);
if (ret)
goto out_put_pllp_clk;
cpufreq_dt_devinfo.name = "cpufreq-dt";
cpufreq_dt_devinfo.parent = &pdev->dev;
cpufreq_dt_devinfo.data = &cpufreq_dt_pd;
cpufreq_dt_devinfo.size_data = sizeof(cpufreq_dt_pd);
priv->cpufreq_dt_pdev =
platform_device_register_full(&cpufreq_dt_devinfo);
if (IS_ERR(priv->cpufreq_dt_pdev)) {
ret = PTR_ERR(priv->cpufreq_dt_pdev);
goto out_switch_to_pllx;
}
platform_set_drvdata(pdev, priv);
return 0;
out_switch_to_pllx:
tegra124_cpu_switch_to_pllx(priv);
out_put_pllp_clk:
clk_put(priv->pllp_clk);
out_put_pllx_clk:
clk_put(priv->pllx_clk);
out_put_dfll_clk:
clk_put(priv->dfll_clk);
out_put_cpu_clk:
clk_put(priv->cpu_clk);
out_put_vdd_cpu_reg:
regulator_put(priv->vdd_cpu_reg);
out_put_np:
of_node_put(np);
return ret;
}
static int tegra124_cpufreq_remove(struct platform_device *pdev)
{
struct tegra124_cpufreq_priv *priv = platform_get_drvdata(pdev);
platform_device_unregister(priv->cpufreq_dt_pdev);
tegra124_cpu_switch_to_pllx(priv);
clk_put(priv->pllp_clk);
clk_put(priv->pllx_clk);
clk_put(priv->dfll_clk);
clk_put(priv->cpu_clk);
regulator_put(priv->vdd_cpu_reg);
return 0;
}
static struct platform_driver tegra124_cpufreq_platdrv = {
.driver.name = "cpufreq-tegra124",
.probe = tegra124_cpufreq_probe,
.remove = tegra124_cpufreq_remove,
};
static int __init tegra_cpufreq_init(void)
{
int ret;
struct platform_device *pdev;
if (!of_machine_is_compatible("nvidia,tegra124"))
return -ENODEV;
/*
* Platform driver+device required for handling EPROBE_DEFER with
* the regulator and the DFLL clock
*/
ret = platform_driver_register(&tegra124_cpufreq_platdrv);
if (ret)
return ret;
pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);
if (IS_ERR(pdev)) {
platform_driver_unregister(&tegra124_cpufreq_platdrv);
return PTR_ERR(pdev);
}
return 0;
}
module_init(tegra_cpufreq_init);
MODULE_AUTHOR("Tuomas Tynkkynen <ttynkkynen@nvidia.com>");
MODULE_DESCRIPTION("cpufreq driver for NVIDIA Tegra124");
MODULE_LICENSE("GPL v2");
drivers/iommu/Kconfig
View file @ 10217810
......@@ -222,7 +222,7 @@ config TEGRA_IOMMU_SMMU
select IOMMU_API
help
This driver supports the IOMMU hardware (SMMU) found on NVIDIA Tegra
SoCs (Tegra30 up to Tegra132).
SoCs (Tegra30 up to Tegra210).
config EXYNOS_IOMMU
bool "Exynos IOMMU Support"
......
drivers/memory/Kconfig
View file @ 10217810
......@@ -7,6 +7,14 @@ menuconfig MEMORY
if MEMORY
config ARM_PL172_MPMC
tristate "ARM PL172 MPMC driver"
depends on ARM_AMBA && OF
help
This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
If you have an embedded system with an AMBA bus and a PL172
controller, say Y or M here.
config ATMEL_SDRAMC
bool "Atmel (Multi-port DDR-)SDRAM Controller"
default y
......
drivers/memory/Makefile
View file @ 10217810
......@@ -5,6 +5,7 @@
ifeq ($(CONFIG_DDR),y)
obj-$(CONFIG_OF) += of_memory.o
endif
obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o
obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o
obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
obj-$(CONFIG_TI_EMIF) += emif.o
......
drivers/memory/pl172.c 0 → 100644
View file @ 10217810
/*
* Memory controller driver for ARM PrimeCell PL172
* PrimeCell MultiPort Memory Controller (PL172)
*
* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
*
* Based on:
* TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/amba/bus.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/time.h>
#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * n)
#define MPMC_STATIC_CFG_MW_8BIT 0x0
#define MPMC_STATIC_CFG_MW_16BIT 0x1
#define MPMC_STATIC_CFG_MW_32BIT 0x2
#define MPMC_STATIC_CFG_PM BIT(3)
#define MPMC_STATIC_CFG_PC BIT(6)
#define MPMC_STATIC_CFG_PB BIT(7)
#define MPMC_STATIC_CFG_EW BIT(8)
#define MPMC_STATIC_CFG_B BIT(19)
#define MPMC_STATIC_CFG_P BIT(20)
#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * n)
#define MPMC_STATIC_WAIT_WEN_MAX 0x0f
#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * n)
#define MPMC_STATIC_WAIT_OEN_MAX 0x0f
#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * n)
#define MPMC_STATIC_WAIT_RD_MAX 0x1f
#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * n)
#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * n)
#define MPMC_STATIC_WAIT_WR_MAX 0x1f
#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * n)
#define MPMC_STATIC_WAIT_TURN_MAX 0x0f
/* Maximum number of static chip selects */
#define PL172_MAX_CS 4
struct pl172_data {
void __iomem *base;
unsigned long rate;
struct clk *clk;
};
static int pl172_timing_prop(struct amba_device *adev,
const struct device_node *np, const char *name,
u32 reg_offset, u32 max, int start)
{
struct pl172_data *pl172 = amba_get_drvdata(adev);
int cycles;
u32 val;
if (!of_property_read_u32(np, name, &val)) {
cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
if (cycles < 0) {
cycles = 0;
} else if (cycles > max) {
dev_err(&adev->dev, "%s timing too tight\n", name);
return -EINVAL;
}
writel(cycles, pl172->base + reg_offset);
}
dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
readl(pl172->base + reg_offset));
return 0;
}
static int pl172_setup_static(struct amba_device *adev,
struct device_node *np, u32 cs)
{
struct pl172_data *pl172 = amba_get_drvdata(adev);
u32 cfg;
int ret;
/* MPMC static memory configuration */
if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
if (cfg == 8) {
cfg = MPMC_STATIC_CFG_MW_8BIT;
} else if (cfg == 16) {
cfg = MPMC_STATIC_CFG_MW_16BIT;
} else if (cfg == 32) {
cfg = MPMC_STATIC_CFG_MW_32BIT;
} else {
dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
return -EINVAL;
}
} else {
dev_err(&adev->dev, "memory-width property required\n");
return -EINVAL;
}
if (of_property_read_bool(np, "mpmc,async-page-mode"))
cfg |= MPMC_STATIC_CFG_PM;
if (of_property_read_bool(np, "mpmc,cs-active-high"))
cfg |= MPMC_STATIC_CFG_PC;
if (of_property_read_bool(np, "mpmc,byte-lane-low"))
cfg |= MPMC_STATIC_CFG_PB;
if (of_property_read_bool(np, "mpmc,extended-wait"))
cfg |= MPMC_STATIC_CFG_EW;
if (of_property_read_bool(np, "mpmc,buffer-enable"))
cfg |= MPMC_STATIC_CFG_B;
if (of_property_read_bool(np, "mpmc,write-protect"))
cfg |= MPMC_STATIC_CFG_P;
writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
/* MPMC static memory timing */
ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
MPMC_STATIC_WAIT_WEN(cs),
MPMC_STATIC_WAIT_WEN_MAX, 1);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
MPMC_STATIC_WAIT_OEN(cs),
MPMC_STATIC_WAIT_OEN_MAX, 0);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
MPMC_STATIC_WAIT_RD(cs),
MPMC_STATIC_WAIT_RD_MAX, 1);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
MPMC_STATIC_WAIT_PAGE(cs),
MPMC_STATIC_WAIT_PAGE_MAX, 1);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
MPMC_STATIC_WAIT_WR(cs),
MPMC_STATIC_WAIT_WR_MAX, 2);
if (ret)
goto fail;
ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
MPMC_STATIC_WAIT_TURN(cs),
MPMC_STATIC_WAIT_TURN_MAX, 1);
if (ret)
goto fail;
return 0;
fail:
dev_err(&adev->dev, "failed to configure cs%u\n", cs);
return ret;
}
static int pl172_parse_cs_config(struct amba_device *adev,
struct device_node *np)
{
u32 cs;
if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
if (cs >= PL172_MAX_CS) {
dev_err(&adev->dev, "cs%u invalid\n", cs);
return -EINVAL;
}
return pl172_setup_static(adev, np, cs);
}
dev_err(&adev->dev, "cs property required\n");
return -EINVAL;
}
static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device_node *child_np, *np = adev->dev.of_node;
struct device *dev = &adev->dev;
static const char *rev = "?";
struct pl172_data *pl172;
int ret;
if (amba_part(adev) == 0x172) {
if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
rev = pl172_revisions[amba_rev(adev)];
}
dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
if (!pl172)
return -ENOMEM;
pl172->clk = devm_clk_get(dev, "mpmcclk");
if (IS_ERR(pl172->clk)) {
dev_err(dev, "no mpmcclk provided clock\n");
return PTR_ERR(pl172->clk);
}
ret = clk_prepare_enable(pl172->clk);
if (ret) {
dev_err(dev, "unable to mpmcclk enable clock\n");
return ret;
}
pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
if (!pl172->rate) {
dev_err(dev, "unable to get mpmcclk clock rate\n");
ret = -EINVAL;
goto err_clk_enable;
}
ret = amba_request_regions(adev, NULL);
if (ret) {
dev_err(dev, "unable to request AMBA regions\n");
goto err_clk_enable;
}
pl172->base = devm_ioremap(dev, adev->res.start,
resource_size(&adev->res));
if (!pl172->base) {
dev_err(dev, "ioremap failed\n");
ret = -ENOMEM;
goto err_no_ioremap;
}
amba_set_drvdata(adev, pl172);
/*
* Loop through each child node, which represent a chip select, and
* configure parameters and timing. If successful; populate devices
* under that node.
*/
for_each_available_child_of_node(np, child_np) {
ret = pl172_parse_cs_config(adev, child_np);
if (ret)
continue;
of_platform_populate(child_np, NULL, NULL, dev);
}
return 0;
err_no_ioremap:
amba_release_regions(adev);
err_clk_enable:
clk_disable_unprepare(pl172->clk);
return ret;
}
static int pl172_remove(struct amba_device *adev)
{
struct pl172_data *pl172 = amba_get_drvdata(adev);
clk_disable_unprepare(pl172->clk);
amba_release_regions(adev);
return 0;
}
static const struct amba_id pl172_ids[] = {
{
.id = 0x07341172,
.mask = 0xffffffff,
},
{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, pl172_ids);
static struct amba_driver pl172_driver = {
.drv = {
.name = "memory-pl172",
},
.probe = pl172_probe,
.remove = pl172_remove,
.id_table = pl172_ids,
};
module_amba_driver(pl172_driver);
MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
MODULE_DESCRIPTION("PL172 Memory Controller Driver");
MODULE_LICENSE("GPL v2");
drivers/memory/tegra/Makefile
View file @ 10217810
......@@ -4,6 +4,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
......
drivers/memory/tegra/mc.c
View file @ 10217810
......@@ -42,7 +42,6 @@
#define MC_ERR_STATUS_ADR_HI_MASK 0x3
#define MC_ERR_STATUS_SECURITY (1 << 17)
#define MC_ERR_STATUS_RW (1 << 16)
#define MC_ERR_STATUS_CLIENT_MASK 0x7f
#define MC_ERR_ADR 0x0c
......@@ -66,6 +65,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
#endif
#ifdef CONFIG_ARCH_TEGRA_132_SOC
{ .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
#endif
#ifdef CONFIG_ARCH_TEGRA_210_SOC
{ .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
#endif
{ }
};
......@@ -283,7 +285,7 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
else
secure = "";
id = value & MC_ERR_STATUS_CLIENT_MASK;
id = value & mc->soc->client_id_mask;
for (i = 0; i < mc->soc->num_clients; i++) {
if (mc->soc->clients[i].id == id) {
......@@ -410,6 +412,8 @@ static int tegra_mc_probe(struct platform_device *pdev)
return err;
}
WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM;
......
drivers/memory/tegra/mc.h
View file @ 10217810
......@@ -41,4 +41,8 @@ extern const struct tegra_mc_soc tegra124_mc_soc;
extern const struct tegra_mc_soc tegra132_mc_soc;
#endif
#ifdef CONFIG_ARCH_TEGRA_210_SOC
extern const struct tegra_mc_soc tegra210_mc_soc;
#endif
#endif /* MEMORY_TEGRA_MC_H */
drivers/memory/tegra/tegra114.c
View file @ 10217810
......@@ -944,5 +944,6 @@ const struct tegra_mc_soc tegra114_mc_soc = {
.num_clients = ARRAY_SIZE(tegra114_mc_clients),
.num_address_bits = 32,
.atom_size = 32,
.client_id_mask = 0x7f,
.smmu = &tegra114_smmu_soc,
};
drivers/memory/tegra/tegra124-emc.c
View file @ 10217810
......@@ -1027,7 +1027,40 @@ static int emc_debug_rate_set(void *data, u64 rate)
DEFINE_SIMPLE_ATTRIBUTE(emc_debug_rate_fops, emc_debug_rate_get,
emc_debug_rate_set, "%lld\n");
static void emc_debugfs_init(struct device *dev)
static int emc_debug_supported_rates_show(struct seq_file *s, void *data)
{
struct tegra_emc *emc = s->private;
const char *prefix = "";
unsigned int i;
for (i = 0; i < emc->num_timings; i++) {
struct emc_timing *timing = &emc->timings[i];
seq_printf(s, "%s%lu", prefix, timing->rate);
prefix = " ";
}
seq_puts(s, "\n");
return 0;
}
static int emc_debug_supported_rates_open(struct inode *inode,
struct file *file)
{
return single_open(file, emc_debug_supported_rates_show,
inode->i_private);
}
static const struct file_operations emc_debug_supported_rates_fops = {
.open = emc_debug_supported_rates_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
{
struct dentry *root, *file;
struct clk *clk;
......@@ -1048,6 +1081,11 @@ static void emc_debugfs_init(struct device *dev)
&emc_debug_rate_fops);
if (!file)
dev_err(dev, "failed to create debugfs entry\n");
file = debugfs_create_file("supported_rates", S_IRUGO, root, emc,
&emc_debug_supported_rates_fops);
if (!file)
dev_err(dev, "failed to create debugfs entry\n");
}
static int tegra_emc_probe(struct platform_device *pdev)
......@@ -1119,7 +1157,7 @@ static int tegra_emc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, emc);
if (IS_ENABLED(CONFIG_DEBUG_FS))
emc_debugfs_init(&pdev->dev);
emc_debugfs_init(&pdev->dev, emc);
return 0;
};
......
drivers/memory/tegra/tegra124.c
View file @ 10217810
......@@ -1032,6 +1032,7 @@ const struct tegra_mc_soc tegra124_mc_soc = {
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
.num_address_bits = 34,
.atom_size = 32,
.client_id_mask = 0x7f,
.smmu = &tegra124_smmu_soc,
.emem_regs = tegra124_mc_emem_regs,
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
......@@ -1067,6 +1068,7 @@ const struct tegra_mc_soc tegra132_mc_soc = {
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
.num_address_bits = 34,
.atom_size = 32,
.client_id_mask = 0x7f,
.smmu = &tegra132_smmu_soc,
};
#endif /* CONFIG_ARCH_TEGRA_132_SOC */
drivers/memory/tegra/tegra210.c 0 → 100644
View file @ 10217810
This diff is collapsed.
drivers/memory/tegra/tegra30.c
View file @ 10217810
......@@ -966,5 +966,6 @@ const struct tegra_mc_soc tegra30_mc_soc = {
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
.num_address_bits = 32,
.atom_size = 16,
.client_id_mask = 0x7f,
.smmu = &tegra30_smmu_soc,
};
drivers/reset/Makefile
View file @ 10217810
obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_ARCH_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
obj-$(CONFIG_ATH79) += reset-ath79.o
drivers/reset/reset-ath79.c 0 → 100644
View file @ 10217810
/*
* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
struct ath79_reset {
struct reset_controller_dev rcdev;
void __iomem *base;
spinlock_t lock;
};
static int ath79_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct ath79_reset *ath79_reset =
container_of(rcdev, struct ath79_reset, rcdev);
unsigned long flags;
u32 val;
spin_lock_irqsave(&ath79_reset->lock, flags);
val = readl(ath79_reset->base);
if (assert)
val |= BIT(id);
else
val &= ~BIT(id);
writel(val, ath79_reset->base);
spin_unlock_irqrestore(&ath79_reset->lock, flags);
return 0;
}
static int ath79_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return ath79_reset_update(rcdev, id, true);
}
static int ath79_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return ath79_reset_update(rcdev, id, false);
}
static int ath79_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct ath79_reset *ath79_reset =
container_of(rcdev, struct ath79_reset, rcdev);
u32 val;
val = readl(ath79_reset->base);
return !!(val & BIT(id));
}
static struct reset_control_ops ath79_reset_ops = {
.assert = ath79_reset_assert,
.deassert = ath79_reset_deassert,
.status = ath79_reset_status,
};
static int ath79_reset_probe(struct platform_device *pdev)
{
struct ath79_reset *ath79_reset;
struct resource *res;
ath79_reset = devm_kzalloc(&pdev->dev,
sizeof(*ath79_reset), GFP_KERNEL);
if (!ath79_reset)
return -ENOMEM;
platform_set_drvdata(pdev, ath79_reset);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ath79_reset->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ath79_reset->base))
return PTR_ERR(ath79_reset->base);
ath79_reset->rcdev.ops = &ath79_reset_ops;
ath79_reset->rcdev.owner = THIS_MODULE;
ath79_reset->rcdev.of_node = pdev->dev.of_node;
ath79_reset->rcdev.of_reset_n_cells = 1;
ath79_reset->rcdev.nr_resets = 32;
return reset_controller_register(&ath79_reset->rcdev);
}
static int ath79_reset_remove(struct platform_device *pdev)
{
struct ath79_reset *ath79_reset = platform_get_drvdata(pdev);
reset_controller_unregister(&ath79_reset->rcdev);
return 0;
}
static const struct of_device_id ath79_reset_dt_ids[] = {
{ .compatible = "qca,ar7100-reset", },
{ },
};
MODULE_DEVICE_TABLE(of, ath79_reset_dt_ids);
static struct platform_driver ath79_reset_driver = {
.probe = ath79_reset_probe,
.remove = ath79_reset_remove,
.driver = {
.name = "ath79-reset",
.of_match_table = ath79_reset_dt_ids,
},
};
module_platform_driver(ath79_reset_driver);
MODULE_AUTHOR("Alban Bedel <albeu@free.fr>");
MODULE_DESCRIPTION("AR71xx Reset Controller Driver");
MODULE_LICENSE("GPL");
drivers/reset/reset-lpc18xx.c 0 → 100644
View file @ 10217810
/*
* Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU).
*
* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
/* LPC18xx RGU registers */
#define LPC18XX_RGU_CTRL0 0x100
#define LPC18XX_RGU_CTRL1 0x104
#define LPC18XX_RGU_ACTIVE_STATUS0 0x150
#define LPC18XX_RGU_ACTIVE_STATUS1 0x154
#define LPC18XX_RGU_RESETS_PER_REG 32
/* Internal reset outputs */
#define LPC18XX_RGU_CORE_RST 0
#define LPC43XX_RGU_M0SUB_RST 12
#define LPC43XX_RGU_M0APP_RST 56
struct lpc18xx_rgu_data {
struct reset_controller_dev rcdev;
struct clk *clk_delay;
struct clk *clk_reg;
void __iomem *base;
spinlock_t lock;
u32 delay_us;
};
#define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev)
static void __iomem *rgu_base;
static int lpc18xx_rgu_restart(struct notifier_block *this, unsigned long mode,
void *cmd)
{
writel(BIT(LPC18XX_RGU_CORE_RST), rgu_base + LPC18XX_RGU_CTRL0);
mdelay(2000);
pr_emerg("%s: unable to restart system\n", __func__);
return NOTIFY_DONE;
}
static struct notifier_block lpc18xx_rgu_restart_nb = {
.notifier_call = lpc18xx_rgu_restart,
.priority = 192,
};
/*
* The LPC18xx RGU has mostly self-deasserting resets except for the
* two reset lines going to the internal Cortex-M0 cores.
*
* To prevent the M0 core resets from accidentally getting deasserted
* status register must be check and bits in control register set to
* preserve the state.
*/
static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev,
unsigned long id, bool set)
{
struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
u32 stat_offset = LPC18XX_RGU_ACTIVE_STATUS0;
u32 ctrl_offset = LPC18XX_RGU_CTRL0;
unsigned long flags;
u32 stat, rst_bit;
stat_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
rst_bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
spin_lock_irqsave(&rc->lock, flags);
stat = ~readl(rc->base + stat_offset);
if (set)
writel(stat | rst_bit, rc->base + ctrl_offset);
else
writel(stat & ~rst_bit, rc->base + ctrl_offset);
spin_unlock_irqrestore(&rc->lock, flags);
return 0;
}
static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return lpc18xx_rgu_setclear_reset(rcdev, id, true);
}
static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return lpc18xx_rgu_setclear_reset(rcdev, id, false);
}
/* Only M0 cores require explicit reset deassert */
static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
lpc18xx_rgu_assert(rcdev, id);
udelay(rc->delay_us);
switch (id) {
case LPC43XX_RGU_M0SUB_RST:
case LPC43XX_RGU_M0APP_RST:
lpc18xx_rgu_setclear_reset(rcdev, id, false);
}
return 0;
}
static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
u32 bit, offset = LPC18XX_RGU_ACTIVE_STATUS0;
offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
return !(readl(rc->base + offset) & bit);
}
static struct reset_control_ops lpc18xx_rgu_ops = {
.reset = lpc18xx_rgu_reset,
.assert = lpc18xx_rgu_assert,
.deassert = lpc18xx_rgu_deassert,
.status = lpc18xx_rgu_status,
};
static int lpc18xx_rgu_probe(struct platform_device *pdev)
{
struct lpc18xx_rgu_data *rc;
struct resource *res;
u32 fcclk, firc;
int ret;
rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
if (!rc)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
rc->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(rc->base))
return PTR_ERR(rc->base);
rc->clk_reg = devm_clk_get(&pdev->dev, "reg");
if (IS_ERR(rc->clk_reg)) {
dev_err(&pdev->dev, "reg clock not found\n");
return PTR_ERR(rc->clk_reg);
}
rc->clk_delay = devm_clk_get(&pdev->dev, "delay");
if (IS_ERR(rc->clk_delay)) {
dev_err(&pdev->dev, "delay clock not found\n");
return PTR_ERR(rc->clk_delay);
}
ret = clk_prepare_enable(rc->clk_reg);
if (ret) {
dev_err(&pdev->dev, "unable to enable reg clock\n");
return ret;
}
ret = clk_prepare_enable(rc->clk_delay);
if (ret) {
dev_err(&pdev->dev, "unable to enable delay clock\n");
goto dis_clk_reg;
}
fcclk = clk_get_rate(rc->clk_reg) / USEC_PER_SEC;
firc = clk_get_rate(rc->clk_delay) / USEC_PER_SEC;
if (fcclk == 0 || firc == 0)
rc->delay_us = 2;
else
rc->delay_us = DIV_ROUND_UP(fcclk, firc * firc);
spin_lock_init(&rc->lock);
rc->rcdev.owner = THIS_MODULE;
rc->rcdev.nr_resets = 64;
rc->rcdev.ops = &lpc18xx_rgu_ops;
rc->rcdev.of_node = pdev->dev.of_node;
platform_set_drvdata(pdev, rc);
ret = reset_controller_register(&rc->rcdev);
if (ret) {
dev_err(&pdev->dev, "unable to register device\n");
goto dis_clks;
}
rgu_base = rc->base;
ret = register_restart_handler(&lpc18xx_rgu_restart_nb);
if (ret)
dev_warn(&pdev->dev, "failed to register restart handler\n");
return 0;
dis_clks:
clk_disable_unprepare(rc->clk_delay);
dis_clk_reg:
clk_disable_unprepare(rc->clk_reg);
return ret;
}
static int lpc18xx_rgu_remove(struct platform_device *pdev)
{
struct lpc18xx_rgu_data *rc = platform_get_drvdata(pdev);
int ret;
ret = unregister_restart_handler(&lpc18xx_rgu_restart_nb);
if (ret)
dev_warn(&pdev->dev, "failed to unregister restart handler\n");
reset_controller_unregister(&rc->rcdev);
clk_disable_unprepare(rc->clk_delay);
clk_disable_unprepare(rc->clk_reg);
return 0;
}
static const struct of_device_id lpc18xx_rgu_match[] = {
{ .compatible = "nxp,lpc1850-rgu" },
{ }
};
MODULE_DEVICE_TABLE(of, lpc18xx_rgu_match);
static struct platform_driver lpc18xx_rgu_driver = {
.probe = lpc18xx_rgu_probe,
.remove = lpc18xx_rgu_remove,
.driver = {
.name = "lpc18xx-reset",
.of_match_table = lpc18xx_rgu_match,
},
};
module_platform_driver(lpc18xx_rgu_driver);
MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
MODULE_DESCRIPTION("Reset driver for LPC18xx/43xx RGU");
MODULE_LICENSE("GPL v2");
drivers/reset/reset-socfpga.c
View file @ 10217810
......@@ -24,11 +24,11 @@
#include <linux/types.h>
#define NR_BANKS 4
#define OFFSET_MODRST 0x10
struct socfpga_reset_data {
spinlock_t lock;
void __iomem *membase;
u32 modrst_offset;
struct reset_controller_dev rcdev;
};
......@@ -45,8 +45,8 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
spin_lock_irqsave(&data->lock, flags);
reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
writel(reg | BIT(offset), data->membase + OFFSET_MODRST +
reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
writel(reg | BIT(offset), data->membase + data->modrst_offset +
(bank * NR_BANKS));
spin_unlock_irqrestore(&data->lock, flags);
......@@ -67,8 +67,8 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
spin_lock_irqsave(&data->lock, flags);
reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
writel(reg & ~BIT(offset), data->membase + OFFSET_MODRST +
reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
(bank * NR_BANKS));
spin_unlock_irqrestore(&data->lock, flags);
......@@ -85,7 +85,7 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
int offset = id % BITS_PER_LONG;
u32 reg;
reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
return !(reg & BIT(offset));
}
......@@ -100,6 +100,8 @@ static int socfpga_reset_probe(struct platform_device *pdev)
{
struct socfpga_reset_data *data;
struct resource *res;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
/*
* The binding was mainlined without the required property.
......@@ -120,6 +122,11 @@ static int socfpga_reset_probe(struct platform_device *pdev)
if (IS_ERR(data->membase))
return PTR_ERR(data->membase);
if (of_property_read_u32(np, "altr,modrst-offset", &data->modrst_offset)) {
dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
data->modrst_offset = 0x10;
}
spin_lock_init(&data->lock);
data->rcdev.owner = THIS_MODULE;
......
drivers/reset/reset-zynq.c 0 → 100644
View file @ 10217810
/*
* Copyright (c) 2015, National Instruments Corp.
*
* Xilinx Zynq Reset controller driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/regmap.h>
#include <linux/types.h>
struct zynq_reset_data {
struct regmap *slcr;
struct reset_controller_dev rcdev;
u32 offset;
};
#define to_zynq_reset_data(p) \
container_of((p), struct zynq_reset_data, rcdev)
static int zynq_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
int bank = id / BITS_PER_LONG;
int offset = id % BITS_PER_LONG;
pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
bank, offset);
return regmap_update_bits(priv->slcr,
priv->offset + (bank * 4),
BIT(offset),
BIT(offset));
}
static int zynq_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
int bank = id / BITS_PER_LONG;
int offset = id % BITS_PER_LONG;
pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
bank, offset);
return regmap_update_bits(priv->slcr,
priv->offset + (bank * 4),
BIT(offset),
~BIT(offset));
}
static int zynq_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct zynq_reset_data *priv = to_zynq_reset_data(rcdev);
int bank = id / BITS_PER_LONG;
int offset = id % BITS_PER_LONG;
int ret;
u32 reg;
pr_debug("%s: %s reset bank %u offset %u\n", KBUILD_MODNAME, __func__,
bank, offset);
ret = regmap_read(priv->slcr, priv->offset + (bank * 4), &reg);
if (ret)
return ret;
return !!(reg & BIT(offset));
}
static struct reset_control_ops zynq_reset_ops = {
.assert = zynq_reset_assert,
.deassert = zynq_reset_deassert,
.status = zynq_reset_status,
};
static int zynq_reset_probe(struct platform_device *pdev)
{
struct resource *res;
struct zynq_reset_data *priv;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"syscon");
if (IS_ERR(priv->slcr)) {
dev_err(&pdev->dev, "unable to get zynq-slcr regmap");
return PTR_ERR(priv->slcr);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "missing IO resource\n");
return -ENODEV;
}
priv->offset = res->start;
priv->rcdev.owner = THIS_MODULE;
priv->rcdev.nr_resets = resource_size(res) / 4 * BITS_PER_LONG;
priv->rcdev.ops = &zynq_reset_ops;
priv->rcdev.of_node = pdev->dev.of_node;
reset_controller_register(&priv->rcdev);
return 0;
}
static int zynq_reset_remove(struct platform_device *pdev)
{
struct zynq_reset_data *priv = platform_get_drvdata(pdev);
reset_controller_unregister(&priv->rcdev);
return 0;
}
static const struct of_device_id zynq_reset_dt_ids[] = {
{ .compatible = "xlnx,zynq-reset", },
{ /* sentinel */ },
};
static struct platform_driver zynq_reset_driver = {
.probe = zynq_reset_probe,
.remove = zynq_reset_remove,
.driver = {
.name = KBUILD_MODNAME,
.of_match_table = zynq_reset_dt_ids,
},
};
module_platform_driver(zynq_reset_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
MODULE_DESCRIPTION("Zynq Reset Controller Driver");
drivers/reset/sti/reset-stih407.c
View file @ 10217810
......@@ -11,7 +11,7 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <dt-bindings/reset-controller/stih407-resets.h>
#include <dt-bindings/reset/stih407-resets.h>
#include "reset-syscfg.h"
/* STiH407 Peripheral powerdown definitions. */
......@@ -126,7 +126,7 @@ static const struct syscfg_reset_controller_data stih407_picophyreset_controller
.channels = stih407_picophyresets,
};
static struct of_device_id stih407_reset_match[] = {
static const struct of_device_id stih407_reset_match[] = {
{
.compatible = "st,stih407-powerdown",
.data = &stih407_powerdown_controller,
......
drivers/reset/sti/reset-stih415.c
View file @ 10217810
......@@ -13,7 +13,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <dt-bindings/reset-controller/stih415-resets.h>
#include <dt-bindings/reset/stih415-resets.h>
#include "reset-syscfg.h"
......@@ -89,7 +89,7 @@ static struct syscfg_reset_controller_data stih415_softreset_controller = {
.channels = stih415_softresets,
};
static struct of_device_id stih415_reset_match[] = {
static const struct of_device_id stih415_reset_match[] = {
{ .compatible = "st,stih415-powerdown",
.data = &stih415_powerdown_controller, },
{ .compatible = "st,stih415-softreset",
......
drivers/reset/sti/reset-stih416.c
View file @ 10217810
......@@ -13,7 +13,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <dt-bindings/reset-controller/stih416-resets.h>
#include <dt-bindings/reset/stih416-resets.h>
#include "reset-syscfg.h"
......@@ -120,7 +120,7 @@ static struct syscfg_reset_controller_data stih416_softreset_controller = {
.channels = stih416_softresets,
};
static struct of_device_id stih416_reset_match[] = {
static const struct of_device_id stih416_reset_match[] = {
{ .compatible = "st,stih416-powerdown",
.data = &stih416_powerdown_controller, },
{ .compatible = "st,stih416-softreset",
......
drivers/soc/Makefile
View file @ 10217810
......@@ -2,6 +2,7 @@
# Makefile for the Linux Kernel SOC specific device drivers.
#
obj-$(CONFIG_MACH_DOVE) += dove/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
......
drivers/soc/dove/pmu.c 0 → 100644
View file @ 10217810
This diff is collapsed.
drivers/soc/qcom/Kconfig
View file @ 10217810
......@@ -13,7 +13,38 @@ config QCOM_GSBI
config QCOM_PM
bool "Qualcomm Power Management"
depends on ARCH_QCOM && !ARM64
select QCOM_SCM
help
QCOM Platform specific power driver to manage cores and L2 low power
modes. It interface with various system drivers to put the cores in
low power modes.
config QCOM_SMD
tristate "Qualcomm Shared Memory Driver (SMD)"
depends on QCOM_SMEM
help
Say y here to enable support for the Qualcomm Shared Memory Driver
providing communication channels to remote processors in Qualcomm
platforms.
config QCOM_SMD_RPM
tristate "Qualcomm Resource Power Manager (RPM) over SMD"
depends on QCOM_SMD && OF
help
If you say yes to this option, support will be included for the
Resource Power Manager system found in the Qualcomm 8974 based
devices.
This is required to access many regulators, clocks and bus
frequencies controlled by the RPM on these devices.
Say M here if you want to include support for the Qualcomm RPM as a
module. This will build a module called "qcom-smd-rpm".
config QCOM_SMEM
tristate "Qualcomm Shared Memory Manager (SMEM)"
depends on ARCH_QCOM
help
Say y here to enable support for the Qualcomm Shared Memory Manager.
The driver provides an interface to items in a heap shared among all
processors in a Qualcomm platform.
drivers/soc/qcom/Makefile
View file @ 10217810
obj-$(CONFIG_QCOM_GSBI) += qcom_gsbi.o
obj-$(CONFIG_QCOM_PM) += spm.o
obj-$(CONFIG_QCOM_SMD) += smd.o
obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
obj-$(CONFIG_QCOM_SMEM) += smem.o
drivers/soc/qcom/smd-rpm.c 0 → 100644
View file @ 10217810
/*
* Copyright (c) 2015, Sony Mobile Communications AB.
* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/soc/qcom/smd.h>
#include <linux/soc/qcom/smd-rpm.h>
#define RPM_REQUEST_TIMEOUT (5 * HZ)
/**
* struct qcom_smd_rpm - state of the rpm device driver
* @rpm_channel: reference to the smd channel
* @ack: completion for acks
* @lock: mutual exclusion around the send/complete pair
* @ack_status: result of the rpm request
*/
struct qcom_smd_rpm {
struct qcom_smd_channel *rpm_channel;
struct completion ack;
struct mutex lock;
int ack_status;
};
/**
* struct qcom_rpm_header - header for all rpm requests and responses
* @service_type: identifier of the service
* @length: length of the payload
*/
struct qcom_rpm_header {
u32 service_type;
u32 length;
};
/**
* struct qcom_rpm_request - request message to the rpm
* @msg_id: identifier of the outgoing message
* @flags: active/sleep state flags
* @type: resource type
* @id: resource id
* @data_len: length of the payload following this header
*/
struct qcom_rpm_request {
u32 msg_id;
u32 flags;
u32 type;
u32 id;
u32 data_len;
};
/**
* struct qcom_rpm_message - response message from the rpm
* @msg_type: indicator of the type of message
* @length: the size of this message, including the message header
* @msg_id: message id
* @message: textual message from the rpm
*
* Multiple of these messages can be stacked in an rpm message.
*/
struct qcom_rpm_message {
u32 msg_type;
u32 length;
union {
u32 msg_id;
u8 message[0];
};
};
#define RPM_SERVICE_TYPE_REQUEST 0x00716572 /* "req\0" */
#define RPM_MSG_TYPE_ERR 0x00727265 /* "err\0" */
#define RPM_MSG_TYPE_MSG_ID 0x2367736d /* "msg#" */
/**
* qcom_rpm_smd_write - write @buf to @type:@id
* @rpm: rpm handle
* @type: resource type
* @id: resource identifier
* @buf: the data to be written
* @count: number of bytes in @buf
*/
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
int state,
u32 type, u32 id,
void *buf,
size_t count)
{
static unsigned msg_id = 1;
int left;
int ret;
struct {
struct qcom_rpm_header hdr;
struct qcom_rpm_request req;
u8 payload[count];
} pkt;
/* SMD packets to the RPM may not exceed 256 bytes */
if (WARN_ON(sizeof(pkt) >= 256))
return -EINVAL;
mutex_lock(&rpm->lock);
pkt.hdr.service_type = RPM_SERVICE_TYPE_REQUEST;
pkt.hdr.length = sizeof(struct qcom_rpm_request) + count;
pkt.req.msg_id = msg_id++;
pkt.req.flags = BIT(state);
pkt.req.type = type;
pkt.req.id = id;
pkt.req.data_len = count;
memcpy(pkt.payload, buf, count);
ret = qcom_smd_send(rpm->rpm_channel, &pkt, sizeof(pkt));
if (ret)
goto out;
left = wait_for_completion_timeout(&rpm->ack, RPM_REQUEST_TIMEOUT);
if (!left)
ret = -ETIMEDOUT;
else
ret = rpm->ack_status;
out:
mutex_unlock(&rpm->lock);
return ret;
}
EXPORT_SYMBOL(qcom_rpm_smd_write);
static int qcom_smd_rpm_callback(struct qcom_smd_device *qsdev,
const void *data,
size_t count)
{
const struct qcom_rpm_header *hdr = data;
const struct qcom_rpm_message *msg;
struct qcom_smd_rpm *rpm = dev_get_drvdata(&qsdev->dev);
const u8 *buf = data + sizeof(struct qcom_rpm_header);
const u8 *end = buf + hdr->length;
char msgbuf[32];
int status = 0;
u32 len;
if (hdr->service_type != RPM_SERVICE_TYPE_REQUEST ||
hdr->length < sizeof(struct qcom_rpm_message)) {
dev_err(&qsdev->dev, "invalid request\n");
return 0;
}
while (buf < end) {
msg = (struct qcom_rpm_message *)buf;
switch (msg->msg_type) {
case RPM_MSG_TYPE_MSG_ID:
break;
case RPM_MSG_TYPE_ERR:
len = min_t(u32, ALIGN(msg->length, 4), sizeof(msgbuf));
memcpy_fromio(msgbuf, msg->message, len);
msgbuf[len - 1] = 0;
if (!strcmp(msgbuf, "resource does not exist"))
status = -ENXIO;
else
status = -EINVAL;
break;
}
buf = PTR_ALIGN(buf + 2 * sizeof(u32) + msg->length, 4);
}
rpm->ack_status = status;
complete(&rpm->ack);
return 0;
}
static int qcom_smd_rpm_probe(struct qcom_smd_device *sdev)
{
struct qcom_smd_rpm *rpm;
rpm = devm_kzalloc(&sdev->dev, sizeof(*rpm), GFP_KERNEL);
if (!rpm)
return -ENOMEM;
mutex_init(&rpm->lock);
init_completion(&rpm->ack);
rpm->rpm_channel = sdev->channel;
dev_set_drvdata(&sdev->dev, rpm);
return of_platform_populate(sdev->dev.of_node, NULL, NULL, &sdev->dev);
}
static void qcom_smd_rpm_remove(struct qcom_smd_device *sdev)
{
of_platform_depopulate(&sdev->dev);
}
static const struct of_device_id qcom_smd_rpm_of_match[] = {
{ .compatible = "qcom,rpm-msm8974" },
{}
};
MODULE_DEVICE_TABLE(of, qcom_smd_rpm_of_match);
static struct qcom_smd_driver qcom_smd_rpm_driver = {
.probe = qcom_smd_rpm_probe,
.remove = qcom_smd_rpm_remove,
.callback = qcom_smd_rpm_callback,
.driver = {
.name = "qcom_smd_rpm",
.owner = THIS_MODULE,
.of_match_table = qcom_smd_rpm_of_match,
},
};
static int __init qcom_smd_rpm_init(void)
{
return qcom_smd_driver_register(&qcom_smd_rpm_driver);
}
arch_initcall(qcom_smd_rpm_init);
static void __exit qcom_smd_rpm_exit(void)
{
qcom_smd_driver_unregister(&qcom_smd_rpm_driver);
}
module_exit(qcom_smd_rpm_exit);
MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
MODULE_DESCRIPTION("Qualcomm SMD backed RPM driver");
MODULE_LICENSE("GPL v2");
drivers/soc/qcom/smd.c 0 → 100644
View file @ 10217810
This diff is collapsed.
drivers/soc/qcom/smem.c 0 → 100644
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/Makefile
View file @ 10217810
obj-$(CONFIG_ARCH_TEGRA) += fuse/
obj-y += fuse/
obj-$(CONFIG_ARCH_TEGRA) += common.o
obj-$(CONFIG_ARCH_TEGRA) += pmc.o
obj-y += common.o
obj-y += pmc.o
drivers/soc/tegra/common.c
View file @ 10217810
......@@ -15,6 +15,8 @@ static const struct of_device_id tegra_machine_match[] = {
{ .compatible = "nvidia,tegra30", },
{ .compatible = "nvidia,tegra114", },
{ .compatible = "nvidia,tegra124", },
{ .compatible = "nvidia,tegra132", },
{ .compatible = "nvidia,tegra210", },
{ }
};
......
drivers/soc/tegra/fuse/Makefile
View file @ 10217810
......@@ -6,3 +6,5 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += speedo-tegra20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += speedo-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += speedo-tegra114.o
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += speedo-tegra124.o
obj-$(CONFIG_ARCH_TEGRA_132_SOC) += speedo-tegra124.o
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += speedo-tegra210.o
drivers/soc/tegra/fuse/fuse-tegra.c
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/fuse-tegra20.c
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/fuse-tegra30.c
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/fuse.h
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/speedo-tegra114.c
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/speedo-tegra124.c
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/speedo-tegra20.c
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/speedo-tegra210.c 0 → 100644
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/speedo-tegra30.c
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/fuse/tegra-apbmisc.c
View file @ 10217810
This diff is collapsed.
drivers/soc/tegra/pmc.c
View file @ 10217810
This diff is collapsed.
include/dt-bindings/memory/tegra210-mc.h 0 → 100644
View file @ 10217810
This diff is collapsed.
include/linux/clk/shmobile.h
View file @ 10217810
This diff is collapsed.
include/linux/soc/dove/pmu.h 0 → 100644
View file @ 10217810
#ifndef LINUX_SOC_DOVE_PMU_H
#define LINUX_SOC_DOVE_PMU_H
int dove_init_pmu(void);
#endif
include/linux/soc/qcom/smd-rpm.h 0 → 100644
View file @ 10217810
This diff is collapsed.
include/linux/soc/qcom/smd.h 0 → 100644
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include/linux/soc/qcom/smem.h 0 → 100644
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include/soc/tegra/fuse.h
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include/soc/tegra/mc.h
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......@@ -102,6 +102,8 @@ struct tegra_mc_soc {
unsigned int num_address_bits;
unsigned int atom_size;
u8 client_id_mask;
const struct tegra_smmu_soc *smmu;
};
......
include/soc/tegra/pmc.h
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