Commit 11144283 authored by Michael Turquette's avatar Michael Turquette

Merge tag 'for-v3.20-exynos7-clk' of git://linuxtv.org/snawrocki/samsung into clk-next

- Clock definitions for Exynos7 SoC peripheral devices:
  video scaler, USB, DMA, SPI and the audio subsystem.
parents 1a34275d 9f930a39
......@@ -34,6 +34,8 @@ Required Properties for Clock Controller:
- "samsung,exynos7-clock-peris"
- "samsung,exynos7-clock-fsys0"
- "samsung,exynos7-clock-fsys1"
- "samsung,exynos7-clock-mscl"
- "samsung,exynos7-clock-aud"
- reg: physical base address of the controller and the length of
memory mapped region.
......@@ -53,6 +55,7 @@ Input clocks for top0 clock controller:
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
- dout_sclk_aud_pll
Input clocks for top1 clock controller:
- fin_pll
......@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller:
- sclk_uart1
- sclk_uart2
- sclk_uart3
- sclk_spi0
- sclk_spi1
- sclk_spi2
- sclk_spi3
- sclk_spi4
- sclk_i2s1
- sclk_pcm1
- sclk_spdif
Input clocks for peris clock controller:
- fin_pll
......@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller:
- dout_aclk_fsys1_200
- dout_sclk_mmc0
- dout_sclk_mmc1
Input clocks for aud clock controller:
- fin_pll
- fout_aud_pll
This diff is collapsed.
......@@ -17,7 +17,11 @@
#define DOUT_SCLK_CC_PLL 4
#define DOUT_SCLK_MFC_PLL 5
#define DOUT_ACLK_CCORE_133 6
#define TOPC_NR_CLK 7
#define DOUT_ACLK_MSCL_532 7
#define ACLK_MSCL_532 8
#define DOUT_SCLK_AUD_PLL 9
#define FOUT_AUD_PLL 10
#define TOPC_NR_CLK 11
/* TOP0 */
#define DOUT_ACLK_PERIC1 1
......@@ -26,7 +30,15 @@
#define CLK_SCLK_UART1 4
#define CLK_SCLK_UART2 5
#define CLK_SCLK_UART3 6
#define TOP0_NR_CLK 7
#define CLK_SCLK_SPI0 7
#define CLK_SCLK_SPI1 8
#define CLK_SCLK_SPI2 9
#define CLK_SCLK_SPI3 10
#define CLK_SCLK_SPI4 11
#define CLK_SCLK_SPDIF 12
#define CLK_SCLK_PCM1 13
#define CLK_SCLK_I2S1 14
#define TOP0_NR_CLK 15
/* TOP1 */
#define DOUT_ACLK_FSYS1_200 1
......@@ -70,7 +82,23 @@
#define PCLK_HSI2C6 9
#define PCLK_HSI2C7 10
#define PCLK_HSI2C8 11
#define PERIC1_NR_CLK 12
#define PCLK_SPI0 12
#define PCLK_SPI1 13
#define PCLK_SPI2 14
#define PCLK_SPI3 15
#define PCLK_SPI4 16
#define SCLK_SPI0 17
#define SCLK_SPI1 18
#define SCLK_SPI2 19
#define SCLK_SPI3 20
#define SCLK_SPI4 21
#define PCLK_I2S1 22
#define PCLK_PCM1 23
#define PCLK_SPDIF 24
#define SCLK_I2S1 25
#define SCLK_PCM1 26
#define SCLK_SPDIF 27
#define PERIC1_NR_CLK 28
/* PERIS */
#define PCLK_CHIPID 1
......@@ -82,11 +110,63 @@
/* FSYS0 */
#define ACLK_MMC2 1
#define FSYS0_NR_CLK 2
#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
#define ACLK_USBDRD300 3
#define SCLK_USBDRD300_SUSPENDCLK 4
#define SCLK_USBDRD300_REFCLK 5
#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
#define ACLK_PDMA0 9
#define ACLK_PDMA1 10
#define FSYS0_NR_CLK 11
/* FSYS1 */
#define ACLK_MMC1 1
#define ACLK_MMC0 2
#define FSYS1_NR_CLK 3
/* MSCL */
#define USERMUX_ACLK_MSCL_532 1
#define DOUT_PCLK_MSCL 2
#define ACLK_MSCL_0 3
#define ACLK_MSCL_1 4
#define ACLK_JPEG 5
#define ACLK_G2D 6
#define ACLK_LH_ASYNC_SI_MSCL_0 7
#define ACLK_LH_ASYNC_SI_MSCL_1 8
#define ACLK_AXI2ACEL_BRIDGE 9
#define ACLK_XIU_MSCLX_0 10
#define ACLK_XIU_MSCLX_1 11
#define ACLK_QE_MSCL_0 12
#define ACLK_QE_MSCL_1 13
#define ACLK_QE_JPEG 14
#define ACLK_QE_G2D 15
#define ACLK_PPMU_MSCL_0 16
#define ACLK_PPMU_MSCL_1 17
#define ACLK_MSCLNP_133 18
#define ACLK_AHB2APB_MSCL0P 19
#define ACLK_AHB2APB_MSCL1P 20
#define PCLK_MSCL_0 21
#define PCLK_MSCL_1 22
#define PCLK_JPEG 23
#define PCLK_G2D 24
#define PCLK_QE_MSCL_0 25
#define PCLK_QE_MSCL_1 26
#define PCLK_QE_JPEG 27
#define PCLK_QE_G2D 28
#define PCLK_PPMU_MSCL_0 29
#define PCLK_PPMU_MSCL_1 30
#define PCLK_AXI2ACEL_BRIDGE 31
#define PCLK_PMU_MSCL 32
#define MSCL_NR_CLK 33
/* AUD */
#define SCLK_I2S 1
#define SCLK_PCM 2
#define PCLK_I2S 3
#define PCLK_PCM 4
#define ACLK_ADMA 5
#define AUD_NR_CLK 6
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
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