Commit 12ccb661 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King

[ARM PATCH] 2312/1: Cache type information fix

Patch from Catalin Marinas

The CType field in the cache type CP15 register does not always
specify whether the cache is VIVT or VIPT. The dump_cpu_info()
function should use the cache_is_(vivt|vipt) macros instead.

Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
parent ff667a48
......@@ -132,21 +132,21 @@ static struct resource io_res[] = {
#define lp2 io_res[2]
static const char *cache_types[16] = {
"VIVT write-through",
"VIVT write-back",
"VIVT write-back",
"write-through",
"write-back",
"write-back",
"undefined 3",
"undefined 4",
"undefined 5",
"VIVT write-back",
"VIVT write-back",
"write-back",
"write-back",
"undefined 8",
"undefined 9",
"undefined 10",
"undefined 11",
"undefined 12",
"undefined 13",
"VIPT write-back",
"write-back",
"undefined 15",
};
......@@ -236,7 +236,8 @@ static void __init dump_cpu_info(void)
unsigned int info = read_cpuid(CPUID_CACHETYPE);
if (info != processor_id) {
printk("CPU: D %s cache\n", cache_types[CACHE_TYPE(info)]);
printk("CPU: D %s %s cache\n", cache_is_vivt() ? "VIVT" : "VIPT",
cache_types[CACHE_TYPE(info)]);
if (CACHE_S(info)) {
dump_cache("CPU: I cache", CACHE_ISIZE(info));
dump_cache("CPU: D cache", CACHE_DSIZE(info));
......
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