Commit 131a10a3 authored by Philip Avinash's avatar Philip Avinash Committed by Sekhar Nori

gpio: davinci: coding style correction

Make some minor coding style fixes. Use proper multi-line
commenting style, and use a macro for register offset.
Signed-off-by: default avatarPhilip Avinash <avinashphilip@ti.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarLad, Prabhakar <prabhakar.csengg@gmail.com>
[nsekhar@ti.com: drop changes which are considered
		 unnecessary churn - line break fixes
		 variable name changes and include file
		 reordering]
Signed-off-by: default avatarSekhar Nori <nsekhar@ti.com>
parent 4a10c2ac
...@@ -31,6 +31,8 @@ struct davinci_gpio_regs { ...@@ -31,6 +31,8 @@ struct davinci_gpio_regs {
u32 intstat; u32 intstat;
}; };
#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
#define chip2controller(chip) \ #define chip2controller(chip) \
container_of(chip, struct davinci_gpio_controller, chip) container_of(chip, struct davinci_gpio_controller, chip)
...@@ -304,7 +306,8 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) ...@@ -304,7 +306,8 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{ {
struct davinci_soc_info *soc_info = &davinci_soc_info; struct davinci_soc_info *soc_info = &davinci_soc_info;
/* NOTE: we assume for now that only irqs in the first gpio_chip /*
* NOTE: we assume for now that only irqs in the first gpio_chip
* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
*/ */
if (offset < soc_info->gpio_unbanked) if (offset < soc_info->gpio_unbanked)
...@@ -368,7 +371,8 @@ static int __init davinci_gpio_irq_setup(void) ...@@ -368,7 +371,8 @@ static int __init davinci_gpio_irq_setup(void)
} }
clk_prepare_enable(clk); clk_prepare_enable(clk);
/* Arrange gpio_to_irq() support, handling either direct IRQs or /*
* Arrange gpio_to_irq() support, handling either direct IRQs or
* banked IRQs. Having GPIOs in the first GPIO bank use direct * banked IRQs. Having GPIOs in the first GPIO bank use direct
* IRQs, while the others use banked IRQs, would need some setup * IRQs, while the others use banked IRQs, would need some setup
* tweaks to recognize hardware which can do that. * tweaks to recognize hardware which can do that.
...@@ -450,10 +454,11 @@ static int __init davinci_gpio_irq_setup(void) ...@@ -450,10 +454,11 @@ static int __init davinci_gpio_irq_setup(void)
} }
done: done:
/* BINTEN -- per-bank interrupt enable. genirq would also let these /*
* BINTEN -- per-bank interrupt enable. genirq would also let these
* bits be set/cleared dynamically. * bits be set/cleared dynamically.
*/ */
__raw_writel(binten, gpio_base + 0x08); __raw_writel(binten, gpio_base + BINTEN);
printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
......
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