Commit 1368645e authored by Paul Mackerras's avatar Paul Mackerras

Merge samba.org:/home/paulus/kernel/linux-2.5

into samba.org:/home/paulus/kernel/for-linus-ppc
parents 980060bb 1678e2b1
...@@ -86,10 +86,6 @@ ...@@ -86,10 +86,6 @@
/* Special Purpose Registers (SPRNs)*/ /* Special Purpose Registers (SPRNs)*/
#define SPRN_CTR 0x009 /* Count Register */ #define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
#if !defined(SPRN_DAC1) && !defined(SPRN_DAC2)
#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
#endif
#define SPRN_DAR 0x013 /* Data Address Register */ #define SPRN_DAR 0x013 /* Data Address Register */
#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
...@@ -290,8 +286,6 @@ ...@@ -290,8 +286,6 @@
#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
/* these bits were defined in inverted endian sense originally, ugh, confusing */ /* these bits were defined in inverted endian sense originally, ugh, confusing */
#define THRM1_TIN (1 << 31) #define THRM1_TIN (1 << 31)
......
...@@ -128,8 +128,12 @@ do { \ ...@@ -128,8 +128,12 @@ do { \
#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
#define SPRN_TSR 0x3D8 /* Timer Status Register */ #define SPRN_TSR 0x3D8 /* Timer Status Register */
#define SPRN_TCR 0x3DA /* Timer Control Register */ #define SPRN_TCR 0x3DA /* Timer Control Register */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#define SPRN_DBSR 0x3F0 /* Debug Status Register */ #define SPRN_DBSR 0x3F0 /* Debug Status Register */
#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
#endif #endif
/* Bit definitions for the DBSR. */ /* Bit definitions for the DBSR. */
......
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