Commit 15ce104c authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher

drm/amd/display: Disable PG on NV12

[Why]
HW team request to disable PG on NV12 (fixing missed cases)

[How]
Disable dpp and hubp PG
Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 891f016d
...@@ -4053,8 +4053,12 @@ static bool dcn20_resource_construct( ...@@ -4053,8 +4053,12 @@ static bool dcn20_resource_construct(
// to be consumed. We could have created dcn20_init_hw to get // to be consumed. We could have created dcn20_init_hw to get
// the same effect by checking ASIC rev, but there was a // the same effect by checking ASIC rev, but there was a
// request at some point to not check ASIC rev on hw sequencer. // request at some point to not check ASIC rev on hw sequencer.
if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
dc->hwseq->funcs.enable_power_gating_plane = NULL; dc->hwseq->funcs.enable_power_gating_plane = NULL;
dc->debug.disable_dpp_power_gate = true;
dc->debug.disable_hubp_power_gate = true;
}
dc->caps.max_planes = pool->base.pipe_count; dc->caps.max_planes = pool->base.pipe_count;
......
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