Commit 17304383 authored by Brian Gerst's avatar Brian Gerst Committed by Linus Torvalds

i386: fix PGE mask

cr4 is a 32-bit register, so casting the mask to an unsigned char is wrong,
as it clears more than the PGE bit.
Signed-off-by: default avatarBrian Gerst <bgerst@didntduck.org>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent d0aff6e6
...@@ -136,7 +136,7 @@ static void prepare_set(void) ...@@ -136,7 +136,7 @@ static void prepare_set(void)
/* Save value of CR4 and clear Page Global Enable (bit 7) */ /* Save value of CR4 and clear Page Global Enable (bit 7) */
if ( cpu_has_pge ) { if ( cpu_has_pge ) {
cr4 = read_cr4(); cr4 = read_cr4();
write_cr4(cr4 & (unsigned char) ~(1 << 7)); write_cr4(cr4 & ~X86_CR4_PGE);
} }
/* Disable and flush caches. Note that wbinvd flushes the TLBs as /* Disable and flush caches. Note that wbinvd flushes the TLBs as
......
...@@ -19,7 +19,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) ...@@ -19,7 +19,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
/* Save value of CR4 and clear Page Global Enable (bit 7) */ /* Save value of CR4 and clear Page Global Enable (bit 7) */
if ( cpu_has_pge ) { if ( cpu_has_pge ) {
ctxt->cr4val = read_cr4(); ctxt->cr4val = read_cr4();
write_cr4(ctxt->cr4val & (unsigned char) ~(1 << 7)); write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
} }
/* Disable and flush caches. Note that wbinvd flushes the TLBs as /* Disable and flush caches. Note that wbinvd flushes the TLBs as
......
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