Commit 186bbc72 authored by Russell King's avatar Russell King

[ARM] Remove adrsvc macro.

The adrsvc macro was used to allow the entry-* files to be built on
ARM32 and ARM26 processors.  Since we no longer support ARM26 CPUs,
eliminate this macro.
parent 87976c04
...@@ -141,7 +141,7 @@ __irq_svc: ...@@ -141,7 +141,7 @@ __irq_svc:
@ @
@ routine called with r0 = irq number, r1 = struct pt_regs * @ routine called with r0 = irq number, r1 = struct pt_regs *
@ @
adrsvc ne, lr, 1b adrne lr, 1b
bne asm_do_IRQ bne asm_do_IRQ
#ifdef CONFIG_PREEMPT #ifdef CONFIG_PREEMPT
ldr r0, [r8, #TI_FLAGS] @ get flags ldr r0, [r8, #TI_FLAGS] @ get flags
...@@ -191,7 +191,7 @@ __und_svc: ...@@ -191,7 +191,7 @@ __und_svc:
@ r0 - instruction @ r0 - instruction
@ @
ldr r0, [r2, #-4] ldr r0, [r2, #-4]
adrsvc al, r9, 1f adr r9, 1f
bl call_fpe bl call_fpe
mov r0, sp @ struct pt_regs *regs mov r0, sp @ struct pt_regs *regs
...@@ -312,7 +312,7 @@ __dabt_usr: ...@@ -312,7 +312,7 @@ __dabt_usr:
@ @
enable_irq r2 enable_irq r2
mov r2, sp mov r2, sp
adrsvc al, lr, ret_from_exception adr lr, ret_from_exception
b do_DataAbort b do_DataAbort
.align 5 .align 5
...@@ -328,7 +328,7 @@ __irq_usr: ...@@ -328,7 +328,7 @@ __irq_usr:
#endif #endif
1: get_irqnr_and_base r0, r6, r5, lr 1: get_irqnr_and_base r0, r6, r5, lr
movne r1, sp movne r1, sp
adrsvc ne, lr, 1b adrne lr, 1b
@ @
@ routine called with r0 = irq number, r1 = struct pt_regs * @ routine called with r0 = irq number, r1 = struct pt_regs *
@ @
...@@ -364,8 +364,8 @@ __und_usr: ...@@ -364,8 +364,8 @@ __und_usr:
@ r0 - instruction @ r0 - instruction
@ @
1: ldrt r0, [r4] 1: ldrt r0, [r4]
adrsvc al, r9, ret_from_exception adr r9, ret_from_exception
adrsvc al, lr, fpundefinstr adr lr, fpundefinstr
@ @
@ fallthrough to call_fpe @ fallthrough to call_fpe
@ @
...@@ -462,7 +462,7 @@ ENTRY(fp_enter) ...@@ -462,7 +462,7 @@ ENTRY(fp_enter)
fpundefinstr: fpundefinstr:
mov r0, sp mov r0, sp
adrsvc al, lr, ret_from_exception adr lr, ret_from_exception
b do_undefinstr b do_undefinstr
.align 5 .align 5
......
...@@ -137,7 +137,7 @@ ENTRY(vector_swi) ...@@ -137,7 +137,7 @@ ENTRY(vector_swi)
tst ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? tst ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
bne __sys_trace bne __sys_trace
adrsvc al, lr, ret_fast_syscall @ return address adr lr, ret_fast_syscall @ return address
cmp scno, #NR_syscalls @ check upper syscall limit cmp scno, #NR_syscalls @ check upper syscall limit
ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine ldrcc pc, [tbl, scno, lsl #2] @ call sys_* routine
...@@ -157,7 +157,7 @@ __sys_trace: ...@@ -157,7 +157,7 @@ __sys_trace:
mov r0, #0 @ trace entry [IP = 0] mov r0, #0 @ trace entry [IP = 0]
bl syscall_trace bl syscall_trace
adrsvc al, lr, __sys_trace_return @ return address adr lr, __sys_trace_return @ return address
add r1, sp, #S_R0 + S_OFF @ pointer to regs add r1, sp, #S_R0 + S_OFF @ pointer to regs
cmp scno, #NR_syscalls @ check upper syscall limit cmp scno, #NR_syscalls @ check upper syscall limit
ldmccia r1, {r0 - r3} @ have to reload r0 - r3 ldmccia r1, {r0 - r3} @ have to reload r0 - r3
......
...@@ -141,13 +141,6 @@ ...@@ -141,13 +141,6 @@
mov \rd, \rd, lsl #13 mov \rd, \rd, lsl #13
.endm .endm
/*
* Like adr, but force SVC mode (if required)
*/
.macro adrsvc, cond, reg, label
adr\cond \reg, \label
.endm
.macro alignment_trap, rbase, rtemp, sym .macro alignment_trap, rbase, rtemp, sym
#ifdef CONFIG_ALIGNMENT_TRAP #ifdef CONFIG_ALIGNMENT_TRAP
#define OFF_CR_ALIGNMENT(x) cr_alignment - x #define OFF_CR_ALIGNMENT(x) cr_alignment - x
......
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