Commit 19ce4f4a authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'clk-exynos-for-v3.10' of...

Merge tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

From Kukjin Kim <kgene.kim@samsung.com>:

add suppport common clock framework for exynos

* tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits)
  ARM: EXYNOS: fix compilation error introduced due to common clock migration
  clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
  clk: exynos4: export clocks required for fimc-is
  clk: samsung: Fix compilation error
  clk: exynos5250: register display block gate clocks to common clock framework
  clk: exynos4: Add support for SoC-specific register save list
  clk: exynos4: Add missing registers to suspend save list
  clk: exynos4: Remove E4X12 prefix from SRC_DMC register
  clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
  clk: exynos4: Add E4210 prefix to LCD1 clock registers
  clk: exynos4: Remove SoC-specific registers from save list
  clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
  clk: exynos4: Define {E,V}PLL registers
  clk: exynos4: Add missing mout_sata on Exynos4210
  clk: exynos4: Add missing CMU_TOP and ISP clocks
  clk: exynos4: Add G3D clocks
  clk: exynos4: Add camera related clock definitions
  clk: exynos4: Export mout_core clock of Exynos4210
  clk: samsung: Remove unimplemented ops for pll
  clk: exynos4: Export clocks used by exynos cpufreq drivers
  ...

[arnd: add missing #address-cells property in mshc DT node]
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 228e3023 da821eb7
* Samsung Exynos4 Clock Controller
The Exynos4 clock controller generates and supplies clock to various controllers
within the Exynos4 SoC. The clock binding described here is applicable to all
SoC's in the Exynos4 family.
Required Properties:
- comptible: should be one of the following.
- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
Exynos4 SoC and this is specified where applicable.
[Core Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
xxti 1
xusbxti 2
fin_pll 3
fout_apll 4
fout_mpll 5
fout_epll 6
fout_vpll 7
sclk_apll 8
sclk_mpll 9
sclk_epll 10
sclk_vpll 11
arm_clk 12
aclk200 13
aclk100 14
aclk160 15
aclk133 16
mout_mpll_user_t 17 Exynos4x12
mout_mpll_user_c 18 Exynos4x12
mout_core 19
mout_apll 20
[Clock Gate for Special Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
sclk_fimc0 128
sclk_fimc1 129
sclk_fimc2 130
sclk_fimc3 131
sclk_cam0 132
sclk_cam1 133
sclk_csis0 134
sclk_csis1 135
sclk_hdmi 136
sclk_mixer 137
sclk_dac 138
sclk_pixel 139
sclk_fimd0 140
sclk_mdnie0 141 Exynos4412
sclk_mdnie_pwm0 12 142 Exynos4412
sclk_mipi0 143
sclk_audio0 144
sclk_mmc0 145
sclk_mmc1 146
sclk_mmc2 147
sclk_mmc3 148
sclk_mmc4 149
sclk_sata 150 Exynos4210
sclk_uart0 151
sclk_uart1 152
sclk_uart2 153
sclk_uart3 154
sclk_uart4 155
sclk_audio1 156
sclk_audio2 157
sclk_spdif 158
sclk_spi0 159
sclk_spi1 160
sclk_spi2 161
sclk_slimbus 162
sclk_fimd1 163 Exynos4210
sclk_mipi1 164 Exynos4210
sclk_pcm1 165
sclk_pcm2 166
sclk_i2s1 167
sclk_i2s2 168
sclk_mipihsi 169 Exynos4412
sclk_mfc 170
sclk_pcm0 171
sclk_g3d 172
sclk_pwm_isp 173 Exynos4x12
sclk_spi0_isp 174 Exynos4x12
sclk_spi1_isp 175 Exynos4x12
sclk_uart_isp 176 Exynos4x12
[Peripheral Clock Gates]
Clock ID SoC (if specific)
-----------------------------------------------
fimc0 256
fimc1 257
fimc2 258
fimc3 259
csis0 260
csis1 261
jpeg 262
smmu_fimc0 263
smmu_fimc1 264
smmu_fimc2 265
smmu_fimc3 266
smmu_jpeg 267
vp 268
mixer 269
tvenc 270 Exynos4210
hdmi 271
smmu_tv 272
mfc 273
smmu_mfcl 274
smmu_mfcr 275
g3d 276
g2d 277 Exynos4210
rotator 278 Exynos4210
mdma 279 Exynos4210
smmu_g2d 280 Exynos4210
smmu_rotator 281 Exynos4210
smmu_mdma 282 Exynos4210
fimd0 283
mie0 284
mdnie0 285 Exynos4412
dsim0 286
smmu_fimd0 287
fimd1 288 Exynos4210
mie1 289 Exynos4210
dsim1 290 Exynos4210
smmu_fimd1 291 Exynos4210
pdma0 292
pdma1 293
pcie_phy 294
sata_phy 295 Exynos4210
tsi 296
sdmmc0 297
sdmmc1 298
sdmmc2 299
sdmmc3 300
sdmmc4 301
sata 302 Exynos4210
sromc 303
usb_host 304
usb_device 305
pcie 306
onenand 307
nfcon 308
smmu_pcie 309
gps 310
smmu_gps 311
uart0 312
uart1 313
uart2 314
uart3 315
uart4 316
i2c0 317
i2c1 318
i2c2 319
i2c3 320
i2c4 321
i2c5 322
i2c6 323
i2c7 324
i2c_hdmi 325
tsadc 326
spi0 327
spi1 328
spi2 329
i2s1 330
i2s2 331
pcm0 332
i2s0 333
pcm1 334
pcm2 335
pwm 336
slimbus 337
spdif 338
ac97 339
modemif 340
chipid 341
sysreg 342
hdmi_cec 343
mct 344
wdt 345
rtc 346
keyif 347
audss 348
mipi_hsi 349 Exynos4210
mdma2 350 Exynos4210
pixelasyncm0 351
pixelasyncm1 352
fimc_lite0 353 Exynos4x12
fimc_lite1 354 Exynos4x12
ppmuispx 355 Exynos4x12
ppmuispmx 356 Exynos4x12
fimc_isp 357 Exynos4x12
fimc_drc 358 Exynos4x12
fimc_fd 359 Exynos4x12
mcuisp 360 Exynos4x12
gicisp 361 Exynos4x12
smmu_isp 362 Exynos4x12
smmu_drc 363 Exynos4x12
smmu_fd 364 Exynos4x12
smmu_lite0 365 Exynos4x12
smmu_lite1 366 Exynos4x12
mcuctl_isp 367 Exynos4x12
mpwm_isp 368 Exynos4x12
i2c0_isp 369 Exynos4x12
i2c1_isp 370 Exynos4x12
mtcadc_isp 371 Exynos4x12
pwm_isp 372 Exynos4x12
wdt_isp 373 Exynos4x12
uart_isp 374 Exynos4x12
asyncaxim 375 Exynos4x12
smmu_ispcx 376 Exynos4x12
spi0_isp 377 Exynos4x12
spi1_isp 378 Exynos4x12
pwm_isp_sclk 379 Exynos4x12
spi0_isp_sclk 380 Exynos4x12
spi1_isp_sclk 381 Exynos4x12
uart_isp_sclk 382 Exynos4x12
[Mux Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
mout_fimc0 384
mout_fimc1 385
mout_fimc2 386
mout_fimc3 387
mout_cam0 388
mout_cam1 389
mout_csis0 390
mout_csis1 391
mout_g3d0 392
mout_g3d1 393
mout_g3d 394
aclk400_mcuisp 395 Exynos4x12
[Div Clocks]
Clock ID SoC (if specific)
-----------------------------------------------
div_isp0 450 Exynos4x12
div_isp1 451 Exynos4x12
div_mcuisp0 452 Exynos4x12
div_mcuisp1 453 Exynos4x12
div_aclk200 454 Exynos4x12
div_aclk400_mcuisp 455 Exynos4x12
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x10030000 {
compatible = "samsung,exynos4210-clock";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock 314>, <&clock 153>;
clock-names = "uart", "clk_uart_baud0";
};
* Samsung Exynos5250 Clock Controller
The Exynos5250 clock controller generates and supplies clock to various
controllers within the Exynos5250 SoC.
Required Properties:
- comptible: should be one of the following.
- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume.
[Core Clocks]
Clock ID
----------------------------
fin_pll 1
[Clock Gate for Special Clocks]
Clock ID
----------------------------
sclk_cam_bayer 128
sclk_cam0 129
sclk_cam1 130
sclk_gscl_wa 131
sclk_gscl_wb 132
sclk_fimd1 133
sclk_mipi1 134
sclk_dp 135
sclk_hdmi 136
sclk_pixel 137
sclk_audio0 138
sclk_mmc0 139
sclk_mmc1 140
sclk_mmc2 141
sclk_mmc3 142
sclk_sata 143
sclk_usb3 144
sclk_jpeg 145
sclk_uart0 146
sclk_uart1 147
sclk_uart2 148
sclk_uart3 149
sclk_pwm 150
sclk_audio1 151
sclk_audio2 152
sclk_spdif 153
sclk_spi0 154
sclk_spi1 155
sclk_spi2 156
[Peripheral Clock Gates]
Clock ID
----------------------------
gscl0 256
gscl1 257
gscl2 258
gscl3 259
gscl_wa 260
gscl_wb 261
smmu_gscl0 262
smmu_gscl1 263
smmu_gscl2 264
smmu_gscl3 265
mfc 266
smmu_mfcl 267
smmu_mfcr 268
rotator 269
jpeg 270
mdma1 271
smmu_rotator 272
smmu_jpeg 273
smmu_mdma1 274
pdma0 275
pdma1 276
sata 277
usbotg 278
mipi_hsi 279
sdmmc0 280
sdmmc1 281
sdmmc2 282
sdmmc3 283
sromc 284
usb2 285
usb3 286
sata_phyctrl 287
sata_phyi2c 288
uart0 289
uart1 290
uart2 291
uart3 292
uart4 293
i2c0 294
i2c1 295
i2c2 296
i2c3 297
i2c4 298
i2c5 299
i2c6 300
i2c7 301
i2c_hdmi 302
adc 303
spi0 304
spi1 305
spi2 306
i2s1 307
i2s2 308
pcm1 309
pcm2 310
pwm 311
spdif 312
ac97 313
hsi2c0 314
hsi2c1 315
hs12c2 316
hs12c3 317
chipid 318
sysreg 319
pmu 320
cmu_top 321
cmu_core 322
cmu_mem 323
tzpc0 324
tzpc1 325
tzpc2 326
tzpc3 327
tzpc4 328
tzpc5 329
tzpc6 330
tzpc7 331
tzpc8 332
tzpc9 333
hdmi_cec 334
mct 335
wdt 336
rtc 337
tmu 338
fimd1 339
mie1 340
dsim0 341
dp 342
mixer 343
hdmi 345
Example 1: An example of a clock controller node is listed below.
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5250-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
Example 2: UART controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
clocks = <&clock 314>, <&clock 153>;
clock-names = "uart", "clk_uart_baud0";
};
* Samsung Exynos5440 Clock Controller
The Exynos5440 clock controller generates and supplies clock to various
controllers within the Exynos5440 SoC.
Required Properties:
- comptible: should be "samsung,exynos5440-clock".
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume.
[Core Clocks]
Clock ID
----------------------------
xtal 1
arm_clk 2
[Peripheral Clock Gates]
Clock ID
----------------------------
spi_baud 16
pb0_250 17
pr0_250 18
pr1_250 19
b_250 20
b_125 21
b_200 22
sata 23
usb 24
gmac0 25
cs250 26
pb0_250_o 27
pr0_250_o 28
pr1_250_o 29
b_250_o 30
b_125_o 31
b_200_o 32
sata_o 33
usb_o 34
gmac0_o 35
cs250_o 36
Example: An example of a clock controller node is listed below.
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5440-clock";
reg = <0x160000 0x10000>;
#clock-cells = <1>;
};
...@@ -21,3 +21,24 @@ Required properties: ...@@ -21,3 +21,24 @@ Required properties:
- samsung,mfc-l : Base address of the second memory bank used by MFC - samsung,mfc-l : Base address of the second memory bank used by MFC
for DMA contiguous memory allocation and its size. for DMA contiguous memory allocation and its size.
Optional properties:
- samsung,power-domain : power-domain property defined with a phandle
to respective power domain.
Example:
SoC specific DT entry:
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
interrupts = <0 94 0>;
samsung,power-domain = <&pd_mfc>;
};
Board specific DT entry:
codec@13400000 {
samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>;
};
Samsung Exynos SoC USB controller
The USB devices interface with USB controllers on Exynos SOCs.
The device node has following properties.
EHCI
Required properties:
- compatible: should be "samsung,exynos4210-ehci" for USB 2.0
EHCI controller in host mode.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
Optional properties:
- samsung,vbus-gpio: if present, specifies the GPIO that
needs to be pulled up for the bus to be powered.
Example:
usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
};
OHCI
Required properties:
- compatible: should be "samsung,exynos4210-ohci" for USB 2.0
OHCI companion controller in host mode.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
Example:
usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
};
...@@ -866,6 +866,7 @@ config ARCH_EXYNOS ...@@ -866,6 +866,7 @@ config ARCH_EXYNOS
select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select CLKDEV_LOOKUP select CLKDEV_LOOKUP
select COMMON_CLK
select CPU_V7 select CPU_V7
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select HAVE_CLK select HAVE_CLK
......
...@@ -42,7 +42,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ ...@@ -42,7 +42,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \ exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \ exynos4210-trats.dtb \
exynos4412-odroidx.dtb \
exynos4412-smdk4412.dtb \ exynos4412-smdk4412.dtb \
exynos4412-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \ exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \ exynos5250-snow.dtb \
exynos5440-ssdk5440.dtb exynos5440-ssdk5440.dtb
......
...@@ -24,6 +24,144 @@ i2c@12C60000 { ...@@ -24,6 +24,144 @@ i2c@12C60000 {
samsung,i2c-max-bus-freq = <378000>; samsung,i2c-max-bus-freq = <378000>;
gpios = <&gpb3 0 2 3 0>, gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>; <&gpb3 1 2 3 0>;
max77686@09 {
compatible = "maxim,max77686";
reg = <0x09>;
voltage-regulators {
ldo1_reg: LDO1 {
regulator-name = "P1.0V_LDO_OUT1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "P1.8V_LDO_OUT2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "P1.8V_LDO_OUT3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo7_reg: LDO7 {
regulator-name = "P1.1V_LDO_OUT7";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
ldo8_reg: LDO8 {
regulator-name = "P1.0V_LDO_OUT8";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
ldo10_reg: LDO10 {
regulator-name = "P1.8V_LDO_OUT10";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo12_reg: LDO12 {
regulator-name = "P3.0V_LDO_OUT12";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
ldo14_reg: LDO14 {
regulator-name = "P1.8V_LDO_OUT14";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo15_reg: LDO15 {
regulator-name = "P1.0V_LDO_OUT15";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
ldo16_reg: LDO16 {
regulator-name = "P1.8V_LDO_OUT16";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
buck1_reg: BUCK1 {
regulator-name = "vdd_mif";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
buck2_reg: BUCK2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
buck3_reg: BUCK3 {
regulator-name = "vdd_int";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
buck4_reg: BUCK4 {
regulator-name = "vdd_g3d";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
buck5_reg: BUCK5 {
regulator-name = "P1.8V_BUCK_OUT5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
buck6_reg: BUCK6 {
regulator-name = "P1.35V_BUCK_OUT6";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
buck7_reg: BUCK7 {
regulator-name = "P2.0V_BUCK_OUT7";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
regulator-always-on;
};
buck8_reg: BUCK8 {
regulator-name = "P2.85V_BUCK_OUT8";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
};
};
}; };
i2c@12C70000 { i2c@12C70000 {
......
...@@ -86,6 +86,8 @@ watchdog@10060000 { ...@@ -86,6 +86,8 @@ watchdog@10060000 {
compatible = "samsung,s3c2410-wdt"; compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>; reg = <0x10060000 0x100>;
interrupts = <0 43 0>; interrupts = <0 43 0>;
clocks = <&clock 345>;
clock-names = "watchdog";
status = "disabled"; status = "disabled";
}; };
...@@ -93,6 +95,8 @@ rtc@10070000 { ...@@ -93,6 +95,8 @@ rtc@10070000 {
compatible = "samsung,s3c6410-rtc"; compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>; reg = <0x10070000 0x100>;
interrupts = <0 44 0>, <0 45 0>; interrupts = <0 44 0>, <0 45 0>;
clocks = <&clock 346>;
clock-names = "rtc";
status = "disabled"; status = "disabled";
}; };
...@@ -100,6 +104,8 @@ keypad@100A0000 { ...@@ -100,6 +104,8 @@ keypad@100A0000 {
compatible = "samsung,s5pv210-keypad"; compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>; reg = <0x100A0000 0x100>;
interrupts = <0 109 0>; interrupts = <0 109 0>;
clocks = <&clock 347>;
clock-names = "keypad";
status = "disabled"; status = "disabled";
}; };
...@@ -107,6 +113,8 @@ sdhci@12510000 { ...@@ -107,6 +113,8 @@ sdhci@12510000 {
compatible = "samsung,exynos4210-sdhci"; compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>; reg = <0x12510000 0x100>;
interrupts = <0 73 0>; interrupts = <0 73 0>;
clocks = <&clock 297>, <&clock 145>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled"; status = "disabled";
}; };
...@@ -114,6 +122,8 @@ sdhci@12520000 { ...@@ -114,6 +122,8 @@ sdhci@12520000 {
compatible = "samsung,exynos4210-sdhci"; compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>; reg = <0x12520000 0x100>;
interrupts = <0 74 0>; interrupts = <0 74 0>;
clocks = <&clock 298>, <&clock 146>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled"; status = "disabled";
}; };
...@@ -121,6 +131,8 @@ sdhci@12530000 { ...@@ -121,6 +131,8 @@ sdhci@12530000 {
compatible = "samsung,exynos4210-sdhci"; compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>; reg = <0x12530000 0x100>;
interrupts = <0 75 0>; interrupts = <0 75 0>;
clocks = <&clock 299>, <&clock 147>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled"; status = "disabled";
}; };
...@@ -128,6 +140,16 @@ sdhci@12540000 { ...@@ -128,6 +140,16 @@ sdhci@12540000 {
compatible = "samsung,exynos4210-sdhci"; compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>; reg = <0x12540000 0x100>;
interrupts = <0 76 0>; interrupts = <0 76 0>;
clocks = <&clock 300>, <&clock 148>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
interrupts = <0 94 0>;
samsung,power-domain = <&pd_mfc>;
status = "disabled"; status = "disabled";
}; };
...@@ -135,6 +157,8 @@ serial@13800000 { ...@@ -135,6 +157,8 @@ serial@13800000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>; reg = <0x13800000 0x100>;
interrupts = <0 52 0>; interrupts = <0 52 0>;
clocks = <&clock 312>, <&clock 151>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled"; status = "disabled";
}; };
...@@ -142,6 +166,8 @@ serial@13810000 { ...@@ -142,6 +166,8 @@ serial@13810000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>; reg = <0x13810000 0x100>;
interrupts = <0 53 0>; interrupts = <0 53 0>;
clocks = <&clock 313>, <&clock 152>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled"; status = "disabled";
}; };
...@@ -149,6 +175,8 @@ serial@13820000 { ...@@ -149,6 +175,8 @@ serial@13820000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>; reg = <0x13820000 0x100>;
interrupts = <0 54 0>; interrupts = <0 54 0>;
clocks = <&clock 314>, <&clock 153>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled"; status = "disabled";
}; };
...@@ -156,6 +184,8 @@ serial@13830000 { ...@@ -156,6 +184,8 @@ serial@13830000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>; reg = <0x13830000 0x100>;
interrupts = <0 55 0>; interrupts = <0 55 0>;
clocks = <&clock 315>, <&clock 154>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled"; status = "disabled";
}; };
...@@ -165,6 +195,8 @@ i2c_0: i2c@13860000 { ...@@ -165,6 +195,8 @@ i2c_0: i2c@13860000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>; reg = <0x13860000 0x100>;
interrupts = <0 58 0>; interrupts = <0 58 0>;
clocks = <&clock 317>;
clock-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -174,6 +206,8 @@ i2c_1: i2c@13870000 { ...@@ -174,6 +206,8 @@ i2c_1: i2c@13870000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>; reg = <0x13870000 0x100>;
interrupts = <0 59 0>; interrupts = <0 59 0>;
clocks = <&clock 318>;
clock-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -183,6 +217,8 @@ i2c_2: i2c@13880000 { ...@@ -183,6 +217,8 @@ i2c_2: i2c@13880000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>; reg = <0x13880000 0x100>;
interrupts = <0 60 0>; interrupts = <0 60 0>;
clocks = <&clock 319>;
clock-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -192,6 +228,8 @@ i2c_3: i2c@13890000 { ...@@ -192,6 +228,8 @@ i2c_3: i2c@13890000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>; reg = <0x13890000 0x100>;
interrupts = <0 61 0>; interrupts = <0 61 0>;
clocks = <&clock 320>;
clock-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -201,6 +239,8 @@ i2c_4: i2c@138A0000 { ...@@ -201,6 +239,8 @@ i2c_4: i2c@138A0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>; reg = <0x138A0000 0x100>;
interrupts = <0 62 0>; interrupts = <0 62 0>;
clocks = <&clock 321>;
clock-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -210,6 +250,8 @@ i2c_5: i2c@138B0000 { ...@@ -210,6 +250,8 @@ i2c_5: i2c@138B0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>; reg = <0x138B0000 0x100>;
interrupts = <0 63 0>; interrupts = <0 63 0>;
clocks = <&clock 322>;
clock-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -219,6 +261,8 @@ i2c_6: i2c@138C0000 { ...@@ -219,6 +261,8 @@ i2c_6: i2c@138C0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>; reg = <0x138C0000 0x100>;
interrupts = <0 64 0>; interrupts = <0 64 0>;
clocks = <&clock 323>;
clock-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -228,6 +272,8 @@ i2c_7: i2c@138D0000 { ...@@ -228,6 +272,8 @@ i2c_7: i2c@138D0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>; reg = <0x138D0000 0x100>;
interrupts = <0 65 0>; interrupts = <0 65 0>;
clocks = <&clock 324>;
clock-names = "i2c";
status = "disabled"; status = "disabled";
}; };
...@@ -239,6 +285,8 @@ spi_0: spi@13920000 { ...@@ -239,6 +285,8 @@ spi_0: spi@13920000 {
rx-dma-channel = <&pdma0 6>; /* preliminary */ rx-dma-channel = <&pdma0 6>; /* preliminary */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 327>, <&clock 159>;
clock-names = "spi", "spi_busclk0";
status = "disabled"; status = "disabled";
}; };
...@@ -250,6 +298,8 @@ spi_1: spi@13930000 { ...@@ -250,6 +298,8 @@ spi_1: spi@13930000 {
rx-dma-channel = <&pdma1 6>; /* preliminary */ rx-dma-channel = <&pdma1 6>; /* preliminary */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 328>, <&clock 160>;
clock-names = "spi", "spi_busclk0";
status = "disabled"; status = "disabled";
}; };
...@@ -261,6 +311,8 @@ spi_2: spi@13940000 { ...@@ -261,6 +311,8 @@ spi_2: spi@13940000 {
rx-dma-channel = <&pdma0 8>; /* preliminary */ rx-dma-channel = <&pdma0 8>; /* preliminary */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 329>, <&clock 161>;
clock-names = "spi", "spi_busclk0";
status = "disabled"; status = "disabled";
}; };
...@@ -275,6 +327,8 @@ pdma0: pdma@12680000 { ...@@ -275,6 +327,8 @@ pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>; reg = <0x12680000 0x1000>;
interrupts = <0 35 0>; interrupts = <0 35 0>;
clocks = <&clock 292>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <32>; #dma-requests = <32>;
...@@ -284,6 +338,8 @@ pdma1: pdma@12690000 { ...@@ -284,6 +338,8 @@ pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>; reg = <0x12690000 0x1000>;
interrupts = <0 36 0>; interrupts = <0 36 0>;
clocks = <&clock 293>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <32>; #dma-requests = <32>;
...@@ -293,6 +349,8 @@ mdma1: mdma@12850000 { ...@@ -293,6 +349,8 @@ mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>; reg = <0x12850000 0x1000>;
interrupts = <0 34 0>; interrupts = <0 34 0>;
clocks = <&clock 279>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <1>; #dma-requests = <1>;
......
...@@ -57,6 +57,12 @@ sdhci@12510000 { ...@@ -57,6 +57,12 @@ sdhci@12510000 {
status = "okay"; status = "okay";
}; };
codec@13400000 {
samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>;
status = "okay";
};
serial@13800000 { serial@13800000 {
status = "okay"; status = "okay";
}; };
...@@ -121,4 +127,16 @@ status { ...@@ -121,4 +127,16 @@ status {
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
}; };
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <0>;
};
xusbxti {
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
};
}; };
...@@ -43,6 +43,12 @@ sdhci@12530000 { ...@@ -43,6 +43,12 @@ sdhci@12530000 {
status = "okay"; status = "okay";
}; };
codec@13400000 {
samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>;
status = "okay";
};
serial@13800000 { serial@13800000 {
status = "okay"; status = "okay";
}; };
...@@ -189,4 +195,16 @@ partition@40000 { ...@@ -189,4 +195,16 @@ partition@40000 {
}; };
}; };
}; };
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <12000000>;
};
xusbxti {
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
};
}; };
...@@ -289,4 +289,16 @@ safe2_sreg: ESAFEOUT2 { ...@@ -289,4 +289,16 @@ safe2_sreg: ESAFEOUT2 {
}; };
}; };
}; };
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <0>;
};
xusbxti {
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
};
}; };
...@@ -55,6 +55,8 @@ mct@10050000 { ...@@ -55,6 +55,8 @@ mct@10050000 {
interrupt-parent = <&mct_map>; interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>, interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>; <4 0>, <5 0>;
clocks = <&clock 3>, <&clock 344>;
clock-names = "fin_pll", "mct";
mct_map: mct-map { mct_map: mct-map {
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -69,6 +71,12 @@ mct_map: mct-map { ...@@ -69,6 +71,12 @@ mct_map: mct-map {
}; };
}; };
clock: clock-controller@0x10030000 {
compatible = "samsung,exynos4210-clock";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
};
pinctrl_0: pinctrl@11400000 { pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl"; compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>; reg = <0x11400000 0x1000>;
......
/*
* Hardkernel's Exynos4412 based ODROID-X board device tree source
*
* Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
*
* Device tree source file for Hardkernel's ODROID-X board which is based on
* Samsung's Exynos4412 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "exynos4412.dtsi"
/ {
model = "Hardkernel ODROID-X board based on Exynos4412";
compatible = "hardkernel,odroid-x", "samsung,exynos4412";
memory {
reg = <0x40000000 0x40000000>;
};
leds {
compatible = "gpio-leds";
led1 {
label = "led1:heart";
gpios = <&gpc1 0 1>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led2 {
label = "led2:mmc0";
gpios = <&gpc1 2 1>;
default-state = "on";
linux,default-trigger = "mmc0";
};
};
mshc@12550000 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
pinctrl-names = "default";
status = "okay";
num-slots = <1>;
supports-highspeed;
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
regulator_p3v3 {
compatible = "regulator-fixed";
regulator-name = "p3v3_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpa1 1 1>;
enable-active-high;
regulator-boot-on;
};
rtc@10070000 {
status = "okay";
};
sdhci@12530000 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
pinctrl-names = "default";
status = "okay";
};
serial@13800000 {
status = "okay";
};
serial@13810000 {
status = "okay";
};
serial@13820000 {
status = "okay";
};
serial@13830000 {
status = "okay";
};
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <0>;
};
xusbxti {
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
};
};
This diff is collapsed.
...@@ -27,6 +27,19 @@ chosen { ...@@ -27,6 +27,19 @@ chosen {
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
}; };
sdhci@12530000 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
pinctrl-names = "default";
status = "okay";
};
codec@13400000 {
samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>;
status = "okay";
};
serial@13800000 { serial@13800000 {
status = "okay"; status = "okay";
}; };
...@@ -42,4 +55,16 @@ serial@13820000 { ...@@ -42,4 +55,16 @@ serial@13820000 {
serial@13830000 { serial@13830000 {
status = "okay"; status = "okay";
}; };
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <0>;
};
xusbxti {
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
};
}; };
...@@ -34,6 +34,8 @@ mct@10050000 { ...@@ -34,6 +34,8 @@ mct@10050000 {
interrupt-parent = <&mct_map>; interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>, interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>; <4 0>, <5 0>, <6 0>, <7 0>;
clocks = <&clock 3>, <&clock 344>;
clock-names = "fin_pll", "mct";
mct_map: mct-map { mct_map: mct-map {
#interrupt-cells = <2>; #interrupt-cells = <2>;
......
...@@ -36,6 +36,12 @@ combiner:interrupt-controller@10440000 { ...@@ -36,6 +36,12 @@ combiner:interrupt-controller@10440000 {
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>; <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
}; };
clock: clock-controller@0x10030000 {
compatible = "samsung,exynos4412-clock";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
};
pinctrl_0: pinctrl@11400000 { pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4x12-pinctrl"; compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>; reg = <0x11400000 0x1000>;
......
/*
* Samsung's Exynos5250 based Arndale board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "exynos5250.dtsi"
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";
compatible = "insignal,arndale", "samsung,exynos5250";
memory {
reg = <0x40000000 0x80000000>;
};
chosen {
bootargs = "console=ttySAC2,115200";
};
i2c@12C60000 {
status = "disabled";
};
i2c@12C70000 {
status = "disabled";
};
i2c@12C80000 {
status = "disabled";
};
i2c@12C90000 {
status = "disabled";
};
i2c@12CA0000 {
status = "disabled";
};
i2c@12CB0000 {
status = "disabled";
};
i2c@12CC0000 {
status = "disabled";
};
i2c@12CD0000 {
status = "disabled";
};
i2c@121D0000 {
status = "disabled";
};
dwmmc_0: dwmmc0@12200000 {
num-slots = <1>;
supports-highspeed;
broken-cd;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <8>;
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
};
};
dwmmc_1: dwmmc1@12210000 {
status = "disabled";
};
dwmmc_2: dwmmc2@12220000 {
num-slots = <1>;
supports-highspeed;
fifo-depth = <0x80>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
slot@0 {
reg = <0>;
bus-width = <4>;
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
};
};
dwmmc_3: dwmmc3@12230000 {
status = "disabled";
};
spi_0: spi@12d20000 {
status = "disabled";
};
spi_1: spi@12d30000 {
status = "disabled";
};
spi_2: spi@12d40000 {
status = "disabled";
};
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <24000000>;
};
};
};
...@@ -231,4 +231,24 @@ sound { ...@@ -231,4 +231,24 @@ sound {
samsung,i2s-controller = <&i2s0>; samsung,i2s-controller = <&i2s0>;
samsung,audio-codec = <&wm8994>; samsung,audio-codec = <&wm8994>;
}; };
usb@12110000 {
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
};
dp-controller {
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
};
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <24000000>;
};
};
}; };
...@@ -40,4 +40,15 @@ slot@0 { ...@@ -40,4 +40,15 @@ slot@0 {
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>; <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
}; };
}; };
usb@12110000 {
samsung,vbus-gpio = <&gpx1 1 1 3 3>;
};
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <24000000>;
};
};
}; };
...@@ -46,6 +46,22 @@ aliases { ...@@ -46,6 +46,22 @@ aliases {
i2c8 = &i2c_8; i2c8 = &i2c_8;
}; };
pd_gsc: gsc-power-domain@0x10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
};
pd_mfc: mfc-power-domain@0x10044040 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044040 0x20>;
};
clock: clock-controller@0x10010000 {
compatible = "samsung,exynos5250-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
gic:interrupt-controller@10481000 { gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic"; compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
...@@ -77,6 +93,8 @@ mct@101C0000 { ...@@ -77,6 +93,8 @@ mct@101C0000 {
interrupt-parent = <&mct_map>; interrupt-parent = <&mct_map>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>, interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>; <4 0>, <5 0>;
clocks = <&clock 1>, <&clock 335>;
clock-names = "fin_pll", "mct";
mct_map: mct-map { mct_map: mct-map {
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -95,54 +113,71 @@ watchdog { ...@@ -95,54 +113,71 @@ watchdog {
compatible = "samsung,s3c2410-wdt"; compatible = "samsung,s3c2410-wdt";
reg = <0x101D0000 0x100>; reg = <0x101D0000 0x100>;
interrupts = <0 42 0>; interrupts = <0 42 0>;
clocks = <&clock 336>;
clock-names = "watchdog";
}; };
codec@11000000 { codec@11000000 {
compatible = "samsung,mfc-v6"; compatible = "samsung,mfc-v6";
reg = <0x11000000 0x10000>; reg = <0x11000000 0x10000>;
interrupts = <0 96 0>; interrupts = <0 96 0>;
samsung,power-domain = <&pd_mfc>;
}; };
rtc { rtc {
compatible = "samsung,s3c6410-rtc"; compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>; reg = <0x101E0000 0x100>;
interrupts = <0 43 0>, <0 44 0>; interrupts = <0 43 0>, <0 44 0>;
clocks = <&clock 337>;
clock-names = "rtc";
}; };
tmu@10060000 { tmu@10060000 {
compatible = "samsung,exynos5250-tmu"; compatible = "samsung,exynos5250-tmu";
reg = <0x10060000 0x100>; reg = <0x10060000 0x100>;
interrupts = <0 65 0>; interrupts = <0 65 0>;
clocks = <&clock 338>;
clock-names = "tmu_apbif";
}; };
serial@12C00000 { serial@12C00000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>; reg = <0x12C00000 0x100>;
interrupts = <0 51 0>; interrupts = <0 51 0>;
clocks = <&clock 289>, <&clock 146>;
clock-names = "uart", "clk_uart_baud0";
}; };
serial@12C10000 { serial@12C10000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>; reg = <0x12C10000 0x100>;
interrupts = <0 52 0>; interrupts = <0 52 0>;
clocks = <&clock 290>, <&clock 147>;
clock-names = "uart", "clk_uart_baud0";
}; };
serial@12C20000 { serial@12C20000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>; reg = <0x12C20000 0x100>;
interrupts = <0 53 0>; interrupts = <0 53 0>;
clocks = <&clock 291>, <&clock 148>;
clock-names = "uart", "clk_uart_baud0";
}; };
serial@12C30000 { serial@12C30000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>; reg = <0x12C30000 0x100>;
interrupts = <0 54 0>; interrupts = <0 54 0>;
clocks = <&clock 292>, <&clock 149>;
clock-names = "uart", "clk_uart_baud0";
}; };
sata@122F0000 { sata@122F0000 {
compatible = "samsung,exynos5-sata-ahci"; compatible = "samsung,exynos5-sata-ahci";
reg = <0x122F0000 0x1ff>; reg = <0x122F0000 0x1ff>;
interrupts = <0 115 0>; interrupts = <0 115 0>;
clocks = <&clock 277>, <&clock 143>;
clock-names = "sata", "sclk_sata";
}; };
sata-phy@12170000 { sata-phy@12170000 {
...@@ -156,6 +191,8 @@ i2c_0: i2c@12C60000 { ...@@ -156,6 +191,8 @@ i2c_0: i2c@12C60000 {
interrupts = <0 56 0>; interrupts = <0 56 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 294>;
clock-names = "i2c";
}; };
i2c_1: i2c@12C70000 { i2c_1: i2c@12C70000 {
...@@ -164,6 +201,8 @@ i2c_1: i2c@12C70000 { ...@@ -164,6 +201,8 @@ i2c_1: i2c@12C70000 {
interrupts = <0 57 0>; interrupts = <0 57 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 295>;
clock-names = "i2c";
}; };
i2c_2: i2c@12C80000 { i2c_2: i2c@12C80000 {
...@@ -172,6 +211,8 @@ i2c_2: i2c@12C80000 { ...@@ -172,6 +211,8 @@ i2c_2: i2c@12C80000 {
interrupts = <0 58 0>; interrupts = <0 58 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 296>;
clock-names = "i2c";
}; };
i2c_3: i2c@12C90000 { i2c_3: i2c@12C90000 {
...@@ -180,6 +221,8 @@ i2c_3: i2c@12C90000 { ...@@ -180,6 +221,8 @@ i2c_3: i2c@12C90000 {
interrupts = <0 59 0>; interrupts = <0 59 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 297>;
clock-names = "i2c";
}; };
i2c_4: i2c@12CA0000 { i2c_4: i2c@12CA0000 {
...@@ -188,6 +231,8 @@ i2c_4: i2c@12CA0000 { ...@@ -188,6 +231,8 @@ i2c_4: i2c@12CA0000 {
interrupts = <0 60 0>; interrupts = <0 60 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 298>;
clock-names = "i2c";
}; };
i2c_5: i2c@12CB0000 { i2c_5: i2c@12CB0000 {
...@@ -196,6 +241,8 @@ i2c_5: i2c@12CB0000 { ...@@ -196,6 +241,8 @@ i2c_5: i2c@12CB0000 {
interrupts = <0 61 0>; interrupts = <0 61 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 299>;
clock-names = "i2c";
}; };
i2c_6: i2c@12CC0000 { i2c_6: i2c@12CC0000 {
...@@ -204,6 +251,8 @@ i2c_6: i2c@12CC0000 { ...@@ -204,6 +251,8 @@ i2c_6: i2c@12CC0000 {
interrupts = <0 62 0>; interrupts = <0 62 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 300>;
clock-names = "i2c";
}; };
i2c_7: i2c@12CD0000 { i2c_7: i2c@12CD0000 {
...@@ -212,6 +261,8 @@ i2c_7: i2c@12CD0000 { ...@@ -212,6 +261,8 @@ i2c_7: i2c@12CD0000 {
interrupts = <0 63 0>; interrupts = <0 63 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 301>;
clock-names = "i2c";
}; };
i2c_8: i2c@12CE0000 { i2c_8: i2c@12CE0000 {
...@@ -220,6 +271,8 @@ i2c_8: i2c@12CE0000 { ...@@ -220,6 +271,8 @@ i2c_8: i2c@12CE0000 {
interrupts = <0 64 0>; interrupts = <0 64 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 302>;
clock-names = "i2c";
}; };
i2c@121D0000 { i2c@121D0000 {
...@@ -227,6 +280,8 @@ i2c@121D0000 { ...@@ -227,6 +280,8 @@ i2c@121D0000 {
reg = <0x121D0000 0x100>; reg = <0x121D0000 0x100>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 288>;
clock-names = "i2c";
}; };
spi_0: spi@12d20000 { spi_0: spi@12d20000 {
...@@ -238,6 +293,8 @@ spi_0: spi@12d20000 { ...@@ -238,6 +293,8 @@ spi_0: spi@12d20000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 304>, <&clock 154>;
clock-names = "spi", "spi_busclk0";
}; };
spi_1: spi@12d30000 { spi_1: spi@12d30000 {
...@@ -249,6 +306,8 @@ spi_1: spi@12d30000 { ...@@ -249,6 +306,8 @@ spi_1: spi@12d30000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 305>, <&clock 155>;
clock-names = "spi", "spi_busclk0";
}; };
spi_2: spi@12d40000 { spi_2: spi@12d40000 {
...@@ -260,6 +319,8 @@ spi_2: spi@12d40000 { ...@@ -260,6 +319,8 @@ spi_2: spi@12d40000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 306>, <&clock 156>;
clock-names = "spi", "spi_busclk0";
}; };
dwmmc_0: dwmmc0@12200000 { dwmmc_0: dwmmc0@12200000 {
...@@ -268,6 +329,8 @@ dwmmc_0: dwmmc0@12200000 { ...@@ -268,6 +329,8 @@ dwmmc_0: dwmmc0@12200000 {
interrupts = <0 75 0>; interrupts = <0 75 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 280>, <&clock 139>;
clock-names = "biu", "ciu";
}; };
dwmmc_1: dwmmc1@12210000 { dwmmc_1: dwmmc1@12210000 {
...@@ -276,6 +339,8 @@ dwmmc_1: dwmmc1@12210000 { ...@@ -276,6 +339,8 @@ dwmmc_1: dwmmc1@12210000 {
interrupts = <0 76 0>; interrupts = <0 76 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 281>, <&clock 140>;
clock-names = "biu", "ciu";
}; };
dwmmc_2: dwmmc2@12220000 { dwmmc_2: dwmmc2@12220000 {
...@@ -284,6 +349,8 @@ dwmmc_2: dwmmc2@12220000 { ...@@ -284,6 +349,8 @@ dwmmc_2: dwmmc2@12220000 {
interrupts = <0 77 0>; interrupts = <0 77 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 282>, <&clock 141>;
clock-names = "biu", "ciu";
}; };
dwmmc_3: dwmmc3@12230000 { dwmmc_3: dwmmc3@12230000 {
...@@ -292,6 +359,8 @@ dwmmc_3: dwmmc3@12230000 { ...@@ -292,6 +359,8 @@ dwmmc_3: dwmmc3@12230000 {
interrupts = <0 78 0>; interrupts = <0 78 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 283>, <&clock 142>;
clock-names = "biu", "ciu";
}; };
i2s0: i2s@03830000 { i2s0: i2s@03830000 {
...@@ -323,6 +392,18 @@ i2s2: i2s@12D70000 { ...@@ -323,6 +392,18 @@ i2s2: i2s@12D70000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
};
usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
};
amba { amba {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -334,6 +415,8 @@ pdma0: pdma@121A0000 { ...@@ -334,6 +415,8 @@ pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>; reg = <0x121A0000 0x1000>;
interrupts = <0 34 0>; interrupts = <0 34 0>;
clocks = <&clock 275>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <32>; #dma-requests = <32>;
...@@ -343,6 +426,8 @@ pdma1: pdma@121B0000 { ...@@ -343,6 +426,8 @@ pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>; reg = <0x121B0000 0x1000>;
interrupts = <0 35 0>; interrupts = <0 35 0>;
clocks = <&clock 276>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <32>; #dma-requests = <32>;
...@@ -352,6 +437,8 @@ mdma0: mdma@10800000 { ...@@ -352,6 +437,8 @@ mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>; reg = <0x10800000 0x1000>;
interrupts = <0 33 0>; interrupts = <0 33 0>;
clocks = <&clock 271>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <1>; #dma-requests = <1>;
...@@ -361,6 +448,8 @@ mdma1: mdma@11C10000 { ...@@ -361,6 +448,8 @@ mdma1: mdma@11C10000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>; reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>; interrupts = <0 124 0>;
clocks = <&clock 271>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <1>; #dma-requests = <1>;
...@@ -614,34 +703,51 @@ gpz: gpio-controller@03860000 { ...@@ -614,34 +703,51 @@ gpz: gpio-controller@03860000 {
}; };
}; };
gsc_0: gsc@0x13e00000 { gsc_0: gsc@0x13e00000 {
compatible = "samsung,exynos5-gsc"; compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>; reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>; interrupts = <0 85 0>;
samsung,power-domain = <&pd_gsc>;
clocks = <&clock 256>;
clock-names = "gscl";
}; };
gsc_1: gsc@0x13e10000 { gsc_1: gsc@0x13e10000 {
compatible = "samsung,exynos5-gsc"; compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>; reg = <0x13e10000 0x1000>;
interrupts = <0 86 0>; interrupts = <0 86 0>;
samsung,power-domain = <&pd_gsc>;
clocks = <&clock 257>;
clock-names = "gscl";
}; };
gsc_2: gsc@0x13e20000 { gsc_2: gsc@0x13e20000 {
compatible = "samsung,exynos5-gsc"; compatible = "samsung,exynos5-gsc";
reg = <0x13e20000 0x1000>; reg = <0x13e20000 0x1000>;
interrupts = <0 87 0>; interrupts = <0 87 0>;
samsung,power-domain = <&pd_gsc>;
clocks = <&clock 258>;
clock-names = "gscl";
}; };
gsc_3: gsc@0x13e30000 { gsc_3: gsc@0x13e30000 {
compatible = "samsung,exynos5-gsc"; compatible = "samsung,exynos5-gsc";
reg = <0x13e30000 0x1000>; reg = <0x13e30000 0x1000>;
interrupts = <0 88 0>; interrupts = <0 88 0>;
samsung,power-domain = <&pd_gsc>;
clocks = <&clock 259>;
clock-names = "gscl";
}; };
hdmi { hdmi {
compatible = "samsung,exynos5-hdmi"; compatible = "samsung,exynos5-hdmi";
reg = <0x14530000 0x70000>; reg = <0x14530000 0x70000>;
interrupts = <0 95 0>; interrupts = <0 95 0>;
clocks = <&clock 333>, <&clock 136>, <&clock 137>,
<&clock 333>, <&clock 333>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
"sclk_hdmiphy", "hdmiphy";
}; };
mixer { mixer {
...@@ -649,4 +755,18 @@ mixer { ...@@ -649,4 +755,18 @@ mixer {
reg = <0x14450000 0x10000>; reg = <0x14450000 0x10000>;
interrupts = <0 94 0>; interrupts = <0 94 0>;
}; };
dp-controller {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
interrupts = <10 3>;
interrupt-parent = <&combiner>;
#address-cells = <1>;
#size-cells = <0>;
dptx-phy {
reg = <0x10040720>;
samsung,enable-mask = <1>;
};
};
}; };
...@@ -28,19 +28,10 @@ spi { ...@@ -28,19 +28,10 @@ spi {
status = "disabled"; status = "disabled";
}; };
i2c@F0000 { fixed-rate-clocks {
status = "disabled"; xtal {
}; compatible = "samsung,clock-xtal";
clock-frequency = <50000000>;
i2c@100000 { };
status = "disabled";
};
watchdog {
status = "disabled";
};
rtc {
status = "disabled";
}; };
}; };
...@@ -16,6 +16,12 @@ / { ...@@ -16,6 +16,12 @@ / {
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
clock: clock-controller@0x160000 {
compatible = "samsung,exynos5440-clock";
reg = <0x160000 0x1000>;
#clock-cells = <1>;
};
gic:interrupt-controller@2E0000 { gic:interrupt-controller@2E0000 {
compatible = "arm,cortex-a15-gic"; compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
...@@ -24,55 +30,51 @@ gic:interrupt-controller@2E0000 { ...@@ -24,55 +30,51 @@ gic:interrupt-controller@2E0000 {
}; };
cpus { cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 { cpu@0 {
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
timer { reg = <0>;
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>;
clock-frequency = <1000000>;
};
}; };
cpu@1 { cpu@1 {
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
timer { reg = <1>;
compatible = "arm,armv7-timer";
interrupts = <1 14 0xf08>;
clock-frequency = <1000000>;
};
}; };
cpu@2 { cpu@2 {
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
timer { reg = <2>;
compatible = "arm,armv7-timer";
interrupts = <1 14 0xf08>;
clock-frequency = <1000000>;
};
}; };
cpu@3 { cpu@3 {
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
timer { reg = <3>;
compatible = "arm,armv7-timer";
interrupts = <1 14 0xf08>;
clock-frequency = <1000000>;
};
}; };
}; };
common { timer {
compatible = "samsung,exynos5440"; compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
clock-frequency = <50000000>;
}; };
serial@B0000 { serial@B0000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>; reg = <0xB0000 0x1000>;
interrupts = <0 2 0>; interrupts = <0 2 0>;
clocks = <&clock 21>, <&clock 21>;
clock-names = "uart", "clk_uart_baud0";
}; };
serial@C0000 { serial@C0000 {
compatible = "samsung,exynos4210-uart"; compatible = "samsung,exynos4210-uart";
reg = <0xC0000 0x1000>; reg = <0xC0000 0x1000>;
interrupts = <0 3 0>; interrupts = <0 3 0>;
clocks = <&clock 21>, <&clock 21>;
clock-names = "uart", "clk_uart_baud0";
}; };
spi { spi {
...@@ -83,6 +85,8 @@ spi { ...@@ -83,6 +85,8 @@ spi {
rx-dma-channel = <&pdma0 4>; /* preliminary */ rx-dma-channel = <&pdma0 4>; /* preliminary */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 21>, <&clock 16>;
clock-names = "spi", "spi_busclk0";
}; };
pinctrl { pinctrl {
...@@ -110,25 +114,31 @@ uart1: uart1 { ...@@ -110,25 +114,31 @@ uart1: uart1 {
}; };
i2c@F0000 { i2c@F0000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,exynos5440-i2c";
reg = <0xF0000 0x1000>; reg = <0xF0000 0x1000>;
interrupts = <0 5 0>; interrupts = <0 5 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 21>;
clock-names = "i2c";
}; };
i2c@100000 { i2c@100000 {
compatible = "samsung,s3c2440-i2c"; compatible = "samsung,exynos5440-i2c";
reg = <0x100000 0x1000>; reg = <0x100000 0x1000>;
interrupts = <0 6 0>; interrupts = <0 6 0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&clock 21>;
clock-names = "i2c";
}; };
watchdog { watchdog {
compatible = "samsung,s3c2410-wdt"; compatible = "samsung,s3c2410-wdt";
reg = <0x110000 0x1000>; reg = <0x110000 0x1000>;
interrupts = <0 1 0>; interrupts = <0 1 0>;
clocks = <&clock 21>;
clock-names = "watchdog";
}; };
amba { amba {
...@@ -142,6 +152,8 @@ pdma0: pdma@121A0000 { ...@@ -142,6 +152,8 @@ pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x120000 0x1000>; reg = <0x120000 0x1000>;
interrupts = <0 34 0>; interrupts = <0 34 0>;
clocks = <&clock 21>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <32>; #dma-requests = <32>;
...@@ -151,6 +163,8 @@ pdma1: pdma@121B0000 { ...@@ -151,6 +163,8 @@ pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x121000 0x1000>; reg = <0x121000 0x1000>;
interrupts = <0 35 0>; interrupts = <0 35 0>;
clocks = <&clock 21>;
clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
#dma-requests = <32>; #dma-requests = <32>;
...@@ -161,5 +175,7 @@ rtc { ...@@ -161,5 +175,7 @@ rtc {
compatible = "samsung,s3c6410-rtc"; compatible = "samsung,s3c6410-rtc";
reg = <0x130000 0x1000>; reg = <0x130000 0x1000>;
interrupts = <0 17 0>, <0 16 0>; interrupts = <0 17 0>, <0 16 0>;
clocks = <&clock 21>;
clock-names = "rtc";
}; };
}; };
...@@ -61,6 +61,7 @@ config SOC_EXYNOS5250 ...@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250" bool "SAMSUNG EXYNOS5250"
default y default y
depends on ARCH_EXYNOS5 depends on ARCH_EXYNOS5
select PM_GENERIC_DOMAINS if PM
select S5P_PM if PM select S5P_PM if PM
select S5P_SLEEP if PM select S5P_SLEEP if PM
select S5P_DEV_MFC select S5P_DEV_MFC
...@@ -405,6 +406,7 @@ config MACH_EXYNOS4_DT ...@@ -405,6 +406,7 @@ config MACH_EXYNOS4_DT
select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
select PINCTRL select PINCTRL
select PINCTRL_EXYNOS select PINCTRL_EXYNOS
select S5P_DEV_MFC
select USE_OF select USE_OF
help help
Machine support for Samsung Exynos4 machine with device tree enabled. Machine support for Samsung Exynos4 machine with device tree enabled.
......
...@@ -13,10 +13,6 @@ obj- := ...@@ -13,10 +13,6 @@ obj- :=
# Core # Core
obj-$(CONFIG_ARCH_EXYNOS) += common.o obj-$(CONFIG_ARCH_EXYNOS) += common.o
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
......
This diff is collapsed.
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for exynos4 clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H __FILE__
#include <linux/clk.h>
extern struct clksrc_clk exynos4_clk_aclk_133;
extern struct clksrc_clk exynos4_clk_mout_mpll;
extern struct clksrc_sources exynos4_clkset_mout_corebus;
extern struct clksrc_sources exynos4_clkset_group;
extern struct clk *exynos4_clkset_aclk_top_list[];
extern struct clk *exynos4_clkset_group_list[];
extern struct clksrc_sources exynos4_clkset_mout_g2d0;
extern struct clksrc_sources exynos4_clkset_mout_g2d1;
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
#endif /* __ASM_ARCH_CLOCK_H */
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4210 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include "common.h"
#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4210_clock_save[] = {
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
};
#endif
static struct clksrc_clk *sysclks[] = {
/* nothing here yet */
};
static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
},
.sources = &exynos4_clkset_mout_g2d0,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
};
static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
},
.sources = &exynos4_clkset_mout_g2d1,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
};
static struct clk *exynos4210_clkset_mout_g2d_list[] = {
[0] = &exynos4210_clk_mout_g2d0.clk,
[1] = &exynos4210_clk_mout_g2d1.clk,
};
static struct clksrc_sources exynos4210_clkset_mout_g2d = {
.sources = exynos4210_clkset_mout_g2d_list,
.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
};
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
}
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_sata",
.id = -1,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &exynos4_clkset_mout_corebus,
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_fimd",
.devname = "exynos4-fb.1",
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimg2d",
},
.sources = &exynos4210_clkset_mout_g2d,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
},
};
static struct clk init_clocks_off[] = {
{
.name = "sataphy",
.id = -1,
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "sata",
.id = -1,
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "fimd",
.devname = "exynos4-fb.1",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.11",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "fimg2d",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
},
};
#ifdef CONFIG_PM_SLEEP
static int exynos4210_clock_suspend(void)
{
s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
return 0;
}
static void exynos4210_clock_resume(void)
{
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
}
#else
#define exynos4210_clock_suspend NULL
#define exynos4210_clock_resume NULL
#endif
static struct syscore_ops exynos4210_clock_syscore_ops = {
.suspend = exynos4210_clock_suspend,
.resume = exynos4210_clock_resume,
};
void __init exynos4210_register_clocks(void)
{
int ptr;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
exynos4_clk_mout_mpll.reg_src.shift = 8;
exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
register_syscore_ops(&exynos4210_clock_syscore_ops);
}
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4212 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include "common.h"
#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4212_clock_save[] = {
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
};
#endif
static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
}
static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
}
static struct clk *clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos4_clk_mout_mpll.clk,
};
static struct clksrc_sources clk_src_mpll_user = {
.sources = clk_src_mpll_user_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
};
static struct clksrc_clk clk_mout_mpll_user = {
.clk = {
.name = "mout_mpll_user",
},
.sources = &clk_src_mpll_user,
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
};
static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
},
.sources = &exynos4_clkset_mout_g2d0,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
};
static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
},
.sources = &exynos4_clkset_mout_g2d1,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
};
static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
[0] = &exynos4x12_clk_mout_g2d0.clk,
[1] = &exynos4x12_clk_mout_g2d1.clk,
};
static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
.sources = exynos4x12_clkset_mout_g2d_list,
.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
};
static struct clksrc_clk *sysclks[] = {
&clk_mout_mpll_user,
};
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_fimg2d",
},
.sources = &exynos4x12_clkset_mout_g2d,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
},
};
static struct clk init_clocks_off[] = {
{
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.12",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (7 << 8),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.13",
.enable = exynos4212_clk_ip_isp1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.14",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.15",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.0",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.1",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimg2d",
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 23),
},
};
#ifdef CONFIG_PM_SLEEP
static int exynos4212_clock_suspend(void)
{
s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
return 0;
}
static void exynos4212_clock_resume(void)
{
s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
}
#else
#define exynos4212_clock_suspend NULL
#define exynos4212_clock_resume NULL
#endif
static struct syscore_ops exynos4212_clock_syscore_ops = {
.suspend = exynos4212_clock_suspend,
.resume = exynos4212_clock_resume,
};
void __init exynos4212_register_clocks(void)
{
int ptr;
/* usbphy1 is removed */
exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used */
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_mpll.reg_src.shift = 12;
exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
register_syscore_ops(&exynos4212_clock_syscore_ops);
}
This diff is collapsed.
...@@ -25,6 +25,8 @@ ...@@ -25,6 +25,8 @@
#include <linux/irqdomain.h> #include <linux/irqdomain.h>
#include <linux/irqchip.h> #include <linux/irqchip.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/clocksource.h>
#include <linux/clk-provider.h>
#include <linux/irqchip/arm-gic.h> #include <linux/irqchip/arm-gic.h>
#include <asm/proc-fns.h> #include <asm/proc-fns.h>
...@@ -39,7 +41,6 @@ ...@@ -39,7 +41,6 @@
#include <mach/regs-gpio.h> #include <mach/regs-gpio.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/pm.h> #include <plat/pm.h>
#include <plat/sdhci.h> #include <plat/sdhci.h>
...@@ -65,17 +66,16 @@ static const char name_exynos5440[] = "EXYNOS5440"; ...@@ -65,17 +66,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
static void exynos4_map_io(void); static void exynos4_map_io(void);
static void exynos5_map_io(void); static void exynos5_map_io(void);
static void exynos5440_map_io(void); static void exynos5440_map_io(void);
static void exynos4_init_clocks(int xtal);
static void exynos5_init_clocks(int xtal);
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static int exynos_init(void); static int exynos_init(void);
unsigned long xxti_f = 0, xusbxti_f = 0;
static struct cpu_table cpu_ids[] __initdata = { static struct cpu_table cpu_ids[] __initdata = {
{ {
.idcode = EXYNOS4210_CPU_ID, .idcode = EXYNOS4210_CPU_ID,
.idmask = EXYNOS4_CPU_MASK, .idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io, .map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts, .init_uarts = exynos4_init_uarts,
.init = exynos_init, .init = exynos_init,
.name = name_exynos4210, .name = name_exynos4210,
...@@ -83,7 +83,6 @@ static struct cpu_table cpu_ids[] __initdata = { ...@@ -83,7 +83,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS4212_CPU_ID, .idcode = EXYNOS4212_CPU_ID,
.idmask = EXYNOS4_CPU_MASK, .idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io, .map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts, .init_uarts = exynos4_init_uarts,
.init = exynos_init, .init = exynos_init,
.name = name_exynos4212, .name = name_exynos4212,
...@@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = { ...@@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS4412_CPU_ID, .idcode = EXYNOS4412_CPU_ID,
.idmask = EXYNOS4_CPU_MASK, .idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io, .map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts, .init_uarts = exynos4_init_uarts,
.init = exynos_init, .init = exynos_init,
.name = name_exynos4412, .name = name_exynos4412,
...@@ -99,7 +97,6 @@ static struct cpu_table cpu_ids[] __initdata = { ...@@ -99,7 +97,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS5250_SOC_ID, .idcode = EXYNOS5250_SOC_ID,
.idmask = EXYNOS5_SOC_MASK, .idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io, .map_io = exynos5_map_io,
.init_clocks = exynos5_init_clocks,
.init = exynos_init, .init = exynos_init,
.name = name_exynos5250, .name = name_exynos5250,
}, { }, {
...@@ -397,43 +394,26 @@ static void __init exynos5_map_io(void) ...@@ -397,43 +394,26 @@ static void __init exynos5_map_io(void)
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
} }
static void __init exynos4_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
if (soc_is_exynos4210())
exynos4210_register_clocks();
else if (soc_is_exynos4212() || soc_is_exynos4412())
exynos4212_register_clocks();
exynos4_register_clocks();
exynos4_setup_clocks();
}
static void __init exynos5440_map_io(void) static void __init exynos5440_map_io(void)
{ {
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0)); iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
} }
static void __init exynos5_init_clocks(int xtal) void __init exynos_init_time(void)
{ {
printk(KERN_DEBUG "%s: initializing clocks\n", __func__); if (of_have_populated_dt()) {
#ifdef CONFIG_OF
/* EXYNOS5440 can support only common clock framework */ of_clk_init(NULL);
clocksource_of_init();
if (soc_is_exynos5440()) #endif
return; } else {
/* todo: remove after migrating legacy E4 platforms to dt */
#ifdef CONFIG_SOC_EXYNOS5250 #ifdef CONFIG_ARCH_EXYNOS4
s3c24xx_register_baseclocks(xtal); exynos4_clk_init(NULL);
s5p_register_clocks(xtal); exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
exynos5_register_clocks();
exynos5_setup_clocks();
#endif #endif
mct_init();
}
} }
void __init exynos4_init_irq(void) void __init exynos4_init_irq(void)
......
...@@ -12,7 +12,11 @@ ...@@ -12,7 +12,11 @@
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
#include <linux/of.h>
extern void mct_init(void); extern void mct_init(void);
void exynos_init_time(void);
extern unsigned long xxti_f, xusbxti_f;
struct map_desc; struct map_desc;
void exynos_init_io(struct map_desc *mach_desc, int size); void exynos_init_io(struct map_desc *mach_desc, int size);
...@@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd); ...@@ -22,6 +26,10 @@ void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd); void exynos5_restart(char mode, const char *cmd);
void exynos_init_late(void); void exynos_init_late(void);
/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
void exynos4_clk_init(struct device_node *np);
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
#ifdef CONFIG_PM_GENERIC_DOMAINS #ifdef CONFIG_PM_GENERIC_DOMAINS
int exynos_pm_late_initcall(void); int exynos_pm_late_initcall(void);
#else #else
......
...@@ -256,113 +256,6 @@ ...@@ -256,113 +256,6 @@
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
/* For EXYNOS5250 */
#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
/* Compatibility defines and inclusion */ /* Compatibility defines and inclusion */
#include <mach/regs-pmu.h> #include <mach/regs-pmu.h>
......
...@@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void) ...@@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
static void __init armlex4210_map_io(void) static void __init armlex4210_map_io(void)
{ {
exynos_init_io(NULL, 0); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(armlex4210_uartcfgs, s3c24xx_init_uarts(armlex4210_uartcfgs,
ARRAY_SIZE(armlex4210_uartcfgs)); ARRAY_SIZE(armlex4210_uartcfgs));
} }
...@@ -202,6 +201,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210") ...@@ -202,6 +201,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
.map_io = armlex4210_map_io, .map_io = armlex4210_map_io,
.init_machine = armlex4210_machine_init, .init_machine = armlex4210_machine_init,
.init_late = exynos_init_late, .init_late = exynos_init_late,
.init_time = mct_init, .init_time = exynos_init_time,
.restart = exynos4_restart, .restart = exynos4_restart,
MACHINE_END MACHINE_END
...@@ -11,122 +11,26 @@ ...@@ -11,122 +11,26 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <linux/kernel.h>
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/of_fdt.h>
#include <linux/serial_core.h> #include <linux/serial_core.h>
#include <linux/memblock.h>
#include <linux/clocksource.h> #include <linux/clocksource.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <mach/map.h> #include <plat/mfc.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
#include "common.h" #include "common.h"
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
* device tree support addition for the Exynos4 architecture.
*
* For drivers that require platform data to be provided from the machine
* file, a platform data pointer can also be supplied along with the
* devices names. Usually, the platform data elements that cannot be parsed
* from the device tree by the drivers (example: function pointers) are
* supplied. But it should be noted that this is a temporary mechanism and
* at some point, the drivers should be capable of parsing all the platform
* data from the device tree.
*/
static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
"exynos4210-uart.0", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
"exynos4210-uart.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
"exynos4210-uart.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
"exynos4210-uart.3", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
"exynos4-sdhci.0", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
"exynos4-sdhci.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
"exynos4-sdhci.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
"exynos4-sdhci.3", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
"s3c2440-i2c.0", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
"s3c2440-i2c.1", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
"s3c2440-i2c.2", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
"s3c2440-i2c.3", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
"s3c2440-i2c.4", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
"s3c2440-i2c.5", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
"s3c2440-i2c.6", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
"s3c2440-i2c.7", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
"exynos4210-spi.0", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
"exynos4210-spi.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
"exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
"exynos-tmu", NULL),
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
"exynos-sysmmu.0", NULL), /* MFC_L */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
"exynos-sysmmu.1", NULL), /* MFC_R */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
"exynos-sysmmu.2", NULL), /* TV */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
"exynos-sysmmu.3", NULL), /* JPEG */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
"exynos-sysmmu.4", NULL), /* ROTATOR */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
"exynos-sysmmu.5", NULL), /* FIMC0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
"exynos-sysmmu.6", NULL), /* FIMC1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
"exynos-sysmmu.7", NULL), /* FIMC2 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
"exynos-sysmmu.8", NULL), /* FIMC3 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
"exynos-sysmmu.9", NULL), /* G2D(4210) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
"exynos-sysmmu.9", NULL), /* G2D(4x12) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
"exynos-sysmmu.10", NULL), /* FIMD0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
"exynos-sysmmu.11", NULL), /* FIMD1(4210) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
"exynos-sysmmu.12", NULL), /* IS0(4x12) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
"exynos-sysmmu.13", NULL), /* IS1(4x12) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
"exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
"exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
{},
};
static void __init exynos4_dt_map_io(void) static void __init exynos4_dt_map_io(void)
{ {
exynos_init_io(NULL, 0); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
} }
static void __init exynos4_dt_machine_init(void) static void __init exynos4_dt_machine_init(void)
{ {
of_platform_populate(NULL, of_default_bus_match_table, of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
exynos4_auxdata_lookup, NULL);
} }
static char const *exynos4_dt_compat[] __initdata = { static char const *exynos4_dt_compat[] __initdata = {
...@@ -136,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = { ...@@ -136,6 +40,18 @@ static char const *exynos4_dt_compat[] __initdata = {
NULL NULL
}; };
static void __init exynos4_reserve(void)
{
#ifdef CONFIG_S5P_DEV_MFC
struct s5p_mfc_dt_meminfo mfc_mem;
/* Reserve memory for MFC only if it's available */
mfc_mem.compatible = "samsung,mfc-v5";
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
mfc_mem.lsize);
#endif
}
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */ /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
.smp = smp_ops(exynos_smp_ops), .smp = smp_ops(exynos_smp_ops),
...@@ -143,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") ...@@ -143,7 +59,8 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
.map_io = exynos4_dt_map_io, .map_io = exynos4_dt_map_io,
.init_machine = exynos4_dt_machine_init, .init_machine = exynos4_dt_machine_init,
.init_late = exynos_init_late, .init_late = exynos_init_late,
.init_time = clocksource_of_init, .init_time = exynos_init_time,
.dt_compat = exynos4_dt_compat, .dt_compat = exynos4_dt_compat,
.restart = exynos4_restart, .restart = exynos4_restart,
.reserve = exynos4_reserve,
MACHINE_END MACHINE_END
...@@ -11,152 +11,21 @@ ...@@ -11,152 +11,21 @@
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/of_fdt.h> #include <linux/of_fdt.h>
#include <linux/serial_core.h>
#include <linux/memblock.h> #include <linux/memblock.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/clocksource.h> #include <linux/clocksource.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <mach/map.h>
#include <mach/regs-pmu.h> #include <mach/regs-pmu.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/regs-serial.h>
#include <plat/mfc.h> #include <plat/mfc.h>
#include "common.h" #include "common.h"
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
* device tree support addition for the EXYNOS5 architecture.
*
* For drivers that require platform data to be provided from the machine
* file, a platform data pointer can also be supplied along with the
* devices names. Usually, the platform data elements that cannot be parsed
* from the device tree by the drivers (example: function pointers) are
* supplied. But it should be noted that this is a temporary mechanism and
* at some point, the drivers should be capable of parsing all the platform
* data from the device tree.
*/
static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
"exynos4210-uart.0", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
"exynos4210-uart.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
"exynos4210-uart.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
"exynos4210-uart.3", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
"s3c2440-i2c.0", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
"s3c2440-i2c.1", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
"s3c2440-i2c.2", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
"s3c2440-i2c.3", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
"s3c2440-i2c.4", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
"s3c2440-i2c.5", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
"s3c2440-i2c.6", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
"s3c2440-i2c.7", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
"s3c2440-hdmiphy-i2c", NULL),
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
"dw_mmc.0", NULL),
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
"dw_mmc.1", NULL),
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
"dw_mmc.2", NULL),
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
"dw_mmc.3", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
"exynos4210-spi.0", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
"exynos4210-spi.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
"exynos4210-spi.2", NULL),
OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
"exynos5-sata", NULL),
OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
"exynos5-sata-phy", NULL),
OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
"exynos5-sata-phy-i2c", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
"exynos-gsc.0", NULL),
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
"exynos-gsc.1", NULL),
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
"exynos-gsc.2", NULL),
OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
"exynos-gsc.3", NULL),
OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
"exynos5-hdmi", NULL),
OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
"exynos5-mixer", NULL),
OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
"exynos-tmu", NULL),
OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
"samsung-i2s.0", NULL),
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
"samsung-i2s.1", NULL),
OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
"samsung-i2s.2", NULL),
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
"exynos-sysmmu.0", "mfc"), /* MFC_L */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
"exynos-sysmmu.1", "mfc"), /* MFC_R */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
"exynos-sysmmu.2", NULL), /* TV */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
"exynos-sysmmu.3", "jpeg"), /* JPEG */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
"exynos-sysmmu.4", NULL), /* ROTATOR */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
"exynos-sysmmu.5", "gscl"), /* GSCL0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
"exynos-sysmmu.6", "gscl"), /* GSCL1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
"exynos-sysmmu.7", "gscl"), /* GSCL2 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
"exynos-sysmmu.8", "gscl"), /* GSCL3 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
"exynos-sysmmu.9", NULL), /* FIMC-IS0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
"exynos-sysmmu.10", NULL), /* FIMC-IS1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
"exynos-sysmmu.11", NULL), /* FIMD1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
"exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
"exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
"exynos-sysmmu.14", NULL), /* G2D */
{},
};
static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
"exynos4210-uart.0", NULL),
{},
};
static void __init exynos5_dt_map_io(void) static void __init exynos5_dt_map_io(void)
{ {
unsigned long root = of_get_flat_dt_root();
exynos_init_io(NULL, 0); exynos_init_io(NULL, 0);
if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
s3c24xx_init_clocks(24000000);
} }
static void __init exynos5_dt_machine_init(void) static void __init exynos5_dt_machine_init(void)
...@@ -183,12 +52,7 @@ static void __init exynos5_dt_machine_init(void) ...@@ -183,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
} }
} }
if (of_machine_is_compatible("samsung,exynos5250")) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
else if (of_machine_is_compatible("samsung,exynos5440"))
of_platform_populate(NULL, of_default_bus_match_table,
exynos5440_auxdata_lookup, NULL);
} }
static char const *exynos5_dt_compat[] __initdata = { static char const *exynos5_dt_compat[] __initdata = {
...@@ -217,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") ...@@ -217,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
.map_io = exynos5_dt_map_io, .map_io = exynos5_dt_map_io,
.init_machine = exynos5_dt_machine_init, .init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late, .init_late = exynos_init_late,
.init_time = clocksource_of_init, .init_time = exynos_init_time,
.dt_compat = exynos5_dt_compat, .dt_compat = exynos5_dt_compat,
.restart = exynos5_restart, .restart = exynos5_restart,
.reserve = exynos5_reserve, .reserve = exynos5_reserve,
......
...@@ -1330,8 +1330,9 @@ static struct platform_device *nuri_devices[] __initdata = { ...@@ -1330,8 +1330,9 @@ static struct platform_device *nuri_devices[] __initdata = {
static void __init nuri_map_io(void) static void __init nuri_map_io(void)
{ {
exynos_init_io(NULL, 0); exynos_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs)); s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
xxti_f = 0;
xusbxti_f = 24000000;
} }
static void __init nuri_reserve(void) static void __init nuri_reserve(void)
...@@ -1380,7 +1381,7 @@ MACHINE_START(NURI, "NURI") ...@@ -1380,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
.map_io = nuri_map_io, .map_io = nuri_map_io,
.init_machine = nuri_machine_init, .init_machine = nuri_machine_init,
.init_late = exynos_init_late, .init_late = exynos_init_late,
.init_time = mct_init, .init_time = exynos_init_time,
.reserve = &nuri_reserve, .reserve = &nuri_reserve,
.restart = exynos4_restart, .restart = exynos4_restart,
MACHINE_END MACHINE_END
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