Commit 1a6ea3ec authored by Ralf Baechle's avatar Ralf Baechle

[MIPS] SEAD: More build fixes.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 09b696ef
......@@ -30,19 +30,9 @@
extern asmlinkage void mipsIRQ(void);
asmlinkage void sead_hw0_irqdispatch(struct pt_regs *regs)
{
do_IRQ(SEADINT_UART0, regs);
}
asmlinkage void sead_hw1_irqdispatch(struct pt_regs *regs)
{
do_IRQ(SEADINT_UART1, regs);
}
void __init arch_init_irq(void)
{
mips_cpu_irq_init(0);
mips_cpu_irq_init(MIPSCPU_INT_BASE);
/* Now safe to set the exception vector. */
set_except_vector(0, mipsIRQ);
......
......@@ -45,7 +45,7 @@ const char *get_system_type(void)
return "MIPS SEAD";
}
static void __init sead_setup(void)
void __init plat_setup(void)
{
ioport_resource.end = 0x7fffffff;
......@@ -69,7 +69,7 @@ static void __init serial_init(void)
#else
s.iobase = SEAD_UART0_REGS_BASE+3;
#endif
s.irq = SEADINT_UART0;
s.irq = MIPSCPU_INT_BASE + MIPSCPU_INT_UART0;
s.uartclk = SEAD_BASE_BAUD * 16;
s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ;
s.iotype = 0;
......
......@@ -20,7 +20,14 @@
#ifndef _MIPS_SEADINT_H
#define _MIPS_SEADINT_H
#define SEADINT_UART0 2
#define SEADINT_UART1 3
/*
* Interrupts 0..7 are used for SEAD CPU interrupts
*/
#define MIPSCPU_INT_BASE 0
#define MIPSCPU_INT_UART0 2
#define MIPSCPU_INT_UART1 3
#define MIPSCPU_INT_CPUCTR 7
#endif /* !(_MIPS_SEADINT_H) */
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