Commit 1bf79102 authored by Lubomir Rintel's avatar Lubomir Rintel Committed by Greg Kroah-Hartman

irqchip/mmp: Only touch the PJ4 IRQ & FIQ bits on enable/disable

[ Upstream commit 2380a22b ]

Resetting bit 4 disables the interrupt delivery to the "secure
processor" core. This breaks the keyboard on a OLPC XO 1.75 laptop,
where the firmware running on the "secure processor" bit-bangs the
PS/2 protocol over the GPIO lines.

It is not clear what the rest of the bits are and Marvell was unhelpful
when asked for documentation. Aside from the SP bit, there are probably
priority bits.

Leaving the unknown bits as the firmware set them up seems to be a wiser
course of action compared to just turning them off.
Signed-off-by: default avatarLubomir Rintel <lkundrak@v3.sk>
Acked-by: default avatarPavel Machek <pavel@ucw.cz>
[maz: fixed-up subject and commit message]
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 423869f8
...@@ -34,6 +34,9 @@ ...@@ -34,6 +34,9 @@
#define SEL_INT_PENDING (1 << 6) #define SEL_INT_PENDING (1 << 6)
#define SEL_INT_NUM_MASK 0x3f #define SEL_INT_NUM_MASK 0x3f
#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5)
#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6)
struct icu_chip_data { struct icu_chip_data {
int nr_irqs; int nr_irqs;
unsigned int virq_base; unsigned int virq_base;
...@@ -190,7 +193,8 @@ static const struct mmp_intc_conf mmp_conf = { ...@@ -190,7 +193,8 @@ static const struct mmp_intc_conf mmp_conf = {
static const struct mmp_intc_conf mmp2_conf = { static const struct mmp_intc_conf mmp2_conf = {
.conf_enable = 0x20, .conf_enable = 0x20,
.conf_disable = 0x0, .conf_disable = 0x0,
.conf_mask = 0x7f, .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ |
MMP2_ICU_INT_ROUTE_PJ4_FIQ,
}; };
static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs) static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
......
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