Commit 1c4ecf48 authored by Trigger Huang's avatar Trigger Huang Committed by Alex Deucher

drm/amdgpu: Fix module unload hang by KIQ on Vega10

Apply commit 4e683cb2644f ("drm/amdgpu: Fix module unload hang by
KIQ IRQ set")to vega10
V2:
	delete reduant kiq irq funcs type check (suggested by Rex.Zhu)
Signed-off-by: default avatarTrigger Huang <trigger.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7ef69843
...@@ -631,7 +631,6 @@ static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev, ...@@ -631,7 +631,6 @@ static int gfx_v9_0_kiq_init_ring(struct amdgpu_device *adev,
ring->pipe = 1; ring->pipe = 1;
} }
irq->data = ring;
ring->queue = 0; ring->queue = 0;
ring->eop_gpu_addr = kiq->eop_gpu_addr; ring->eop_gpu_addr = kiq->eop_gpu_addr;
sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue); sprintf(ring->name, "kiq %d.%d.%d", ring->me, ring->pipe, ring->queue);
...@@ -647,7 +646,6 @@ static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring, ...@@ -647,7 +646,6 @@ static void gfx_v9_0_kiq_free_ring(struct amdgpu_ring *ring,
{ {
amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs); amdgpu_wb_free(ring->adev, ring->adev->virt.reg_val_offs);
amdgpu_ring_fini(ring); amdgpu_ring_fini(ring);
irq->data = NULL;
} }
/* create MQD for each compute queue */ /* create MQD for each compute queue */
...@@ -3370,9 +3368,7 @@ static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev, ...@@ -3370,9 +3368,7 @@ static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
enum amdgpu_interrupt_state state) enum amdgpu_interrupt_state state)
{ {
uint32_t tmp, target; uint32_t tmp, target;
struct amdgpu_ring *ring = (struct amdgpu_ring *)src->data; struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
if (ring->me == 1) if (ring->me == 1)
target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
...@@ -3416,9 +3412,7 @@ static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev, ...@@ -3416,9 +3412,7 @@ static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
struct amdgpu_iv_entry *entry) struct amdgpu_iv_entry *entry)
{ {
u8 me_id, pipe_id, queue_id; u8 me_id, pipe_id, queue_id;
struct amdgpu_ring *ring = (struct amdgpu_ring *)source->data; struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
BUG_ON(!ring || (ring->funcs->type != AMDGPU_RING_TYPE_KIQ));
me_id = (entry->ring_id & 0x0c) >> 2; me_id = (entry->ring_id & 0x0c) >> 2;
pipe_id = (entry->ring_id & 0x03) >> 0; pipe_id = (entry->ring_id & 0x03) >> 0;
......
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