Commit 1c7cbd63 authored by Richard Weinberger's avatar Richard Weinberger

Merge tag 'nand/for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next

NAND core changes:
- Support having the bad block markers in either the first, second or
  last page of a block. The combination of all three location is now
  possible.
- Constification of NAND_OP_PARSER(_PATTERN) elements.
- Generic NAND DT bindings changed to yaml format (can be used to
  check the proposed bindings. First platform to be fully supported:
  sunxi.
- Stopped using several legacy hooks.
- Preparation to use the generic NAND layer with the addition of
  several helpers and the removal of the struct nand_chip from generic
  functions.
- Kconfig cleanup to prepare the introduction of external ECC engines
  support.
- Fallthrough comments.
- Introduction of the SPI-mem dirmap API for SPI-NAND devices.

Raw NAND controller drivers changes:
- nandsim:
  * Switch to ->exec-op().
- meson:
  * Misc cleanups and fixes.
  * New OOB layout.
- Sunxi:
  * A23/A33 NAND DMA support.
- Ingenic:
  * Full reorganization and cleanup.
  * Clear separation between NAND controller and ECC engine.
  * Support JZ4740 an JZ4725B.
- Denali:
  * Clear controller/chip separation.
  * ->exec_op() migration.
  * Various cleanups.
- fsl_elbc:
  * Enable software ECC support.
- Atmel:
  * Sam9x60 support.
- GPMI:
  * Introduce the GPMI_IS_MXS() macro.
- Various trivial/spelling/coding style fixes.
parents 37624b58 1c14fe21
...@@ -15,6 +15,7 @@ Required properties: ...@@ -15,6 +15,7 @@ Required properties:
"atmel,at91sam9g45-ebi" "atmel,at91sam9g45-ebi"
"atmel,at91sam9x5-ebi" "atmel,at91sam9x5-ebi"
"atmel,sama5d3-ebi" "atmel,sama5d3-ebi"
"microchip,sam9x60-ebi"
- reg: Contains offset/length value for EBI memory mapping. - reg: Contains offset/length value for EBI memory mapping.
This property might contain several entries if the EBI This property might contain several entries if the EBI
......
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 NAND Controller Device Tree Bindings
allOf:
- $ref: "nand-controller.yaml"
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <maxime.ripard@bootlin.com>
properties:
"#address-cells": true
"#size-cells": true
compatible:
enum:
- allwinner,sun4i-a10-nand
- allwinner,sun8i-a23-nand-controller
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
clock-names:
items:
- const: ahb
- const: mod
resets:
maxItems: 1
reset-names:
const: ahb
dmas:
maxItems: 1
dma-names:
const: rxtx
pinctrl-names: true
patternProperties:
"^pinctrl-[0-9]+$": true
"^nand@[a-f0-9]+$":
properties:
reg:
maxItems: 1
minimum: 0
maximum: 7
nand-ecc-mode: true
nand-ecc-algo:
const: bch
nand-ecc-step-size:
enum: [ 512, 1024 ]
nand-ecc-strength:
maximum: 80
allwinner,rb:
description:
Contains the native Ready/Busy IDs.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- minItems: 1
maxItems: 2
items:
minimum: 0
maximum: 1
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
...
...@@ -14,6 +14,7 @@ Required properties: ...@@ -14,6 +14,7 @@ Required properties:
"atmel,at91sam9261-nand-controller" "atmel,at91sam9261-nand-controller"
"atmel,at91sam9g45-nand-controller" "atmel,at91sam9g45-nand-controller"
"atmel,sama5d3-nand-controller" "atmel,sama5d3-nand-controller"
"microchip,sam9x60-nand-controller"
- ranges: empty ranges property to forward EBI ranges definitions. - ranges: empty ranges property to forward EBI ranges definitions.
- #address-cells: should be set to 2. - #address-cells: should be set to 2.
- #size-cells: should be set to 1. - #size-cells: should be set to 1.
......
...@@ -7,34 +7,48 @@ Required properties: ...@@ -7,34 +7,48 @@ Required properties:
"socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b) "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
- reg : should contain registers location and length for data and reg. - reg : should contain registers location and length for data and reg.
- reg-names: Should contain the reg names "nand_data" and "denali_reg" - reg-names: Should contain the reg names "nand_data" and "denali_reg"
- #address-cells: should be 1. The cell encodes the chip select connection.
- #size-cells : should be 0.
- interrupts : The interrupt number. - interrupts : The interrupt number.
- clocks: should contain phandle of the controller core clock, the bus - clocks: should contain phandle of the controller core clock, the bus
interface clock, and the ECC circuit clock. interface clock, and the ECC circuit clock.
- clock-names: should contain "nand", "nand_x", "ecc" - clock-names: should contain "nand", "nand_x", "ecc"
Optional properties: Sub-nodes:
- nand-ecc-step-size: see nand.txt for details. If present, the value must be Sub-nodes represent available NAND chips.
512 for "altr,socfpga-denali-nand"
1024 for "socionext,uniphier-denali-nand-v5a" Required properties:
1024 for "socionext,uniphier-denali-nand-v5b" - reg: should contain the bank ID of the controller to which each chip
- nand-ecc-strength: see nand.txt for details. Valid values are: select is connected.
8, 15 for "altr,socfpga-denali-nand"
8, 16, 24 for "socionext,uniphier-denali-nand-v5a" Optional properties:
8, 16 for "socionext,uniphier-denali-nand-v5b" - nand-ecc-step-size: see nand.txt for details.
- nand-ecc-maximize: see nand.txt for details If present, the value must be
512 for "altr,socfpga-denali-nand"
The device tree may optionally contain sub-nodes describing partitions of the 1024 for "socionext,uniphier-denali-nand-v5a"
1024 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-strength: see nand.txt for details. Valid values are:
8, 15 for "altr,socfpga-denali-nand"
8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
8, 16 for "socionext,uniphier-denali-nand-v5b"
- nand-ecc-maximize: see nand.txt for details
The chip nodes may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail. address space. See partition.txt for more detail.
Examples: Examples:
nand: nand@ff900000 { nand: nand@ff900000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <0>;
compatible = "altr,socfpga-denali-nand"; compatible = "altr,socfpga-denali-nand";
reg = <0xff900000 0x20>, <0xffb80000 0x1000>; reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg"; reg-names = "nand_data", "denali_reg";
clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
clock-names = "nand", "nand_x", "ecc"; clock-names = "nand", "nand_x", "ecc";
interrupts = <0 144 4>; interrupts = <0 144 4>;
nand@0 {
reg = <0>;
}
}; };
* Ingenic JZ4780 NAND/BCH * Ingenic JZ4780 NAND/ECC
This file documents the device tree bindings for NAND flash devices on the This file documents the device tree bindings for NAND flash devices on the
JZ4780. NAND devices are connected to the NEMC controller (described in JZ4780. NAND devices are connected to the NEMC controller (described in
...@@ -6,15 +6,18 @@ memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must ...@@ -6,15 +6,18 @@ memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
be children of the NEMC node. be children of the NEMC node.
Required NAND controller device properties: Required NAND controller device properties:
- compatible: Should be set to "ingenic,jz4780-nand". - compatible: Should be one of:
* ingenic,jz4740-nand
* ingenic,jz4725b-nand
* ingenic,jz4780-nand
- reg: For each bank with a NAND chip attached, should specify a bank number, - reg: For each bank with a NAND chip attached, should specify a bank number,
an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank). an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
Optional NAND controller device properties: Optional NAND controller device properties:
- ingenic,bch-controller: To make use of the hardware BCH controller, this - ecc-engine: To make use of the hardware ECC controller, this
property must contain a phandle for the BCH controller node. The required property must contain a phandle for the ECC controller node. The required
properties for this node are described below. If this is not specified, properties for this node are described below. If this is not specified,
software BCH will be used instead. software ECC will be used instead.
Optional children nodes: Optional children nodes:
- Individual NAND chips are children of the NAND controller node. - Individual NAND chips are children of the NAND controller node.
...@@ -45,7 +48,7 @@ nemc: nemc@13410000 { ...@@ -45,7 +48,7 @@ nemc: nemc@13410000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
ingenic,bch-controller = <&bch>; ecc-engine = <&bch>;
nand@1 { nand@1 {
reg = <1>; reg = <1>;
...@@ -67,14 +70,17 @@ nemc: nemc@13410000 { ...@@ -67,14 +70,17 @@ nemc: nemc@13410000 {
}; };
}; };
The BCH controller is a separate SoC component used for error correction on The ECC controller is a separate SoC component used for error correction on
NAND devices. The following is a description of the device properties for a NAND devices. The following is a description of the device properties for a
BCH controller. ECC controller.
Required BCH properties: Required ECC properties:
- compatible: Should be set to "ingenic,jz4780-bch". - compatible: Should be one of:
- reg: Should specify the BCH controller registers location and length. * ingenic,jz4740-ecc
- clocks: Clock for the BCH controller. * ingenic,jz4725b-bch
* ingenic,jz4780-bch
- reg: Should specify the ECC controller registers location and length.
- clocks: Clock for the ECC controller.
Example: Example:
......
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NAND Chip and NAND Controller Generic Binding
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Richard Weinberger <richard@nod.at>
description: |
The NAND controller should be represented with its own DT node, and
all NAND chips attached to this controller should be defined as
children nodes of the NAND controller. This representation should be
enforced even for simple controllers supporting only one chip.
The ECC strength and ECC step size properties define the user
desires in terms of correction capability of a controller. Together,
they request the ECC engine to correct {strength} bit errors per
{size} bytes.
The interpretation of these parameters is implementation-defined, so
not all implementations must support all possible
combinations. However, implementations are encouraged to further
specify the value(s) they support.
properties:
$nodename:
pattern: "^nand-controller(@.*)?"
"#address-cells":
const: 1
"#size-cells":
const: 0
ranges: true
patternProperties:
"^nand@[a-f0-9]$":
properties:
reg:
description:
Contains the native Ready/Busy IDs.
nand-ecc-mode:
allOf:
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
description:
Desired ECC engine, either hardware (most of the time
embedded in the NAND controller) or software correction
(Linux will handle the calculations). soft_bch is deprecated
and should be replaced by soft and nand-ecc-algo.
nand-ecc-algo:
allOf:
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ hamming, bch, rs ]
description:
Desired ECC algorithm.
nand-bus-width:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 8, 16 ]
- default: 8
description:
Bus width to the NAND chip
nand-on-flash-bbt:
$ref: /schemas/types.yaml#/definitions/flag
description:
With this property, the OS will search the device for a Bad
Block Table (BBT). If not found, it will create one, reserve
a few blocks at the end of the device to store it and update
it as the device ages. Otherwise, the out-of-band area of a
few pages of all the blocks will be scanned at boot time to
find Bad Block Markers (BBM). These markers will help to
build a volatile BBT in RAM.
nand-ecc-strength:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 1
description:
Maximum number of bits that can be corrected per ECC step.
nand-ecc-step-size:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- minimum: 1
description:
Number of data bytes covered by a single ECC step.
nand-ecc-maximize:
$ref: /schemas/types.yaml#/definitions/flag
description:
Whether or not the ECC strength should be maximized. The
maximum ECC strength is both controller and chip
dependent. The ECC engine has to select the ECC config
providing the best strength and taking the OOB area size
constraint into account. This is particularly useful when
only the in-band area is used by the upper layers, and you
want to make your NAND as reliable as possible.
nand-is-boot-medium:
$ref: /schemas/types.yaml#/definitions/flag
description:
Whether or not the NAND chip is a boot medium. Drivers might
use this information to select ECC algorithms supported by
the boot ROM or similar restrictions.
nand-rb:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Contains the native Ready/Busy IDs.
required:
- reg
required:
- "#address-cells"
- "#size-cells"
examples:
- |
nand-controller {
#address-cells = <1>;
#size-cells = <0>;
/* controller specific properties */
nand@0 {
reg = <0>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
/* controller specific properties */
};
};
* NAND chip and NAND controller generic binding
NAND controller/NAND chip representation:
The NAND controller should be represented with its own DT node, and all
NAND chips attached to this controller should be defined as children nodes
of the NAND controller. This representation should be enforced even for
simple controllers supporting only one chip.
Mandatory NAND controller properties:
- #address-cells: depends on your controller. Should at least be 1 to
encode the CS line id.
- #size-cells: depends on your controller. Put zero unless you need a
mapping between CS lines and dedicated memory regions
Optional NAND controller properties
- ranges: only needed if you need to define a mapping between CS lines and
memory regions
Optional NAND chip properties:
- nand-ecc-mode : String, operation mode of the NAND ecc mode.
Supported values are: "none", "soft", "hw", "hw_syndrome",
"hw_oob_first", "on-die".
Deprecated values:
"soft_bch": use "soft" and nand-ecc-algo instead
- nand-ecc-algo: string, algorithm of NAND ECC.
Valid values are: "hamming", "bch", "rs".
- nand-bus-width : 8 or 16 bus width if not present 8
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
- nand-ecc-strength: integer representing the number of bits to correct
per ECC step.
- nand-ecc-step-size: integer representing the number of data bytes
that are covered by a single ECC step.
- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
strength. The maximum ECC strength is both controller and
chip dependent. The controller side has to select the ECC
config providing the best strength and taking the OOB area
size constraint into account.
This is particularly useful when only the in-band area is
used by the upper layers, and you want to make your NAND
as reliable as possible.
- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might use
this information to select ECC algorithms supported by
the boot ROM or similar restrictions.
- nand-rb: shall contain the native Ready/Busy ids.
The ECC strength and ECC step size properties define the correction capability
of a controller. Together, they say a controller can correct "{strength} bit
errors per {size} bytes".
The interpretation of these parameters is implementation-defined, so not all
implementations must support all possible combinations. However, implementations
are encouraged to further specify the value(s) they support.
Example:
nand-controller {
#address-cells = <1>;
#size-cells = <0>;
/* controller specific properties */
nand@0 {
reg = <0>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
/* controller specific properties */
};
};
Allwinner NAND Flash Controller (NFC)
Required properties:
- compatible : "allwinner,sun4i-a10-nand".
- reg : shall contain registers location and length for data and reg.
- interrupts : shall define the nand controller interrupt.
- #address-cells: shall be set to 1. Encode the nand CS.
- #size-cells : shall be set to 0.
- clocks : shall reference nand controller clocks.
- clock-names : nand controller internal clock names. Shall contain :
* "ahb" : AHB gating clock
* "mod" : nand controller clock
Optional properties:
- dmas : shall reference DMA channel associated to the NAND controller.
- dma-names : shall be "rxtx".
Optional children nodes:
Children nodes represent the available nand chips.
Optional properties:
- reset : phandle + reset specifier pair
- reset-names : must contain "ahb"
- allwinner,rb : shall contain the native Ready/Busy ids.
- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
"none")
see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
Examples:
nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <0 37 1>;
clocks = <&ahb_gates 13>, <&nand_clk>;
clock-names = "ahb", "mod";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
nand@0 {
reg = <0>;
allwinner,rb = <0>;
nand-ecc-mode = "soft_bch";
};
};
...@@ -56,7 +56,7 @@ CONFIG_MTD=y ...@@ -56,7 +56,7 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_GLUEBI=y
......
...@@ -36,7 +36,7 @@ CONFIG_MTD_CFI_INTELEXT=y ...@@ -36,7 +36,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PLATRAM=y CONFIG_MTD_PLATRAM=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=y CONFIG_MTD_NAND_GPIO=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
# CONFIG_NET_CADENCE is not set # CONFIG_NET_CADENCE is not set
......
...@@ -58,7 +58,7 @@ CONFIG_MTD_CFI_AMDSTD=y ...@@ -58,7 +58,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=y CONFIG_MTD_PXA2XX=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=m CONFIG_MTD_NAND_GPIO=m
CONFIG_MTD_NAND_CM_X270=y CONFIG_MTD_NAND_CM_X270=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
......
...@@ -48,7 +48,7 @@ CONFIG_LIB80211=m ...@@ -48,7 +48,7 @@ CONFIG_LIB80211=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
......
...@@ -64,7 +64,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y ...@@ -64,7 +64,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=y CONFIG_MTD_PXA2XX=y
CONFIG_MTD_BLOCK2MTD=y CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DISKONCHIP=y CONFIG_MTD_NAND_DISKONCHIP=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000 CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
......
...@@ -87,7 +87,7 @@ CONFIG_MTD_CMDLINE_PARTS=y ...@@ -87,7 +87,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_ROM=y CONFIG_MTD_ROM=y
CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SHARPSL=y CONFIG_MTD_NAND_SHARPSL=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
......
...@@ -74,7 +74,7 @@ CONFIG_MTD_CFI_INTELEXT=m ...@@ -74,7 +74,7 @@ CONFIG_MTD_CFI_INTELEXT=m
CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_AMDSTD=m
CONFIG_MTD_PHYSMAP=m CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_M25P80=m CONFIG_MTD_M25P80=m
CONFIG_MTD_NAND=m CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_DAVINCI=m CONFIG_MTD_NAND_DAVINCI=m
CONFIG_MTD_SPI_NOR=m CONFIG_MTD_SPI_NOR=m
CONFIG_MTD_UBI=m CONFIG_MTD_UBI=m
......
...@@ -54,7 +54,7 @@ CONFIG_MTD_CFI_AMDSTD=y ...@@ -54,7 +54,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PXA2XX=y CONFIG_MTD_PXA2XX=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -63,7 +63,7 @@ CONFIG_MTD_CFI_AMDSTD=y ...@@ -63,7 +63,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_ROM=y CONFIG_MTD_ROM=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_BLK_DEV_NBD=y CONFIG_BLK_DEV_NBD=y
CONFIG_EEPROM_LEGACY=y CONFIG_EEPROM_LEGACY=y
CONFIG_SCSI=y CONFIG_SCSI=y
......
...@@ -43,7 +43,7 @@ CONFIG_MAC80211_RC_PID=y ...@@ -43,7 +43,7 @@ CONFIG_MAC80211_RC_PID=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set # CONFIG_STANDALONE is not set
CONFIG_MTD=m CONFIG_MTD=m
CONFIG_MTD_NAND=m CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_TMIO=m CONFIG_MTD_NAND_TMIO=m
CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_LOOP=m
# CONFIG_SCSI_PROC_FS is not set # CONFIG_SCSI_PROC_FS is not set
......
...@@ -61,7 +61,7 @@ CONFIG_MTD_CFI_GEOMETRY=y ...@@ -61,7 +61,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_I2 is not set # CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MXC=y CONFIG_MTD_NAND_MXC=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT24=y
......
...@@ -110,7 +110,7 @@ CONFIG_MTD_PHYSMAP_OF=y ...@@ -110,7 +110,7 @@ CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_DATAFLASH=y CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_VF610_NFC=y CONFIG_MTD_NAND_VF610_NFC=y
CONFIG_MTD_NAND_MXC=y CONFIG_MTD_NAND_MXC=y
......
...@@ -112,7 +112,7 @@ CONFIG_MTD_CFI=y ...@@ -112,7 +112,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_IXP4XX=y CONFIG_MTD_IXP4XX=y
CONFIG_MTD_NAND=m CONFIG_MTD_RAW_NAND=m
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_RAM_SIZE=8192
......
...@@ -124,7 +124,7 @@ CONFIG_MTD_CMDLINE_PARTS=y ...@@ -124,7 +124,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_PLATRAM=y CONFIG_MTD_PLATRAM=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DAVINCI=y CONFIG_MTD_NAND_DAVINCI=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
......
...@@ -47,7 +47,7 @@ CONFIG_DEVTMPFS_MOUNT=y ...@@ -47,7 +47,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SLC_LPC32XX=y CONFIG_MTD_NAND_SLC_LPC32XX=y
CONFIG_MTD_NAND_MLC_LPC32XX=y CONFIG_MTD_NAND_MLC_LPC32XX=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
......
...@@ -92,7 +92,7 @@ CONFIG_MTD_CFI_AMDSTD=y ...@@ -92,7 +92,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_RAM=y CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=y CONFIG_MTD_ROM=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_S3C2410=y CONFIG_MTD_NAND_S3C2410=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_LPDDR=y CONFIG_MTD_LPDDR=y
......
...@@ -28,7 +28,7 @@ CONFIG_IP_PNP=y ...@@ -28,7 +28,7 @@ CONFIG_IP_PNP=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_GENERIC=y CONFIG_MTD_ONENAND_GENERIC=y
# CONFIG_BLK_DEV is not set # CONFIG_BLK_DEV is not set
......
...@@ -39,7 +39,7 @@ CONFIG_MTD_CFI_INTELEXT=y ...@@ -39,7 +39,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PLATRAM=y CONFIG_MTD_PLATRAM=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=y CONFIG_MTD_NAND_GPIO=y
# CONFIG_INPUT is not set # CONFIG_INPUT is not set
# CONFIG_SERIO is not set # CONFIG_SERIO is not set
......
...@@ -87,7 +87,7 @@ CONFIG_MTD_CFI_GEOMETRY=y ...@@ -87,7 +87,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_ORION=y CONFIG_MTD_NAND_ORION=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
......
...@@ -184,7 +184,7 @@ CONFIG_MTD=y ...@@ -184,7 +184,7 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_OMAP2=y CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_MTD_NAND_OMAP_BCH=y
......
...@@ -47,7 +47,7 @@ CONFIG_MTD_CFI_GEOMETRY=y ...@@ -47,7 +47,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ORION=y CONFIG_MTD_NAND_ORION=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
# CONFIG_SCSI_PROC_FS is not set # CONFIG_SCSI_PROC_FS is not set
......
...@@ -77,7 +77,7 @@ CONFIG_MTD_CFI_INTELEXT=y ...@@ -77,7 +77,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ORION=y CONFIG_MTD_NAND_ORION=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
......
...@@ -52,7 +52,7 @@ CONFIG_MTD_CFI_AMDSTD=y ...@@ -52,7 +52,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
......
...@@ -50,7 +50,7 @@ CONFIG_MTD_BLOCK=y ...@@ -50,7 +50,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPMI_NAND=y CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
......
...@@ -53,8 +53,8 @@ CONFIG_MTD_BLOCK=y ...@@ -53,8 +53,8 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_GENERIC=y CONFIG_MTD_ONENAND_GENERIC=y
CONFIG_MTD_NAND_ECC_SMC=y CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y
......
...@@ -90,7 +90,7 @@ CONFIG_MTD_CMDLINE_PARTS=y ...@@ -90,7 +90,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=2 CONFIG_BLK_DEV_RAM_COUNT=2
......
...@@ -143,8 +143,8 @@ CONFIG_MTD_M25P80=m ...@@ -143,8 +143,8 @@ CONFIG_MTD_M25P80=m
CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y
CONFIG_MTD_ONENAND_OMAP2=y CONFIG_MTD_ONENAND_OMAP2=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ECC_BCH=y CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_OMAP2=y CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_MTD_NAND_OMAP_BCH=y
CONFIG_MTD_SPI_NOR=m CONFIG_MTD_SPI_NOR=m
......
...@@ -70,7 +70,7 @@ CONFIG_MTD_CFI_GEOMETRY=y ...@@ -70,7 +70,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_ORION=y CONFIG_MTD_NAND_ORION=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
......
...@@ -50,7 +50,7 @@ CONFIG_SIMPLE_PM_BUS=y ...@@ -50,7 +50,7 @@ CONFIG_SIMPLE_PM_BUS=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_OXNAS=y CONFIG_MTD_NAND_OXNAS=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
......
...@@ -31,7 +31,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ...@@ -31,7 +31,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND=y
CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y
......
...@@ -185,8 +185,8 @@ CONFIG_MTD_PXA2XX=m ...@@ -185,8 +185,8 @@ CONFIG_MTD_PXA2XX=m
CONFIG_MTD_M25P80=m CONFIG_MTD_M25P80=m
CONFIG_MTD_BLOCK2MTD=y CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_DOCG3=m CONFIG_MTD_DOCG3=m
CONFIG_MTD_NAND=m CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_ECC_BCH=y CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_GPIO=m CONFIG_MTD_NAND_GPIO=m
CONFIG_MTD_NAND_DISKONCHIP=m CONFIG_MTD_NAND_DISKONCHIP=m
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
......
...@@ -57,7 +57,7 @@ CONFIG_DEVTMPFS_MOUNT=y ...@@ -57,7 +57,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
......
...@@ -192,7 +192,7 @@ CONFIG_MTD_JEDECPROBE=y ...@@ -192,7 +192,7 @@ CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ROM=y CONFIG_MTD_ROM=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_S3C2410=y CONFIG_MTD_NAND_S3C2410=y
CONFIG_PARPORT=y CONFIG_PARPORT=y
CONFIG_PARPORT_PC=m CONFIG_PARPORT_PC=m
......
...@@ -23,7 +23,7 @@ CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x5100 ...@@ -23,7 +23,7 @@ CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/linuxrc initrd=0x5100
CONFIG_VFP=y CONFIG_VFP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_S3C2410=y CONFIG_MTD_NAND_S3C2410=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -66,7 +66,7 @@ CONFIG_MTD_CMDLINE_PARTS=y ...@@ -66,7 +66,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
......
...@@ -51,7 +51,7 @@ CONFIG_DEVTMPFS_MOUNT=y ...@@ -51,7 +51,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
......
...@@ -32,7 +32,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ...@@ -32,7 +32,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RAM_SIZE=16384
......
...@@ -17,7 +17,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ...@@ -17,7 +17,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RAM_SIZE=16384
......
...@@ -14,7 +14,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ...@@ -14,7 +14,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_OF_PARTS=y CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y CONFIG_MTD_NAND_FSMC=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RAM_SIZE=16384
......
...@@ -84,7 +84,7 @@ CONFIG_MTD_CMDLINE_PARTS=y ...@@ -84,7 +84,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_ROM=y CONFIG_MTD_ROM=y
CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SHARPSL=y CONFIG_MTD_NAND_SHARPSL=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SD=y
......
...@@ -39,7 +39,7 @@ CONFIG_DEVTMPFS_MOUNT=y ...@@ -39,7 +39,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_TESTS=m CONFIG_MTD_TESTS=m
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_TANGO=y CONFIG_MTD_NAND_TANGO=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=y CONFIG_SCSI=y
......
...@@ -76,7 +76,7 @@ CONFIG_MTD_DOC2001PLUS=y ...@@ -76,7 +76,7 @@ CONFIG_MTD_DOC2001PLUS=y
CONFIG_MTD_DOCPROBE_ADVANCED=y CONFIG_MTD_DOCPROBE_ADVANCED=y
CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000 CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
CONFIG_MTD_DOCPROBE_HIGH=y CONFIG_MTD_DOCPROBE_HIGH=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DISKONCHIP=y CONFIG_MTD_NAND_DISKONCHIP=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000 CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
......
...@@ -27,7 +27,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ...@@ -27,7 +27,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSMC=y CONFIG_MTD_NAND_FSMC=y
# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVDEV=y
......
...@@ -206,7 +206,7 @@ CONFIG_SIMPLE_PM_BUS=y ...@@ -206,7 +206,7 @@ CONFIG_SIMPLE_PM_BUS=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_DENALI_DT=y
CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_NAND_QCOM=y
......
...@@ -41,7 +41,7 @@ CONFIG_MTD_CFI_AMDSTD=y ...@@ -41,7 +41,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_BCM47XXSFLASH=y CONFIG_MTD_BCM47XXSFLASH=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_BCM47XXNFLASH=y CONFIG_MTD_NAND_BCM47XXNFLASH=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_B44=y CONFIG_B44=y
......
...@@ -51,7 +51,7 @@ CONFIG_DEVTMPFS=y ...@@ -51,7 +51,7 @@ CONFIG_DEVTMPFS=y
CONFIG_DMA_CMA=y CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=32 CONFIG_CMA_SIZE_MBYTES=32
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_JZ4780=y CONFIG_MTD_NAND_JZ4780=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_FASTMAP=y
......
...@@ -95,8 +95,8 @@ CONFIG_MTD_CFI_AMDSTD=y ...@@ -95,8 +95,8 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y CONFIG_MTD_SST25L=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_ECC_BCH=y CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_AU1550=y CONFIG_MTD_NAND_AU1550=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
......
...@@ -15,9 +15,9 @@ CONFIG_MTD=y ...@@ -15,9 +15,9 @@ CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_ECC_BCH=y CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_GPIO=y CONFIG_MTD_NAND_GPIO=y
CONFIG_MTD_NAND_IDS=y CONFIG_MTD_NAND_IDS=y
......
...@@ -10,7 +10,7 @@ CONFIG_MTD=y ...@@ -10,7 +10,7 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
......
...@@ -42,7 +42,7 @@ CONFIG_DEVTMPFS_MOUNT=y ...@@ -42,7 +42,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=m CONFIG_SCSI=m
......
...@@ -43,7 +43,7 @@ CONFIG_DEVTMPFS_MOUNT=y ...@@ -43,7 +43,7 @@ CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=m CONFIG_SCSI=m
......
...@@ -44,7 +44,7 @@ CONFIG_TCP_CONG_WESTWOOD=y ...@@ -44,7 +44,7 @@ CONFIG_TCP_CONG_WESTWOOD=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_JZ4740=y CONFIG_MTD_NAND_JZ4740=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
......
...@@ -110,7 +110,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ...@@ -110,7 +110,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_BLOCK2MTD=y CONFIG_MTD_BLOCK2MTD=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
CONFIG_ATA=y CONFIG_ATA=y
# CONFIG_ATA_VERBOSE_ERROR is not set # CONFIG_ATA_VERBOSE_ERROR is not set
......
...@@ -40,7 +40,7 @@ CONFIG_MTD_CFI_AMDSTD=y ...@@ -40,7 +40,7 @@ CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_RBTX4939=y CONFIG_MTD_RBTX4939=y
CONFIG_MTD_NAND=m CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_TXX9NDFMC=m CONFIG_MTD_NAND_TXX9NDFMC=m
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -81,7 +81,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y ...@@ -81,7 +81,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_LANTIQ=y CONFIG_MTD_LANTIQ=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_XWAY=y CONFIG_MTD_NAND_XWAY=y
CONFIG_EEPROM_93CX6=m CONFIG_EEPROM_93CX6=m
CONFIG_SCSI=y CONFIG_SCSI=y
......
...@@ -33,7 +33,7 @@ CONFIG_MTD_CFI=y ...@@ -33,7 +33,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000 CONFIG_BLK_DEV_RAM_SIZE=35000
......
...@@ -33,7 +33,7 @@ CONFIG_MTD_CFI=y ...@@ -33,7 +33,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000 CONFIG_BLK_DEV_RAM_SIZE=35000
......
...@@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y ...@@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000 CONFIG_BLK_DEV_RAM_SIZE=35000
......
...@@ -33,7 +33,7 @@ CONFIG_MTD_BLOCK=y ...@@ -33,7 +33,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000 CONFIG_BLK_DEV_RAM_SIZE=35000
......
...@@ -33,7 +33,7 @@ CONFIG_MTD_JEDECPROBE=y ...@@ -33,7 +33,7 @@ CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y CONFIG_MTD_NAND_NDFC=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000 CONFIG_BLK_DEV_RAM_SIZE=35000
......
...@@ -34,7 +34,7 @@ CONFIG_MTD_BLOCK=y ...@@ -34,7 +34,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_NDFC=y CONFIG_MTD_NAND_NDFC=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -31,7 +31,7 @@ CONFIG_MTD_BLOCK=y ...@@ -31,7 +31,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -31,7 +31,7 @@ CONFIG_MTD_BLOCK=y ...@@ -31,7 +31,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_BLK_DEV_RAM_SIZE=32768
......
...@@ -71,7 +71,7 @@ CONFIG_MTD_CMDLINE_PARTS=y ...@@ -71,7 +71,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_M25P80=y CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PLATRAM=y CONFIG_MTD_PLATRAM=y
......
...@@ -73,7 +73,7 @@ CONFIG_MTD_JEDECPROBE=y ...@@ -73,7 +73,7 @@ CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m
......
...@@ -31,7 +31,7 @@ CONFIG_MTD_CFI=y ...@@ -31,7 +31,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SOCRATES=y CONFIG_MTD_NAND_SOCRATES=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -35,8 +35,8 @@ CONFIG_MTD=y ...@@ -35,8 +35,8 @@ CONFIG_MTD=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND_ECC_SMC=y CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_UPM=y CONFIG_MTD_NAND_FSL_UPM=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -65,7 +65,7 @@ CONFIG_MTD_CFI_INTELEXT=y ...@@ -65,7 +65,7 @@ CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_UPM=y CONFIG_MTD_NAND_FSL_UPM=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
......
...@@ -47,7 +47,7 @@ CONFIG_MTD_CFI=y ...@@ -47,7 +47,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_NET_TULIP=y CONFIG_NET_TULIP=y
......
...@@ -46,7 +46,7 @@ CONFIG_MTD_CFI=y ...@@ -46,7 +46,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ROM=y CONFIG_MTD_ROM=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_MPC5121_NFC=y CONFIG_MTD_NAND_MPC5121_NFC=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -46,7 +46,7 @@ CONFIG_MTD_BLOCK=y ...@@ -46,7 +46,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -51,7 +51,7 @@ CONFIG_MTD=y ...@@ -51,7 +51,7 @@ CONFIG_MTD=y
CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=y CONFIG_MTD_SLRAM=y
CONFIG_MTD_PHRAM=y CONFIG_MTD_PHRAM=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PASEMI=y CONFIG_MTD_NAND_PASEMI=y
CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -44,7 +44,7 @@ CONFIG_MTD_CFI=y ...@@ -44,7 +44,7 @@ CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_NAND=m CONFIG_MTD_RAW_NAND=m
CONFIG_MTD_NAND_NDFC=m CONFIG_MTD_NAND_NDFC=m
CONFIG_MTD_UBI=m CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m CONFIG_MTD_UBI_GLUEBI=m
......
...@@ -35,7 +35,7 @@ CONFIG_MTD_BLOCK=y ...@@ -35,7 +35,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_SH_FLCTL=y CONFIG_MTD_NAND_SH_FLCTL=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y ...@@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4 CONFIG_BLK_DEV_RAM_COUNT=4
......
...@@ -34,7 +34,7 @@ CONFIG_MTD_BLOCK=y ...@@ -34,7 +34,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y CONFIG_SCSI=y
......
...@@ -108,7 +108,7 @@ CONFIG_MTD_ROM=m ...@@ -108,7 +108,7 @@ CONFIG_MTD_ROM=m
CONFIG_MTD_ABSENT=m CONFIG_MTD_ABSENT=m
CONFIG_MTD_PLATRAM=y CONFIG_MTD_PLATRAM=y
CONFIG_MTD_PHRAM=y CONFIG_MTD_PHRAM=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_PLATFORM=y CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_NAND_SH_FLCTL=m CONFIG_MTD_NAND_SH_FLCTL=m
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
......
...@@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y ...@@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_UBI=y CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4 CONFIG_BLK_DEV_RAM_COUNT=4
......
...@@ -155,7 +155,7 @@ CONFIG_INFTL=m ...@@ -155,7 +155,7 @@ CONFIG_INFTL=m
CONFIG_RFD_FTL=m CONFIG_RFD_FTL=m
CONFIG_MTD_CFI=m CONFIG_MTD_CFI=m
CONFIG_MTD_JEDECPROBE=m CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_NAND=m CONFIG_MTD_RAW_NAND=m
CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
......
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <soc/at91/atmel-sfr.h>
struct atmel_ebi_dev_config { struct atmel_ebi_dev_config {
int cs; int cs;
...@@ -36,6 +37,7 @@ struct atmel_ebi_dev { ...@@ -36,6 +37,7 @@ struct atmel_ebi_dev {
struct atmel_ebi_caps { struct atmel_ebi_caps {
unsigned int available_cs; unsigned int available_cs;
unsigned int ebi_csa_offs; unsigned int ebi_csa_offs;
const char *regmap_name;
void (*get_config)(struct atmel_ebi_dev *ebid, void (*get_config)(struct atmel_ebi_dev *ebid,
struct atmel_ebi_dev_config *conf); struct atmel_ebi_dev_config *conf);
int (*xlate_config)(struct atmel_ebi_dev *ebid, int (*xlate_config)(struct atmel_ebi_dev *ebid,
...@@ -47,7 +49,7 @@ struct atmel_ebi_caps { ...@@ -47,7 +49,7 @@ struct atmel_ebi_caps {
struct atmel_ebi { struct atmel_ebi {
struct clk *clk; struct clk *clk;
struct regmap *matrix; struct regmap *regmap;
struct { struct {
struct regmap *regmap; struct regmap *regmap;
struct clk *clk; struct clk *clk;
...@@ -357,7 +359,7 @@ static int atmel_ebi_dev_setup(struct atmel_ebi *ebi, struct device_node *np, ...@@ -357,7 +359,7 @@ static int atmel_ebi_dev_setup(struct atmel_ebi *ebi, struct device_node *np,
* one "atmel,smc-" property is present. * one "atmel,smc-" property is present.
*/ */
if (ebi->caps->ebi_csa_offs && apply) if (ebi->caps->ebi_csa_offs && apply)
regmap_update_bits(ebi->matrix, regmap_update_bits(ebi->regmap,
ebi->caps->ebi_csa_offs, ebi->caps->ebi_csa_offs,
BIT(cs), 0); BIT(cs), 0);
...@@ -372,6 +374,7 @@ static int atmel_ebi_dev_setup(struct atmel_ebi *ebi, struct device_node *np, ...@@ -372,6 +374,7 @@ static int atmel_ebi_dev_setup(struct atmel_ebi *ebi, struct device_node *np,
static const struct atmel_ebi_caps at91sam9260_ebi_caps = { static const struct atmel_ebi_caps at91sam9260_ebi_caps = {
.available_cs = 0xff, .available_cs = 0xff,
.ebi_csa_offs = AT91SAM9260_MATRIX_EBICSA, .ebi_csa_offs = AT91SAM9260_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config, .get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config, .xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config, .apply_config = at91sam9_ebi_apply_config,
...@@ -380,6 +383,7 @@ static const struct atmel_ebi_caps at91sam9260_ebi_caps = { ...@@ -380,6 +383,7 @@ static const struct atmel_ebi_caps at91sam9260_ebi_caps = {
static const struct atmel_ebi_caps at91sam9261_ebi_caps = { static const struct atmel_ebi_caps at91sam9261_ebi_caps = {
.available_cs = 0xff, .available_cs = 0xff,
.ebi_csa_offs = AT91SAM9261_MATRIX_EBICSA, .ebi_csa_offs = AT91SAM9261_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config, .get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config, .xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config, .apply_config = at91sam9_ebi_apply_config,
...@@ -388,6 +392,7 @@ static const struct atmel_ebi_caps at91sam9261_ebi_caps = { ...@@ -388,6 +392,7 @@ static const struct atmel_ebi_caps at91sam9261_ebi_caps = {
static const struct atmel_ebi_caps at91sam9263_ebi0_caps = { static const struct atmel_ebi_caps at91sam9263_ebi0_caps = {
.available_cs = 0x3f, .available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9263_MATRIX_EBI0CSA, .ebi_csa_offs = AT91SAM9263_MATRIX_EBI0CSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config, .get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config, .xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config, .apply_config = at91sam9_ebi_apply_config,
...@@ -396,6 +401,7 @@ static const struct atmel_ebi_caps at91sam9263_ebi0_caps = { ...@@ -396,6 +401,7 @@ static const struct atmel_ebi_caps at91sam9263_ebi0_caps = {
static const struct atmel_ebi_caps at91sam9263_ebi1_caps = { static const struct atmel_ebi_caps at91sam9263_ebi1_caps = {
.available_cs = 0x7, .available_cs = 0x7,
.ebi_csa_offs = AT91SAM9263_MATRIX_EBI1CSA, .ebi_csa_offs = AT91SAM9263_MATRIX_EBI1CSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config, .get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config, .xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config, .apply_config = at91sam9_ebi_apply_config,
...@@ -404,6 +410,7 @@ static const struct atmel_ebi_caps at91sam9263_ebi1_caps = { ...@@ -404,6 +410,7 @@ static const struct atmel_ebi_caps at91sam9263_ebi1_caps = {
static const struct atmel_ebi_caps at91sam9rl_ebi_caps = { static const struct atmel_ebi_caps at91sam9rl_ebi_caps = {
.available_cs = 0x3f, .available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9RL_MATRIX_EBICSA, .ebi_csa_offs = AT91SAM9RL_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config, .get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config, .xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config, .apply_config = at91sam9_ebi_apply_config,
...@@ -412,6 +419,7 @@ static const struct atmel_ebi_caps at91sam9rl_ebi_caps = { ...@@ -412,6 +419,7 @@ static const struct atmel_ebi_caps at91sam9rl_ebi_caps = {
static const struct atmel_ebi_caps at91sam9g45_ebi_caps = { static const struct atmel_ebi_caps at91sam9g45_ebi_caps = {
.available_cs = 0x3f, .available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9G45_MATRIX_EBICSA, .ebi_csa_offs = AT91SAM9G45_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config, .get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config, .xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config, .apply_config = at91sam9_ebi_apply_config,
...@@ -420,6 +428,7 @@ static const struct atmel_ebi_caps at91sam9g45_ebi_caps = { ...@@ -420,6 +428,7 @@ static const struct atmel_ebi_caps at91sam9g45_ebi_caps = {
static const struct atmel_ebi_caps at91sam9x5_ebi_caps = { static const struct atmel_ebi_caps at91sam9x5_ebi_caps = {
.available_cs = 0x3f, .available_cs = 0x3f,
.ebi_csa_offs = AT91SAM9X5_MATRIX_EBICSA, .ebi_csa_offs = AT91SAM9X5_MATRIX_EBICSA,
.regmap_name = "atmel,matrix",
.get_config = at91sam9_ebi_get_config, .get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config, .xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config, .apply_config = at91sam9_ebi_apply_config,
...@@ -432,6 +441,15 @@ static const struct atmel_ebi_caps sama5d3_ebi_caps = { ...@@ -432,6 +441,15 @@ static const struct atmel_ebi_caps sama5d3_ebi_caps = {
.apply_config = sama5_ebi_apply_config, .apply_config = sama5_ebi_apply_config,
}; };
static const struct atmel_ebi_caps sam9x60_ebi_caps = {
.available_cs = 0x3f,
.ebi_csa_offs = AT91_SFR_CCFG_EBICSA,
.regmap_name = "microchip,sfr",
.get_config = at91sam9_ebi_get_config,
.xlate_config = atmel_ebi_xslate_smc_config,
.apply_config = at91sam9_ebi_apply_config,
};
static const struct of_device_id atmel_ebi_id_table[] = { static const struct of_device_id atmel_ebi_id_table[] = {
{ {
.compatible = "atmel,at91sam9260-ebi", .compatible = "atmel,at91sam9260-ebi",
...@@ -465,6 +483,10 @@ static const struct of_device_id atmel_ebi_id_table[] = { ...@@ -465,6 +483,10 @@ static const struct of_device_id atmel_ebi_id_table[] = {
.compatible = "atmel,sama5d3-ebi", .compatible = "atmel,sama5d3-ebi",
.data = &sama5d3_ebi_caps, .data = &sama5d3_ebi_caps,
}, },
{
.compatible = "microchip,sam9x60-ebi",
.data = &sam9x60_ebi_caps,
},
{ /* sentinel */ } { /* sentinel */ }
}; };
...@@ -543,13 +565,14 @@ static int atmel_ebi_probe(struct platform_device *pdev) ...@@ -543,13 +565,14 @@ static int atmel_ebi_probe(struct platform_device *pdev)
/* /*
* The sama5d3 does not provide an EBICSA register and thus does need * The sama5d3 does not provide an EBICSA register and thus does need
* to access the matrix registers. * to access it.
*/ */
if (ebi->caps->ebi_csa_offs) { if (ebi->caps->ebi_csa_offs) {
ebi->matrix = ebi->regmap =
syscon_regmap_lookup_by_phandle(np, "atmel,matrix"); syscon_regmap_lookup_by_phandle(np,
if (IS_ERR(ebi->matrix)) ebi->caps->regmap_name);
return PTR_ERR(ebi->matrix); if (IS_ERR(ebi->regmap))
return PTR_ERR(ebi->regmap);
} }
ret = of_property_read_u32(np, "#address-cells", &val); ret = of_property_read_u32(np, "#address-cells", &val);
......
...@@ -230,12 +230,11 @@ config SSFDC ...@@ -230,12 +230,11 @@ config SSFDC
This enables read only access to SmartMedia formatted NAND This enables read only access to SmartMedia formatted NAND
flash. You can mount it with FAT file system. flash. You can mount it with FAT file system.
config SM_FTL config SM_FTL
tristate "SmartMedia/xD new translation layer" tristate "SmartMedia/xD new translation layer"
depends on BLOCK depends on BLOCK
select MTD_BLKDEVS select MTD_BLKDEVS
select MTD_NAND_ECC select MTD_NAND_ECC_SW_HAMMING
help help
This enables EXPERIMENTAL R/W support for SmartMedia/xD This enables EXPERIMENTAL R/W support for SmartMedia/xD
FTL (Flash translation layer). FTL (Flash translation layer).
......
...@@ -207,7 +207,7 @@ comment "Disk-On-Chip Device Drivers" ...@@ -207,7 +207,7 @@ comment "Disk-On-Chip Device Drivers"
config MTD_DOCG3 config MTD_DOCG3
tristate "M-Systems Disk-On-Chip G3" tristate "M-Systems Disk-On-Chip G3"
select BCH select BCH
select BCH_CONST_PARAMS if !MTD_NAND_BCH select BCH_CONST_PARAMS if !MTD_NAND_ECC_SW_BCH
select BITREVERSE select BITREVERSE
help help
This provides an MTD device driver for the M-Systems DiskOnChip This provides an MTD device driver for the M-Systems DiskOnChip
......
...@@ -2,6 +2,5 @@ config MTD_NAND_CORE ...@@ -2,6 +2,5 @@ config MTD_NAND_CORE
tristate tristate
source "drivers/mtd/nand/onenand/Kconfig" source "drivers/mtd/nand/onenand/Kconfig"
source "drivers/mtd/nand/raw/Kconfig" source "drivers/mtd/nand/raw/Kconfig"
source "drivers/mtd/nand/spi/Kconfig" source "drivers/mtd/nand/spi/Kconfig"
...@@ -173,6 +173,40 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo) ...@@ -173,6 +173,40 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo)
} }
EXPORT_SYMBOL_GPL(nanddev_mtd_erase); EXPORT_SYMBOL_GPL(nanddev_mtd_erase);
/**
* nanddev_mtd_max_bad_blocks() - Get the maximum number of bad eraseblock on
* a specific region of the NAND device
* @mtd: MTD device
* @offs: offset of the NAND region
* @len: length of the NAND region
*
* Default implementation for mtd->_max_bad_blocks(). Only works if
* nand->memorg.max_bad_eraseblocks_per_lun is > 0.
*
* Return: a positive number encoding the maximum number of eraseblocks on a
* portion of memory, a negative error code otherwise.
*/
int nanddev_mtd_max_bad_blocks(struct mtd_info *mtd, loff_t offs, size_t len)
{
struct nand_device *nand = mtd_to_nanddev(mtd);
struct nand_pos pos, end;
unsigned int max_bb = 0;
if (!nand->memorg.max_bad_eraseblocks_per_lun)
return -ENOTSUPP;
nanddev_offs_to_pos(nand, offs, &pos);
nanddev_offs_to_pos(nand, offs + len, &end);
for (nanddev_offs_to_pos(nand, offs, &pos);
nanddev_pos_cmp(&pos, &end) < 0;
nanddev_pos_next_lun(nand, &pos))
max_bb += nand->memorg.max_bad_eraseblocks_per_lun;
return max_bb;
}
EXPORT_SYMBOL_GPL(nanddev_mtd_max_bad_blocks);
/** /**
* nanddev_init() - Initialize a NAND device * nanddev_init() - Initialize a NAND device
* @nand: NAND device * @nand: NAND device
......
...@@ -2458,7 +2458,7 @@ static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) ...@@ -2458,7 +2458,7 @@ static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
/* We write two bytes, so we don't have to mess with 16-bit access */ /* We write two bytes, so we don't have to mess with 16-bit access */
ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); ofs += mtd->oobsize + (this->badblockpos & ~0x01);
/* FIXME : What to do when marking SLC block in partition /* FIXME : What to do when marking SLC block in partition
* with MLC erasesize? For now, it is not advisable to * with MLC erasesize? For now, it is not advisable to
* create partitions containing both SLC and MLC regions. * create partitions containing both SLC and MLC regions.
...@@ -3967,6 +3967,9 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) ...@@ -3967,6 +3967,9 @@ int onenand_scan(struct mtd_info *mtd, int maxchips)
if (!(this->options & ONENAND_SKIP_INITIAL_UNLOCKING)) if (!(this->options & ONENAND_SKIP_INITIAL_UNLOCKING))
this->unlock_all(mtd); this->unlock_all(mtd);
/* Set the bad block marker position */
this->badblockpos = ONENAND_BADBLOCK_POS;
ret = this->scan_bbt(mtd); ret = this->scan_bbt(mtd);
if ((!FLEXONENAND(this)) || ret) if ((!FLEXONENAND(this)) || ret)
return ret; return ret;
......
...@@ -190,9 +190,6 @@ static int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) ...@@ -190,9 +190,6 @@ static int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
if (!bbm->bbt) if (!bbm->bbt)
return -ENOMEM; return -ENOMEM;
/* Set the bad block position */
bbm->badblockpos = ONENAND_BADBLOCK_POS;
/* Set erase shift */ /* Set erase shift */
bbm->bbt_erase_shift = this->erase_shift; bbm->bbt_erase_shift = this->erase_shift;
......
This diff is collapsed.
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_MTD_NAND) += nand.o obj-$(CONFIG_MTD_RAW_NAND) += nand.o
obj-$(CONFIG_MTD_NAND_ECC) += nand_ecc.o obj-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += nand_ecc.o
obj-$(CONFIG_MTD_NAND_BCH) += nand_bch.o nand-$(CONFIG_MTD_NAND_ECC_SW_BCH) += nand_bch.o
obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o
obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o
...@@ -45,8 +45,7 @@ obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o ...@@ -45,8 +45,7 @@ obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o
obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o obj-y += ingenic/
obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o
obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
......
// SPDX-License-Identifier: GPL-2.0
/* /*
* Copyright 2017 ATMEL * Copyright 2017 ATMEL
* Copyright 2017 Free Electrons * Copyright 2017 Free Electrons
...@@ -29,10 +30,6 @@ ...@@ -29,10 +30,6 @@
* Add Nand Flash Controller support for SAMA5 SoC * Add Nand Flash Controller support for SAMA5 SoC
* Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
* *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* A few words about the naming convention in this file. This convention * A few words about the naming convention in this file. This convention
* applies to structure and function names. * applies to structure and function names.
* *
...@@ -65,6 +62,7 @@ ...@@ -65,6 +62,7 @@
#include <linux/iopoll.h> #include <linux/iopoll.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/regmap.h> #include <linux/regmap.h>
#include <soc/at91/atmel-sfr.h>
#include "pmecc.h" #include "pmecc.h"
...@@ -211,6 +209,7 @@ struct atmel_nand_controller_caps { ...@@ -211,6 +209,7 @@ struct atmel_nand_controller_caps {
bool legacy_of_bindings; bool legacy_of_bindings;
u32 ale_offs; u32 ale_offs;
u32 cle_offs; u32 cle_offs;
const char *ebi_csa_regmap_name;
const struct atmel_nand_controller_ops *ops; const struct atmel_nand_controller_ops *ops;
}; };
...@@ -231,10 +230,15 @@ to_nand_controller(struct nand_controller *ctl) ...@@ -231,10 +230,15 @@ to_nand_controller(struct nand_controller *ctl)
return container_of(ctl, struct atmel_nand_controller, base); return container_of(ctl, struct atmel_nand_controller, base);
} }
struct atmel_smc_nand_ebi_csa_cfg {
u32 offs;
u32 nfd0_on_d16;
};
struct atmel_smc_nand_controller { struct atmel_smc_nand_controller {
struct atmel_nand_controller base; struct atmel_nand_controller base;
struct regmap *matrix; struct regmap *ebi_csa_regmap;
unsigned int ebi_csa_offs; struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
}; };
static inline struct atmel_smc_nand_controller * static inline struct atmel_smc_nand_controller *
...@@ -1068,15 +1072,15 @@ static int atmel_nand_pmecc_init(struct nand_chip *chip) ...@@ -1068,15 +1072,15 @@ static int atmel_nand_pmecc_init(struct nand_chip *chip)
req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
else if (chip->ecc.strength) else if (chip->ecc.strength)
req.ecc.strength = chip->ecc.strength; req.ecc.strength = chip->ecc.strength;
else if (chip->ecc_strength_ds) else if (chip->base.eccreq.strength)
req.ecc.strength = chip->ecc_strength_ds; req.ecc.strength = chip->base.eccreq.strength;
else else
req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
if (chip->ecc.size) if (chip->ecc.size)
req.ecc.sectorsize = chip->ecc.size; req.ecc.sectorsize = chip->ecc.size;
else if (chip->ecc_step_ds) else if (chip->base.eccreq.step_size)
req.ecc.sectorsize = chip->ecc_step_ds; req.ecc.sectorsize = chip->base.eccreq.step_size;
else else
req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO; req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
...@@ -1507,13 +1511,20 @@ static void atmel_smc_nand_init(struct atmel_nand_controller *nc, ...@@ -1507,13 +1511,20 @@ static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
atmel_nand_init(nc, nand); atmel_nand_init(nc, nand);
smc_nc = to_smc_nand_controller(chip->controller); smc_nc = to_smc_nand_controller(chip->controller);
if (!smc_nc->matrix) if (!smc_nc->ebi_csa_regmap)
return; return;
/* Attach the CS to the NAND Flash logic. */ /* Attach the CS to the NAND Flash logic. */
for (i = 0; i < nand->numcs; i++) for (i = 0; i < nand->numcs; i++)
regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs, regmap_update_bits(smc_nc->ebi_csa_regmap,
smc_nc->ebi_csa->offs,
BIT(nand->cs[i].id), BIT(nand->cs[i].id)); BIT(nand->cs[i].id), BIT(nand->cs[i].id));
if (smc_nc->ebi_csa->nfd0_on_d16)
regmap_update_bits(smc_nc->ebi_csa_regmap,
smc_nc->ebi_csa->offs,
smc_nc->ebi_csa->nfd0_on_d16,
smc_nc->ebi_csa->nfd0_on_d16);
} }
static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc, static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
...@@ -1797,7 +1808,7 @@ static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc) ...@@ -1797,7 +1808,7 @@ static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
ret = of_property_read_u32(np, "#size-cells", &val); ret = of_property_read_u32(np, "#size-cells", &val);
if (ret) { if (ret) {
dev_err(dev, "missing #address-cells property\n"); dev_err(dev, "missing #size-cells property\n");
return ret; return ret;
} }
...@@ -1833,34 +1844,71 @@ static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc) ...@@ -1833,34 +1844,71 @@ static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
clk_put(nc->mck); clk_put(nc->mck);
} }
static const struct of_device_id atmel_matrix_of_ids[] = { static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
.offs = AT91SAM9260_MATRIX_EBICSA,
};
static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
.offs = AT91SAM9261_MATRIX_EBICSA,
};
static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
.offs = AT91SAM9263_MATRIX_EBI0CSA,
};
static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
.offs = AT91SAM9RL_MATRIX_EBICSA,
};
static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
.offs = AT91SAM9G45_MATRIX_EBICSA,
};
static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
.offs = AT91SAM9N12_MATRIX_EBICSA,
};
static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
.offs = AT91SAM9X5_MATRIX_EBICSA,
};
static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
.offs = AT91_SFR_CCFG_EBICSA,
.nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
};
static const struct of_device_id atmel_ebi_csa_regmap_of_ids[] = {
{ {
.compatible = "atmel,at91sam9260-matrix", .compatible = "atmel,at91sam9260-matrix",
.data = (void *)AT91SAM9260_MATRIX_EBICSA, .data = &at91sam9260_ebi_csa,
}, },
{ {
.compatible = "atmel,at91sam9261-matrix", .compatible = "atmel,at91sam9261-matrix",
.data = (void *)AT91SAM9261_MATRIX_EBICSA, .data = &at91sam9261_ebi_csa,
}, },
{ {
.compatible = "atmel,at91sam9263-matrix", .compatible = "atmel,at91sam9263-matrix",
.data = (void *)AT91SAM9263_MATRIX_EBI0CSA, .data = &at91sam9263_ebi_csa,
}, },
{ {
.compatible = "atmel,at91sam9rl-matrix", .compatible = "atmel,at91sam9rl-matrix",
.data = (void *)AT91SAM9RL_MATRIX_EBICSA, .data = &at91sam9rl_ebi_csa,
}, },
{ {
.compatible = "atmel,at91sam9g45-matrix", .compatible = "atmel,at91sam9g45-matrix",
.data = (void *)AT91SAM9G45_MATRIX_EBICSA, .data = &at91sam9g45_ebi_csa,
}, },
{ {
.compatible = "atmel,at91sam9n12-matrix", .compatible = "atmel,at91sam9n12-matrix",
.data = (void *)AT91SAM9N12_MATRIX_EBICSA, .data = &at91sam9n12_ebi_csa,
}, },
{ {
.compatible = "atmel,at91sam9x5-matrix", .compatible = "atmel,at91sam9x5-matrix",
.data = (void *)AT91SAM9X5_MATRIX_EBICSA, .data = &at91sam9x5_ebi_csa,
},
{
.compatible = "microchip,sam9x60-sfr",
.data = &sam9x60_ebi_csa,
}, },
{ /* sentinel */ }, { /* sentinel */ },
}; };
...@@ -1982,37 +2030,38 @@ atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc) ...@@ -1982,37 +2030,38 @@ atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
struct device_node *np; struct device_node *np;
int ret; int ret;
/* We do not retrieve the matrix syscon when parsing old DTs. */ /* We do not retrieve the EBICSA regmap when parsing old DTs. */
if (nc->base.caps->legacy_of_bindings) if (nc->base.caps->legacy_of_bindings)
return 0; return 0;
np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0); np = of_parse_phandle(dev->parent->of_node,
nc->base.caps->ebi_csa_regmap_name, 0);
if (!np) if (!np)
return 0; return 0;
match = of_match_node(atmel_matrix_of_ids, np); match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);
if (!match) { if (!match) {
of_node_put(np); of_node_put(np);
return 0; return 0;
} }
nc->matrix = syscon_node_to_regmap(np); nc->ebi_csa_regmap = syscon_node_to_regmap(np);
of_node_put(np); of_node_put(np);
if (IS_ERR(nc->matrix)) { if (IS_ERR(nc->ebi_csa_regmap)) {
ret = PTR_ERR(nc->matrix); ret = PTR_ERR(nc->ebi_csa_regmap);
dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret); dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
return ret; return ret;
} }
nc->ebi_csa_offs = (uintptr_t)match->data; nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
/* /*
* The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
* add 4 to ->ebi_csa_offs. * add 4 to ->ebi_csa->offs.
*/ */
if (of_device_is_compatible(dev->parent->of_node, if (of_device_is_compatible(dev->parent->of_node,
"atmel,at91sam9263-ebi1")) "atmel,at91sam9263-ebi1"))
nc->ebi_csa_offs += 4; nc->ebi_csa->offs += 4;
return 0; return 0;
} }
...@@ -2341,6 +2390,7 @@ static const struct atmel_nand_controller_ops at91rm9200_nc_ops = { ...@@ -2341,6 +2390,7 @@ static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = { static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
.ale_offs = BIT(21), .ale_offs = BIT(21),
.cle_offs = BIT(22), .cle_offs = BIT(22),
.ebi_csa_regmap_name = "atmel,matrix",
.ops = &at91rm9200_nc_ops, .ops = &at91rm9200_nc_ops,
}; };
...@@ -2355,12 +2405,14 @@ static const struct atmel_nand_controller_ops atmel_smc_nc_ops = { ...@@ -2355,12 +2405,14 @@ static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = { static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
.ale_offs = BIT(21), .ale_offs = BIT(21),
.cle_offs = BIT(22), .cle_offs = BIT(22),
.ebi_csa_regmap_name = "atmel,matrix",
.ops = &atmel_smc_nc_ops, .ops = &atmel_smc_nc_ops,
}; };
static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = { static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
.ale_offs = BIT(22), .ale_offs = BIT(22),
.cle_offs = BIT(21), .cle_offs = BIT(21),
.ebi_csa_regmap_name = "atmel,matrix",
.ops = &atmel_smc_nc_ops, .ops = &atmel_smc_nc_ops,
}; };
...@@ -2368,6 +2420,15 @@ static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = { ...@@ -2368,6 +2420,15 @@ static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
.has_dma = true, .has_dma = true,
.ale_offs = BIT(21), .ale_offs = BIT(21),
.cle_offs = BIT(22), .cle_offs = BIT(22),
.ebi_csa_regmap_name = "atmel,matrix",
.ops = &atmel_smc_nc_ops,
};
static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
.has_dma = true,
.ale_offs = BIT(21),
.cle_offs = BIT(22),
.ebi_csa_regmap_name = "microchip,sfr",
.ops = &atmel_smc_nc_ops, .ops = &atmel_smc_nc_ops,
}; };
...@@ -2415,6 +2476,10 @@ static const struct of_device_id atmel_nand_controller_of_ids[] = { ...@@ -2415,6 +2476,10 @@ static const struct of_device_id atmel_nand_controller_of_ids[] = {
.compatible = "atmel,sama5d3-nand-controller", .compatible = "atmel,sama5d3-nand-controller",
.data = &atmel_sama5_nc_caps, .data = &atmel_sama5_nc_caps,
}, },
{
.compatible = "microchip,sam9x60-nand-controller",
.data = &microchip_sam9x60_nc_caps,
},
/* Support for old/deprecated bindings: */ /* Support for old/deprecated bindings: */
{ {
.compatible = "atmel,at91rm9200-nand", .compatible = "atmel,at91rm9200-nand",
......
// SPDX-License-Identifier: GPL-2.0
/* /*
* Copyright 2017 ATMEL * Copyright 2017 ATMEL
* Copyright 2017 Free Electrons * Copyright 2017 Free Electrons
...@@ -28,10 +29,6 @@ ...@@ -28,10 +29,6 @@
* Add Nand Flash Controller support for SAMA5 SoC * Add Nand Flash Controller support for SAMA5 SoC
* Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
* *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* The PMECC is an hardware assisted BCH engine, which means part of the * The PMECC is an hardware assisted BCH engine, which means part of the
* ECC algorithm is left to the software. The hardware/software repartition * ECC algorithm is left to the software. The hardware/software repartition
* is explained in the "PMECC Controller Functional Description" chapter in * is explained in the "PMECC Controller Functional Description" chapter in
......
/* SPDX-License-Identifier: GPL-2.0 */
/* /*
* © Copyright 2016 ATMEL * © Copyright 2016 ATMEL
* © Copyright 2016 Free Electrons * © Copyright 2016 Free Electrons
...@@ -28,11 +29,6 @@ ...@@ -28,11 +29,6 @@
* *
* Add Nand Flash Controller support for SAMA5 SoC * Add Nand Flash Controller support for SAMA5 SoC
* © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/ */
#ifndef ATMEL_PMECC_H #ifndef ATMEL_PMECC_H
......
...@@ -428,7 +428,7 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) ...@@ -428,7 +428,7 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
} }
/* Configure FLASH */ /* Configure FLASH */
chipsize = b47n->nand_chip.chipsize >> 20; chipsize = nanddev_target_size(&b47n->nand_chip.base) >> 20;
tbits = ffs(chipsize); /* find first bit set */ tbits = ffs(chipsize); /* find first bit set */
if (!tbits || tbits != fls(chipsize)) { if (!tbits || tbits != fls(chipsize)) {
pr_err("Invalid flash size: 0x%lX\n", chipsize); pr_err("Invalid flash size: 0x%lX\n", chipsize);
......
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