Commit 1db92e54 authored by Michael Turquette's avatar Michael Turquette Committed by Stephen Boyd

Merge branch 'v4.3-topic/clk-samsung' of...

Merge branch 'v4.3-topic/clk-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-next
parents afe76c8f 7c9422ef
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <dt-bindings/clock/exynos3250.h> #include <dt-bindings/clock/exynos3250.h>
#include "clk.h" #include "clk.h"
#include "clk-cpu.h"
#include "clk-pll.h" #include "clk-pll.h"
#define SRC_LEFTBUS 0x4200 #define SRC_LEFTBUS 0x4200
...@@ -317,8 +318,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = { ...@@ -317,8 +318,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p, MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
SRC_CPU, 24, 1), SRC_CPU, 24, 1),
MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1), MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1), MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1,
MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
CLK_SET_RATE_PARENT, 0),
}; };
static struct samsung_div_clock div_clks[] __initdata = { static struct samsung_div_clock div_clks[] __initdata = {
...@@ -770,6 +773,26 @@ static struct samsung_cmu_info cmu_info __initdata = { ...@@ -770,6 +773,26 @@ static struct samsung_cmu_info cmu_info __initdata = {
.nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs), .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs),
}; };
#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \
(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
((corem) << 4))
#define E3250_CPU_DIV1(hpm, copy) \
(((hpm) << 4) | ((copy) << 0))
static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
{ 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), },
{ 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), },
{ 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), },
{ 0 },
};
static void __init exynos3250_cmu_init(struct device_node *np) static void __init exynos3250_cmu_init(struct device_node *np)
{ {
struct samsung_clk_provider *ctx; struct samsung_clk_provider *ctx;
...@@ -778,6 +801,11 @@ static void __init exynos3250_cmu_init(struct device_node *np) ...@@ -778,6 +801,11 @@ static void __init exynos3250_cmu_init(struct device_node *np)
if (!ctx) if (!ctx)
return; return;
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_core_p[0], mout_core_p[1], 0x14200,
e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
CLK_CPU_HAS_DIV1);
exynos3_core_down_clock(ctx->reg_base); exynos3_core_down_clock(ctx->reg_base);
} }
CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
......
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <linux/syscore_ops.h> #include <linux/syscore_ops.h>
#include "clk.h" #include "clk.h"
#include "clk-cpu.h"
#define APLL_LOCK 0x0 #define APLL_LOCK 0x0
#define APLL_CON0 0x100 #define APLL_CON0 0x100
...@@ -746,6 +747,32 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { ...@@ -746,6 +747,32 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
VPLL_LOCK, VPLL_CON0, NULL), VPLL_LOCK, VPLL_CON0, NULL),
}; };
#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
#define E5250_CPU_DIV1(hpm, copy) \
(((hpm) << 4) | (copy))
static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
{ 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
{ 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
{ 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
{ 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
{ 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
{ 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
{ 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
{ 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
{ 0 },
};
static const struct of_device_id ext_clk_match[] __initconst = { static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,clock-xxti", .data = (void *)0, }, { .compatible = "samsung,clock-xxti", .data = (void *)0, },
{ }, { },
...@@ -795,6 +822,10 @@ static void __init exynos5250_clk_init(struct device_node *np) ...@@ -795,6 +822,10 @@ static void __init exynos5250_clk_init(struct device_node *np)
ARRAY_SIZE(exynos5250_div_clks)); ARRAY_SIZE(exynos5250_div_clks));
samsung_clk_register_gate(ctx, exynos5250_gate_clks, samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks)); ARRAY_SIZE(exynos5250_gate_clks));
exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
mout_cpu_p[0], mout_cpu_p[1], 0x200,
exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
CLK_CPU_HAS_DIV1);
/* /*
* Enable arm clock down (in idle) and set arm divider * Enable arm clock down (in idle) and set arm divider
......
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#define CLK_FOUT_VPLL 4 #define CLK_FOUT_VPLL 4
#define CLK_FOUT_UPLL 5 #define CLK_FOUT_UPLL 5
#define CLK_FOUT_MPLL 6 #define CLK_FOUT_MPLL 6
#define CLK_ARM_CLK 7
/* Muxes */ /* Muxes */
#define CLK_MOUT_MPLL_USER_L 16 #define CLK_MOUT_MPLL_USER_L 16
......
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#define CLK_FOUT_CPLL 6 #define CLK_FOUT_CPLL 6
#define CLK_FOUT_EPLL 7 #define CLK_FOUT_EPLL 7
#define CLK_FOUT_VPLL 8 #define CLK_FOUT_VPLL 8
#define CLK_ARM_CLK 9
/* gate for special clocks (sclk) */ /* gate for special clocks (sclk) */
#define CLK_SCLK_CAM_BAYER 128 #define CLK_SCLK_CAM_BAYER 128
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment