Commit 1e62c52d authored by Adam Thomson's avatar Adam Thomson Committed by Mark Brown

ASoC: da7213: Update PLL ranges to improve locking at frequency boundary

This update changes the dividers used for ranges of input MCLK
frequencies, to improve PLL locking for a corner case when at edge
of MCLK frequency input divider range.
Signed-off-by: default avatarAdam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7e28fd46
...@@ -1344,26 +1344,26 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, ...@@ -1344,26 +1344,26 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
/* Workout input divider based on MCLK rate */ /* Workout input divider based on MCLK rate */
if ((da7213->mclk_rate == 32768) && (source == DA7213_SYSCLK_PLL)) { if ((da7213->mclk_rate == 32768) && (source == DA7213_SYSCLK_PLL)) {
/* 32KHz PLL Mode */ /* 32KHz PLL Mode */
indiv_bits = DA7213_PLL_INDIV_10_20_MHZ; indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7213_PLL_INDIV_10_20_MHZ_VAL; indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL;
freq_ref = 3750000; freq_ref = 3750000;
pll_ctrl |= DA7213_PLL_32K_MODE; pll_ctrl |= DA7213_PLL_32K_MODE;
} else { } else {
/* 5 - 54MHz MCLK */ /* 5 - 54MHz MCLK */
if (da7213->mclk_rate < 5000000) { if (da7213->mclk_rate < 5000000) {
goto pll_err; goto pll_err;
} else if (da7213->mclk_rate <= 10000000) { } else if (da7213->mclk_rate <= 9000000) {
indiv_bits = DA7213_PLL_INDIV_5_10_MHZ; indiv_bits = DA7213_PLL_INDIV_5_TO_9_MHZ;
indiv = DA7213_PLL_INDIV_5_10_MHZ_VAL; indiv = DA7213_PLL_INDIV_5_TO_9_MHZ_VAL;
} else if (da7213->mclk_rate <= 20000000) { } else if (da7213->mclk_rate <= 18000000) {
indiv_bits = DA7213_PLL_INDIV_10_20_MHZ; indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7213_PLL_INDIV_10_20_MHZ_VAL; indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL;
} else if (da7213->mclk_rate <= 40000000) { } else if (da7213->mclk_rate <= 36000000) {
indiv_bits = DA7213_PLL_INDIV_20_40_MHZ; indiv_bits = DA7213_PLL_INDIV_18_TO_36_MHZ;
indiv = DA7213_PLL_INDIV_20_40_MHZ_VAL; indiv = DA7213_PLL_INDIV_18_TO_36_MHZ_VAL;
} else if (da7213->mclk_rate <= 54000000) { } else if (da7213->mclk_rate <= 54000000) {
indiv_bits = DA7213_PLL_INDIV_40_54_MHZ; indiv_bits = DA7213_PLL_INDIV_36_TO_54_MHZ;
indiv = DA7213_PLL_INDIV_40_54_MHZ_VAL; indiv = DA7213_PLL_INDIV_36_TO_54_MHZ_VAL;
} else { } else {
goto pll_err; goto pll_err;
} }
......
...@@ -163,10 +163,10 @@ ...@@ -163,10 +163,10 @@
#define DA7213_VMID_EN (0x1 << 7) #define DA7213_VMID_EN (0x1 << 7)
/* DA7213_PLL_CTRL = 0x27 */ /* DA7213_PLL_CTRL = 0x27 */
#define DA7213_PLL_INDIV_5_10_MHZ (0x0 << 2) #define DA7213_PLL_INDIV_5_TO_9_MHZ (0x0 << 2)
#define DA7213_PLL_INDIV_10_20_MHZ (0x1 << 2) #define DA7213_PLL_INDIV_9_TO_18_MHZ (0x1 << 2)
#define DA7213_PLL_INDIV_20_40_MHZ (0x2 << 2) #define DA7213_PLL_INDIV_18_TO_36_MHZ (0x2 << 2)
#define DA7213_PLL_INDIV_40_54_MHZ (0x3 << 2) #define DA7213_PLL_INDIV_36_TO_54_MHZ (0x3 << 2)
#define DA7213_PLL_INDIV_MASK (0x3 << 2) #define DA7213_PLL_INDIV_MASK (0x3 << 2)
#define DA7213_PLL_MCLK_SQR_EN (0x1 << 4) #define DA7213_PLL_MCLK_SQR_EN (0x1 << 4)
#define DA7213_PLL_32K_MODE (0x1 << 5) #define DA7213_PLL_32K_MODE (0x1 << 5)
...@@ -499,16 +499,16 @@ ...@@ -499,16 +499,16 @@
#define DA7213_ALC_AVG_ITERATIONS 5 #define DA7213_ALC_AVG_ITERATIONS 5
/* PLL related */ /* PLL related */
#define DA7213_SYSCLK_MCLK 0 #define DA7213_SYSCLK_MCLK 0
#define DA7213_SYSCLK_PLL 1 #define DA7213_SYSCLK_PLL 1
#define DA7213_PLL_FREQ_OUT_90316800 90316800 #define DA7213_PLL_FREQ_OUT_90316800 90316800
#define DA7213_PLL_FREQ_OUT_98304000 98304000 #define DA7213_PLL_FREQ_OUT_98304000 98304000
#define DA7213_PLL_FREQ_OUT_94310400 94310400 #define DA7213_PLL_FREQ_OUT_94310400 94310400
#define DA7213_PLL_INDIV_5_10_MHZ_VAL 2 #define DA7213_PLL_INDIV_5_TO_9_MHZ_VAL 2
#define DA7213_PLL_INDIV_10_20_MHZ_VAL 4 #define DA7213_PLL_INDIV_9_TO_18_MHZ_VAL 4
#define DA7213_PLL_INDIV_20_40_MHZ_VAL 8 #define DA7213_PLL_INDIV_18_TO_36_MHZ_VAL 8
#define DA7213_PLL_INDIV_40_54_MHZ_VAL 16 #define DA7213_PLL_INDIV_36_TO_54_MHZ_VAL 16
#define DA7213_SRM_CHECK_RETRIES 8 #define DA7213_SRM_CHECK_RETRIES 8
enum da7213_clk_src { enum da7213_clk_src {
DA7213_CLKSRC_MCLK = 0, DA7213_CLKSRC_MCLK = 0,
......
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