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Commit 1f2dd7bc authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'v3.19-rockchip-dts1' of... 

Merge tag 'v3.19-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Merge "first bunch on Rockchip dt changes" from Heiko Stübner:

First hunk of rockchip devicetree patches, containing:
- cpu operating points and supplies
- dma support for spi controllers
- i2s on rk3066 and rk3188
- default core clock settings for rk3288

* tag 'v3.19-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Add SPI DMA into rk3288.dtsi
  ARM: dts: rockchip: enable init rate for clock
  ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188
  ARM: dts: rockchip: enable DMA on SPI for rk3066 and rk3188
  ARM: dts: rockchip: add cpu supplies to boards
  ARM: dts: rockchip: add operating points and armclk references
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 2c49e025 11bd57b8
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Showing with 184 additions and 5 deletions
arch/arm/boot/dts/rk3066a-bqcurie2.dts
View file @ 1f2dd7bc
...@@ -60,6 +60,10 @@ button@1 { ...@@ -60,6 +60,10 @@ button@1 {
}; };
}; };
&cpu0 {
cpu0-supply = <&vdd_arm>;
};
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
......
arch/arm/boot/dts/rk3066a.dtsi
View file @ 1f2dd7bc
...@@ -26,11 +26,21 @@ cpus { ...@@ -26,11 +26,21 @@ cpus {
#size-cells = <0>; #size-cells = <0>;
enable-method = "rockchip,rk3066-smp"; enable-method = "rockchip,rk3066-smp";
cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
reg = <0x0>; reg = <0x0>;
operating-points = <
/* kHz uV */
1008000 1075000
816000 1025000
600000 1025000
504000 1000000
312000 975000
>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
...@@ -53,6 +63,51 @@ smp-sram@0 { ...@@ -53,6 +63,51 @@ smp-sram@0 {
}; };
}; };
i2s0: i2s@10118000 {
compatible = "rockchip,rk3066-i2s";
reg = <0x10118000 0x2000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
dmas = <&dmac1_s 4>, <&dmac1_s 5>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
status = "disabled";
};
i2s1: i2s@1011a000 {
compatible = "rockchip,rk3066-i2s";
reg = <0x1011a000 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
status = "disabled";
};
i2s2: i2s@1011c000 {
compatible = "rockchip,rk3066-i2s";
reg = <0x1011c000 0x2000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
dmas = <&dmac1_s 9>, <&dmac1_s 10>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
status = "disabled";
};
cru: clock-controller@20000000 { cru: clock-controller@20000000 {
compatible = "rockchip,rk3066a-cru"; compatible = "rockchip,rk3066a-cru";
reg = <0x20000000 0x1000>; reg = <0x20000000 0x1000>;
...@@ -405,6 +460,42 @@ sd1_bus4: sd1-bus-width4 { ...@@ -405,6 +460,42 @@ sd1_bus4: sd1-bus-width4 {
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
}; };
}; };
i2s0 {
i2s0_bus: i2s0-bus {
rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
};
};
i2s2 {
i2s2_bus: i2s2-bus {
rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
};
};
}; };
}; };
......
arch/arm/boot/dts/rk3188-radxarock.dts
View file @ 1f2dd7bc
...@@ -118,6 +118,10 @@ phy0: ethernet-phy@0 { ...@@ -118,6 +118,10 @@ phy0: ethernet-phy@0 {
}; };
}; };
&cpu0 {
cpu0-supply = <&vdd_arm>;
};
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
...@@ -159,7 +163,7 @@ vdd_log: REG2 { ...@@ -159,7 +163,7 @@ vdd_log: REG2 {
vdd_arm: REG3 { vdd_arm: REG3 {
regulator-name = "VDD_ARM"; regulator-name = "VDD_ARM";
regulator-min-microvolt = <875000>; regulator-min-microvolt = <875000>;
regulator-max-microvolt = <1300000>; regulator-max-microvolt = <1350000>;
regulator-always-on; regulator-always-on;
}; };
......
arch/arm/boot/dts/rk3188.dtsi
View file @ 1f2dd7bc
...@@ -26,11 +26,24 @@ cpus { ...@@ -26,11 +26,24 @@ cpus {
#size-cells = <0>; #size-cells = <0>;
enable-method = "rockchip,rk3066-smp"; enable-method = "rockchip,rk3066-smp";
cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
reg = <0x0>; reg = <0x0>;
operating-points = <
/* kHz uV */
1608000 1350000
1416000 1250000
1200000 1150000
1008000 1075000
816000 975000
600000 950000
504000 925000
312000 875000
>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
...@@ -65,6 +78,21 @@ smp-sram@0 { ...@@ -65,6 +78,21 @@ smp-sram@0 {
}; };
}; };
i2s0: i2s@1011a000 {
compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
reg = <0x1011a000 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
status = "disabled";
};
cru: clock-controller@20000000 { cru: clock-controller@20000000 {
compatible = "rockchip,rk3188-cru"; compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>; reg = <0x20000000 0x1000>;
...@@ -395,6 +423,17 @@ sd1_bus4: sd1-bus-width4 { ...@@ -395,6 +423,17 @@ sd1_bus4: sd1-bus-width4 {
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
}; };
}; };
i2s0 {
i2s0_bus: i2s0-bus {
rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
};
};
}; };
}; };
......
arch/arm/boot/dts/rk3288-evb-rk808.dts
View file @ 1f2dd7bc
...@@ -17,6 +17,10 @@ / { ...@@ -17,6 +17,10 @@ / {
compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
}; };
&cpu0 {
cpu0-supply = <&vdd_cpu>;
};
&i2c0 { &i2c0 {
clock-frequency = <400000>; clock-frequency = <400000>;
status = "okay"; status = "okay";
...@@ -44,7 +48,7 @@ vdd_cpu: DCDC_REG1 { ...@@ -44,7 +48,7 @@ vdd_cpu: DCDC_REG1 {
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <750000>; regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1300000>; regulator-max-microvolt = <1350000>;
regulator-name = "vdd_arm"; regulator-name = "vdd_arm";
}; };
......
arch/arm/boot/dts/rk3288.dtsi
View file @ 1f2dd7bc
...@@ -47,10 +47,27 @@ cpus { ...@@ -47,10 +47,27 @@ cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu@500 { cpu0: cpu@500 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a12"; compatible = "arm,cortex-a12";
reg = <0x500>; reg = <0x500>;
operating-points = <
/* KHz uV */
1608000 1350000
1512000 1300000
1416000 1200000
1200000 1100000
1008000 1050000
816000 1000000
696000 950000
600000 900000
408000 900000
312000 900000
216000 900000
126000 900000
>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
}; };
cpu@501 { cpu@501 {
device_type = "cpu"; device_type = "cpu";
...@@ -177,6 +194,8 @@ spi0: spi@ff110000 { ...@@ -177,6 +194,8 @@ spi0: spi@ff110000 {
compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk"; clock-names = "spiclk", "apb_pclk";
dmas = <&dmac_peri 11>, <&dmac_peri 12>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
...@@ -190,6 +209,8 @@ spi1: spi@ff120000 { ...@@ -190,6 +209,8 @@ spi1: spi@ff120000 {
compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk"; clock-names = "spiclk", "apb_pclk";
dmas = <&dmac_peri 13>, <&dmac_peri 14>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
...@@ -203,6 +224,8 @@ spi2: spi@ff130000 { ...@@ -203,6 +224,8 @@ spi2: spi@ff130000 {
compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
clock-names = "spiclk", "apb_pclk"; clock-names = "spiclk", "apb_pclk";
dmas = <&dmac_peri 15>, <&dmac_peri 16>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
...@@ -455,6 +478,16 @@ cru: clock-controller@ff760000 { ...@@ -455,6 +478,16 @@ cru: clock-controller@ff760000 {
rockchip,grf = <&grf>; rockchip,grf = <&grf>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>, <&cru ACLK_CPU>,
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
<&cru PCLK_PERI>;
assigned-clock-rates = <594000000>, <400000000>,
<500000000>, <300000000>,
<150000000>, <75000000>,
<300000000>, <150000000>,
<75000000>;
}; };
grf: syscon@ff770000 { grf: syscon@ff770000 {
......
arch/arm/boot/dts/rk3xxx.dtsi
View file @ 1f2dd7bc
...@@ -367,6 +367,8 @@ spi0: spi@20070000 { ...@@ -367,6 +367,8 @@ spi0: spi@20070000 {
reg = <0x20070000 0x1000>; reg = <0x20070000 0x1000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
dmas = <&dmac2 10>, <&dmac2 11>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
...@@ -378,6 +380,8 @@ spi1: spi@20074000 { ...@@ -378,6 +380,8 @@ spi1: spi@20074000 {
reg = <0x20074000 0x1000>; reg = <0x20074000 0x1000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
dmas = <&dmac2 12>, <&dmac2 13>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
}; };
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