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Commit 1f6c62ca authored by Nickey Yang's avatar Nickey Yang Committed by Heiko Stuebner
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drm/rockchip: vop: add the definition of dclk_pol 

Some VOP's (such as px30) dclk_pol bit is at the last.
So it is necessary to distinguish dclk_pol and pin_pol.
Signed-off-by: default avatarNickey Yang <nickey.yang@rock-chips.com>
Reviewed-by: default avatarSandy Huang <hjc@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20191010034452.20260-2-nickey.yang@rock-chips.com
parent c7337670
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Showing with 43 additions and 22 deletions
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View file @ 1f6c62ca
...@@ -1198,9 +1198,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, ...@@ -1198,9 +1198,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
return; return;
} }
pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
pin_pol = BIT(DCLK_INVERT);
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
BIT(HSYNC_POSITIVE) : 0; BIT(HSYNC_POSITIVE) : 0;
pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
BIT(VSYNC_POSITIVE) : 0; BIT(VSYNC_POSITIVE) : 0;
...@@ -1209,25 +1207,29 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, ...@@ -1209,25 +1207,29 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
switch (s->output_type) { switch (s->output_type) {
case DRM_MODE_CONNECTOR_LVDS: case DRM_MODE_CONNECTOR_LVDS:
VOP_REG_SET(vop, output, rgb_en, 1); VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
VOP_REG_SET(vop, output, rgb_en, 1);
break; break;
case DRM_MODE_CONNECTOR_eDP: case DRM_MODE_CONNECTOR_eDP:
VOP_REG_SET(vop, output, edp_dclk_pol, 1);
VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
VOP_REG_SET(vop, output, edp_en, 1); VOP_REG_SET(vop, output, edp_en, 1);
break; break;
case DRM_MODE_CONNECTOR_HDMIA: case DRM_MODE_CONNECTOR_HDMIA:
VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
VOP_REG_SET(vop, output, hdmi_en, 1); VOP_REG_SET(vop, output, hdmi_en, 1);
break; break;
case DRM_MODE_CONNECTOR_DSI: case DRM_MODE_CONNECTOR_DSI:
VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
VOP_REG_SET(vop, output, mipi_en, 1); VOP_REG_SET(vop, output, mipi_en, 1);
VOP_REG_SET(vop, output, mipi_dual_channel_en, VOP_REG_SET(vop, output, mipi_dual_channel_en,
!!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
break; break;
case DRM_MODE_CONNECTOR_DisplayPort: case DRM_MODE_CONNECTOR_DisplayPort:
pin_pol &= ~BIT(DCLK_INVERT); VOP_REG_SET(vop, output, dp_dclk_pol, 0);
VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
VOP_REG_SET(vop, output, dp_en, 1); VOP_REG_SET(vop, output, dp_en, 1);
break; break;
......
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View file @ 1f6c62ca
...@@ -46,10 +46,15 @@ struct vop_modeset { ...@@ -46,10 +46,15 @@ struct vop_modeset {
struct vop_output { struct vop_output {
struct vop_reg pin_pol; struct vop_reg pin_pol;
struct vop_reg dp_pin_pol; struct vop_reg dp_pin_pol;
struct vop_reg dp_dclk_pol;
struct vop_reg edp_pin_pol; struct vop_reg edp_pin_pol;
struct vop_reg edp_dclk_pol;
struct vop_reg hdmi_pin_pol; struct vop_reg hdmi_pin_pol;
struct vop_reg hdmi_dclk_pol;
struct vop_reg mipi_pin_pol; struct vop_reg mipi_pin_pol;
struct vop_reg mipi_dclk_pol;
struct vop_reg rgb_pin_pol; struct vop_reg rgb_pin_pol;
struct vop_reg rgb_dclk_pol;
struct vop_reg dp_en; struct vop_reg dp_en;
struct vop_reg edp_en; struct vop_reg edp_en;
struct vop_reg hdmi_en; struct vop_reg hdmi_en;
...@@ -296,8 +301,7 @@ enum dither_down_mode_sel { ...@@ -296,8 +301,7 @@ enum dither_down_mode_sel {
enum vop_pol { enum vop_pol {
HSYNC_POSITIVE = 0, HSYNC_POSITIVE = 0,
VSYNC_POSITIVE = 1, VSYNC_POSITIVE = 1,
DEN_NEGATIVE = 2, DEN_NEGATIVE = 2
DCLK_INVERT = 3
}; };
#define FRAC_16_16(mult, div) (((mult) << 16) / (div)) #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
......
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View file @ 1f6c62ca
...@@ -215,9 +215,11 @@ static const struct vop_modeset px30_modeset = { ...@@ -215,9 +215,11 @@ static const struct vop_modeset px30_modeset = {
}; };
static const struct vop_output px30_output = { static const struct vop_output px30_output = {
.rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 1), .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1),
.mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 25), .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2),
.rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0),
.mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25),
.mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26),
.mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24),
}; };
...@@ -720,10 +722,14 @@ static const struct vop_win_data rk3368_vop_win_data[] = { ...@@ -720,10 +722,14 @@ static const struct vop_win_data rk3368_vop_win_data[] = {
}; };
static const struct vop_output rk3368_output = { static const struct vop_output rk3368_output = {
.rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
.hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
.edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
.mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
.rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
.hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
.edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
.mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
...@@ -767,11 +773,16 @@ static const struct vop_data rk3366_vop = { ...@@ -767,11 +773,16 @@ static const struct vop_data rk3366_vop = {
}; };
static const struct vop_output rk3399_output = { static const struct vop_output rk3399_output = {
.dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), .dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19),
.rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
.hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
.edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
.mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
.dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16),
.rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
.hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
.edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
.mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
.dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
...@@ -875,14 +886,18 @@ static const struct vop_modeset rk3328_modeset = { ...@@ -875,14 +886,18 @@ static const struct vop_modeset rk3328_modeset = {
}; };
static const struct vop_output rk3328_output = { static const struct vop_output rk3328_output = {
.rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
.hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
.edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
.mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
.rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
.hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
.edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
.mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
.rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
.hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
.edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
.mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
}; };
static const struct vop_misc rk3328_misc = { static const struct vop_misc rk3328_misc = {
......
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