Commit 200ffb15 authored by Quinn Tran's avatar Quinn Tran Committed by Bart Van Assche

qla2xxx: Reduce exess wait during chip reset

Soft reset and Risc reset should take 100uS to complete.
This change pad the timeout up to 400uS, which should be
plenty.
Signed-off-by: default avatarQuinn Tran <quinn.tran@cavium.com>
Signed-off-by: default avatarHimanshu Madhani <himanshu.madhani@cavium.com>
Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarBart Van Assche <bart.vanassche@sandisk.com>
parent 5f35509d
...@@ -1191,7 +1191,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha) ...@@ -1191,7 +1191,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha)
/* Wait for soft-reset to complete. */ /* Wait for soft-reset to complete. */
RD_REG_DWORD(&reg->ctrl_status); RD_REG_DWORD(&reg->ctrl_status);
for (cnt = 0; cnt < 6000000; cnt++) { for (cnt = 0; cnt < 60; cnt++) {
barrier(); barrier();
if ((RD_REG_DWORD(&reg->ctrl_status) & if ((RD_REG_DWORD(&reg->ctrl_status) &
CSRX_ISP_SOFT_RESET) == 0) CSRX_ISP_SOFT_RESET) == 0)
...@@ -1234,7 +1234,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha) ...@@ -1234,7 +1234,7 @@ qla24xx_reset_risc(scsi_qla_host_t *vha)
RD_REG_DWORD(&reg->hccr); RD_REG_DWORD(&reg->hccr);
RD_REG_WORD(&reg->mailbox0); RD_REG_WORD(&reg->mailbox0);
for (cnt = 6000000; RD_REG_WORD(&reg->mailbox0) != 0 && for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
rval == QLA_SUCCESS; cnt--) { rval == QLA_SUCCESS; cnt--) {
barrier(); barrier();
if (cnt) if (cnt)
......
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