Commit 20a09459 authored by Chris Wilson's avatar Chris Wilson Committed by Eric Anholt

drm/i915: Write to display base last.

Writing to the DSPBASE register triggers the double-buffered update to
all the control registers, so always write it last in the update
sequence.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 1d8e1c75
...@@ -1585,15 +1585,13 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, ...@@ -1585,15 +1585,13 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
Start, Offset, x, y, crtc->fb->pitch); Start, Offset, x, y, crtc->fb->pitch);
I915_WRITE(dspstride, crtc->fb->pitch); I915_WRITE(dspstride, crtc->fb->pitch);
if (IS_I965G(dev)) { if (IS_I965G(dev)) {
I915_WRITE(dspbase, Offset);
I915_READ(dspbase);
I915_WRITE(dspsurf, Start); I915_WRITE(dspsurf, Start);
I915_READ(dspsurf);
I915_WRITE(dsptileoff, (y << 16) | x); I915_WRITE(dsptileoff, (y << 16) | x);
I915_WRITE(dspbase, Offset);
} else { } else {
I915_WRITE(dspbase, Start + Offset); I915_WRITE(dspbase, Start + Offset);
I915_READ(dspbase);
} }
POSTING_READ(dspbase);
if ((IS_I965G(dev) || plane == 0)) if ((IS_I965G(dev) || plane == 0))
intel_update_fbc(crtc, &crtc->mode); intel_update_fbc(crtc, &crtc->mode);
......
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