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Commit 216df828 authored by Mark A. Greer's avatar Mark A. Greer Committed by Linus Torvalds
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[PATCH] ppc32: support for Marvell EV-64260[ab]-BP eval platform 

This patch adds support for a line of evaluation platforms from Marvell
that use the Marvell GT64260[ab] host bridges.

This patch depends on the Marvell host bridge support patch (mv64x60).
Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent fe7c9be8
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Showing with 1075 additions and 994 deletions
arch/ppc/boot/simple/Makefile
View file @ 216df828
......@@ -66,7 +66,7 @@ zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE
entrypoint-$(CONFIG_OCOTEA) := 0x01000000
extra.o-$(CONFIG_OCOTEA) := pibs.o
extra.o-$(CONFIG_EV64260) := direct.o misc-ev64260.o
extra.o-$(CONFIG_EV64260) := misc-ev64260.o
end-$(CONFIG_EV64260) := ev64260
cacheflag-$(CONFIG_EV64260) := -include $(clear_L2_L3)
......
arch/ppc/boot/simple/gt64260_tty.c deleted 100644 → 0
View file @ fe7c9be8
/*
* arch/ppc/boot/simple/gt64260_tty.c
*
* Bootloader version of the embedded MPSC/UART driver for the GT64260[A].
* Note: Due to 64260A errata, DMA will be used for UART input (via SDMA).
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
/* This code assumes that the data cache has been disabled (L1, L2, L3). */
#include <linux/config.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
#include <asm/gt64260_defs.h>
extern void udelay(long);
static void stop_dma(int chan);
static u32 gt64260_base = EV64260_BRIDGE_REG_BASE; /* base addr of 64260 */
inline unsigned
gt64260_in_le32(volatile unsigned *addr)
{
unsigned ret;
__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
inline void
gt64260_out_le32(volatile unsigned *addr, int val)
{
__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
}
#define GT64260_REG_READ(offs) \
(gt64260_in_le32((volatile uint *)(gt64260_base + (offs))))
#define GT64260_REG_WRITE(offs, d) \
(gt64260_out_le32((volatile uint *)(gt64260_base + (offs)), (int)(d)))
static struct {
u32 sdc;
u32 sdcm;
u32 rx_desc;
u32 rx_buf_ptr;
u32 scrdp;
u32 tx_desc;
u32 sctdp;
u32 sftdp;
} sdma_regs;
#define SDMA_REGS_INIT(chan) { \
sdma_regs.sdc = GT64260_SDMA_##chan##_SDC; \
sdma_regs.sdcm = GT64260_SDMA_##chan##_SDCM; \
sdma_regs.rx_desc = GT64260_SDMA_##chan##_RX_DESC; \
sdma_regs.rx_buf_ptr = GT64260_SDMA_##chan##_RX_BUF_PTR; \
sdma_regs.scrdp = GT64260_SDMA_##chan##_SCRDP; \
sdma_regs.tx_desc = GT64260_SDMA_##chan##_TX_DESC; \
sdma_regs.sctdp = GT64260_SDMA_##chan##_SCTDP; \
sdma_regs.sftdp = GT64260_SDMA_##chan##_SFTDP; \
}
typedef struct {
volatile u16 bufsize;
volatile u16 bytecnt;
volatile u32 cmd_stat;
volatile u32 next_desc_ptr;
volatile u32 buffer;
} gt64260_rx_desc_t;
typedef struct {
volatile u16 bytecnt;
volatile u16 shadow;
volatile u32 cmd_stat;
volatile u32 next_desc_ptr;
volatile u32 buffer;
} gt64260_tx_desc_t;
#define MAX_RESET_WAIT 10000
#define MAX_TX_WAIT 10000
#define RX_NUM_DESC 2
#define TX_NUM_DESC 2
#define RX_BUF_SIZE 16
#define TX_BUF_SIZE 16
static gt64260_rx_desc_t rd[RX_NUM_DESC] __attribute__ ((aligned(32)));
static gt64260_tx_desc_t td[TX_NUM_DESC] __attribute__ ((aligned(32)));
static char rx_buf[RX_NUM_DESC * RX_BUF_SIZE] __attribute__ ((aligned(32)));
static char tx_buf[TX_NUM_DESC * TX_BUF_SIZE] __attribute__ ((aligned(32)));
static int cur_rd = 0;
static int cur_td = 0;
#define RX_INIT_RDP(rdp) { \
(rdp)->bufsize = 2; \
(rdp)->bytecnt = 0; \
(rdp)->cmd_stat = GT64260_SDMA_DESC_CMDSTAT_L | \
GT64260_SDMA_DESC_CMDSTAT_F | \
GT64260_SDMA_DESC_CMDSTAT_O; \
}
unsigned long
serial_init(int chan, void *ignored)
{
u32 mpsc_adjust, sdma_adjust, brg_bcr;
int i;
stop_dma(0);
stop_dma(1);
if (chan != 1) {
chan = 0; /* default to chan 0 if anything but 1 */
mpsc_adjust = 0;
sdma_adjust = 0;
brg_bcr = GT64260_BRG_0_BCR;
SDMA_REGS_INIT(0);
}
else {
mpsc_adjust = 0x1000;
sdma_adjust = 0x2000;
brg_bcr = GT64260_BRG_1_BCR;
SDMA_REGS_INIT(1);
}
/* Set up ring buffers */
for (i=0; i<RX_NUM_DESC; i++) {
RX_INIT_RDP(&rd[i]);
rd[i].buffer = (u32)&rx_buf[i * RX_BUF_SIZE];
rd[i].next_desc_ptr = (u32)&rd[i+1];
}
rd[RX_NUM_DESC - 1].next_desc_ptr = (u32)&rd[0];
for (i=0; i<TX_NUM_DESC; i++) {
td[i].bytecnt = 0;
td[i].shadow = 0;
td[i].buffer = (u32)&tx_buf[i * TX_BUF_SIZE];
td[i].cmd_stat = GT64260_SDMA_DESC_CMDSTAT_F |
GT64260_SDMA_DESC_CMDSTAT_L;
td[i].next_desc_ptr = (u32)&td[i+1];
}
td[TX_NUM_DESC - 1].next_desc_ptr = (u32)&td[0];
/* Set MPSC Routing */
GT64260_REG_WRITE(GT64260_MPSC_MRR, 0x3ffffe38);
GT64260_REG_WRITE(GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
/* MPSC 0/1 Rx & Tx get clocks BRG0/1 */
GT64260_REG_WRITE(GT64260_MPSC_RCRR, 0x00000100);
GT64260_REG_WRITE(GT64260_MPSC_TCRR, 0x00000100);
/* clear pending interrupts */
GT64260_REG_WRITE(GT64260_SDMA_INTR_MASK, 0);
GT64260_REG_WRITE(GT64260_SDMA_0_SCRDP + sdma_adjust, &rd[0]);
GT64260_REG_WRITE(GT64260_SDMA_0_SCTDP + sdma_adjust,
&td[TX_NUM_DESC - 1]);
GT64260_REG_WRITE(GT64260_SDMA_0_SFTDP + sdma_adjust,
&td[TX_NUM_DESC - 1]);
GT64260_REG_WRITE(GT64260_SDMA_0_SDC + sdma_adjust,
GT64260_SDMA_SDC_RFT | GT64260_SDMA_SDC_SFM |
GT64260_SDMA_SDC_BLMR | GT64260_SDMA_SDC_BLMT |
(3 << 12));
/* Set BRG to generate proper baud rate */
GT64260_REG_WRITE(brg_bcr, ((8 << 18) | (1 << 16) | 36));
/* Put MPSC into UART mode, no null modem, 16x clock mode */
GT64260_REG_WRITE(GT64260_MPSC_0_MMCRL + mpsc_adjust, 0x000004c4);
GT64260_REG_WRITE(GT64260_MPSC_0_MMCRH + mpsc_adjust, 0x04400400);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_1 + mpsc_adjust, 0);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_9 + mpsc_adjust, 0);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_10 + mpsc_adjust, 0);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_3 + mpsc_adjust, 4);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_4 + mpsc_adjust, 0);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_5 + mpsc_adjust, 0);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_6 + mpsc_adjust, 0);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_7 + mpsc_adjust, 0);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_8 + mpsc_adjust, 0);
/* 8 data bits, 1 stop bit */
GT64260_REG_WRITE(GT64260_MPSC_0_MPCR + mpsc_adjust, (3 << 12));
GT64260_REG_WRITE(GT64260_SDMA_0_SDCM + sdma_adjust,
GT64260_SDMA_SDCM_ERD);
GT64260_REG_WRITE(GT64260_MPSC_0_CHR_2 + sdma_adjust,
GT64260_MPSC_UART_CR_EH);
udelay(100);
return (ulong)chan;
}
static void
stop_dma(int chan)
{
u32 sdma_sdcm = GT64260_SDMA_0_SDCM;
int i;
if (chan == 1) {
sdma_sdcm = GT64260_SDMA_1_SDCM;
}
/* Abort SDMA Rx, Tx */
GT64260_REG_WRITE(sdma_sdcm,
GT64260_SDMA_SDCM_AR | GT64260_SDMA_SDCM_STD);
for (i=0; i<MAX_RESET_WAIT; i++) {
if ((GT64260_REG_READ(sdma_sdcm) & (GT64260_SDMA_SDCM_AR |
GT64260_SDMA_SDCM_AT)) == 0) break;
udelay(100);
}
return;
}
static int
wait_for_ownership(void)
{
int i;
for (i=0; i<MAX_TX_WAIT; i++) {
if ((GT64260_REG_READ(sdma_regs.sdcm) &
GT64260_SDMA_SDCM_TXD) == 0) break;
udelay(1000);
}
return (i < MAX_TX_WAIT);
}
void
serial_putc(unsigned long com_port, unsigned char c)
{
gt64260_tx_desc_t *tdp;
if (wait_for_ownership() == 0) return;
tdp = &td[cur_td];
if (++cur_td >= TX_NUM_DESC) cur_td = 0;
*(unchar *)(tdp->buffer ^ 7) = c;
tdp->bytecnt = 1;
tdp->shadow = 1;
tdp->cmd_stat = GT64260_SDMA_DESC_CMDSTAT_L |
GT64260_SDMA_DESC_CMDSTAT_F | GT64260_SDMA_DESC_CMDSTAT_O;
GT64260_REG_WRITE(sdma_regs.sctdp, tdp);
GT64260_REG_WRITE(sdma_regs.sftdp, tdp);
GT64260_REG_WRITE(sdma_regs.sdcm,
GT64260_REG_READ(sdma_regs.sdcm) | GT64260_SDMA_SDCM_TXD);
return;
}
unsigned char
serial_getc(unsigned long com_port)
{
gt64260_rx_desc_t *rdp;
unchar c = '\0';
rdp = &rd[cur_rd];
if ((rdp->cmd_stat & (GT64260_SDMA_DESC_CMDSTAT_O |
GT64260_SDMA_DESC_CMDSTAT_ES)) == 0) {
c = *(unchar *)(rdp->buffer ^ 7);
RX_INIT_RDP(rdp);
if (++cur_rd >= RX_NUM_DESC) cur_rd = 0;
}
return c;
}
int
serial_tstc(unsigned long com_port)
{
gt64260_rx_desc_t *rdp;
int loop_count = 0;
int rc = 0;
rdp = &rd[cur_rd];
/* Go thru rcv desc's until empty looking for one with data (no error)*/
while (((rdp->cmd_stat & GT64260_SDMA_DESC_CMDSTAT_O) == 0) &&
(loop_count++ < RX_NUM_DESC)) {
/* If there was an error, reinit the desc & continue */
if ((rdp->cmd_stat & GT64260_SDMA_DESC_CMDSTAT_ES) != 0) {
RX_INIT_RDP(rdp);
if (++cur_rd >= RX_NUM_DESC) cur_rd = 0;
rdp = (gt64260_rx_desc_t *)rdp->next_desc_ptr;
}
else {
rc = 1;
break;
}
}
return rc;
}
void
serial_close(unsigned long com_port)
{
stop_dma(com_port);
return;
}
arch/ppc/boot/simple/head.S
View file @ 216df828
......@@ -135,9 +135,9 @@ haveOF:
*/
#endif
#ifdef CONFIG_EV64260
/* Move 64260's base regs & CS window for external UART */
bl ev64260_init
#ifdef CONFIG_MV64X60
/* mv64x60 specific hook to do things like moving register base, etc. */
bl mv64x60_init
#endif
/* Get the load address.
......
arch/ppc/boot/simple/misc-ev64260.S
View file @ 216df828
......@@ -6,55 +6,65 @@
*
* Author: Mark Greer <mgreer@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <asm/ppc_asm.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/gt64260_defs.h>
#include <asm/mv64x60_defs.h>
#include <platforms/ev64260.h>
.globl ev64260_init
ev64260_init:
li r20,0
.globl mv64x60_board_init
mv64x60_board_init:
/* DINK doesn't enable 745x timebase, so enable here (Adrian Cox) */
mfspr r25,PVR
srwi r25,r25,16
cmplwi r25,(PVR_7450 >> 16)
bne 1f
mfspr r25,HID0
oris r25,r25,(HID0_TBEN >> 16)
mtspr HID0,r25
1:
#if (CONFIG_MV64X60_NEW_BASE != CONFIG_MV64X60_BASE)
li r23,20
/* Relocate galileo's regs */
addis r25,0,GT64260_INTERNAL_SPACE_DEFAULT_ADDR@h
ori r25,r25,GT64260_INTERNAL_SPACE_DECODE
lwbrx r26,0,(r25)
lis r24,0xffff
and r26,r26,r24
addis r24,0,EV64260_BRIDGE_REG_BASE@h
srw r24,r24,r23
or r26,r26,r24
stwbrx r26,0,(r25)
sync
/* Wait for write to take effect */
addis r25,0,EV64260_BRIDGE_REG_BASE@h
ori r25,r25,GT64260_INTERNAL_SPACE_DECODE
1: lwbrx r24,0,(r25)
cmpw r24,r26
bne 1b
/* Change CS2 (UARTS on device module) window */
addis r25,0,EV64260_BRIDGE_REG_BASE@h
ori r25,r25,GT64260_CPU_CS_DECODE_2_BOT
/*
* Change the CS2 window for the UART so that the bootloader
* can do I/O thru the UARTs.
*/
addis r25,0,CONFIG_MV64X60_NEW_BASE@h
ori r25,r25,MV64x60_CPU2DEV_2_BASE
addis r26,0,EV64260_UART_BASE@h
srw r26,r26,r23
stwbrx r26,0,(r25)
stwbrx r26,0,(r25)
sync
addis r25,0,EV64260_BRIDGE_REG_BASE@h
ori r25,r25,GT64260_CPU_CS_DECODE_2_TOP
addis r25,0,CONFIG_MV64X60_NEW_BASE@h
ori r25,r25,MV64x60_CPU2DEV_2_SIZE
addis r26,0,EV64260_UART_END@h
srw r26,r26,r23
stwbrx r26,0,(r25)
stwbrx r26,0,(r25)
sync
#endif
blr
#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
.data
.globl mv64x60_console_baud
mv64x60_console_baud:
.long EV64260_DEFAULT_BAUD
.globl mv64x60_mpsc_clk_src
mv64x60_mpsc_clk_src:
.long EV64260_MPSC_CLK_SRC
blr
.globl mv64x60_mpsc_clk_freq
mv64x60_mpsc_clk_freq:
.long EV64260_MPSC_CLK_FREQ
#endif
arch/ppc/configs/ev64260_defconfig
View file @ 216df828
This diff is collapsed.
arch/ppc/platforms/Makefile
View file @ 216df828
......@@ -23,7 +23,7 @@ obj-$(CONFIG_PREP_RESIDUAL) += residual.o
obj-$(CONFIG_ADIR) += adir_setup.o adir_pic.o adir_pci.o
obj-$(CONFIG_PQ2ADS) += pq2ads.o
obj-$(CONFIG_TQM8260) += tqm8260_setup.o
obj-$(CONFIG_EV64260) += ev64260_setup.o
obj-$(CONFIG_EV64260) += ev64260.o
obj-$(CONFIG_GEMINI) += gemini_pci.o gemini_setup.o gemini_prom.o
obj-$(CONFIG_K2) += k2.o
obj-$(CONFIG_LOPEC) += lopec.o
......
arch/ppc/platforms/ev64260.c 0 → 100644
View file @ 216df828
This diff is collapsed.
arch/ppc/platforms/ev64260.h
View file @ 216df828
......@@ -5,38 +5,103 @@
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
/*
* The GT64260 has 2 PCI buses each with 1 window from the CPU bus to
* The MV64x60 has 2 PCI buses each with 1 window from the CPU bus to
* PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
* We'll only use one PCI MEM window on each PCI bus.
*
* This is the CPU physical memory map (windows must be at least 1MB and start
* on a boundary that is a multiple of the window size):
*
* 0xfc000000-0xffffffff - External FLASH on device module
* 0xfbf00000-0xfbffffff - Embedded (on board) FLASH
* 0xfbe00000-0xfbefffff - GT64260 Registers (preferably)
* but really a config option
* 0xfbd00000-0xfbdfffff - External SRAM on device module
* 0xfbc00000-0xfbcfffff - TODC chip on device module
* 0xfbb00000-0xfbbfffff - External UART on device module
* 0xa2000000-0xfbafffff - <hole>
* 0xa1000000-0xa1ffffff - PCI 1 I/O (defined in gt64260.h)
* 0xa0000000-0xa0ffffff - PCI 0 I/O (defined in gt64260.h)
* 0x90000000-0x9fffffff - PCI 1 MEM (defined in gt64260.h)
* 0x80000000-0x8fffffff - PCI 0 MEM (defined in gt64260.h)
*/
#ifndef __PPC_PLATFORMS_EV64260_H
#define __PPC_PLATFORMS_EV64260_H
#define EV64260_BRIDGE_REG_BASE 0xf8000000
#define EV64260_BRIDGE_REG_BASE_TO_TOP 0x08000000U
/* PCI mappings */
#define EV64260_PCI0_IO_CPU_BASE 0xa0000000
#define EV64260_PCI0_IO_PCI_BASE 0x00000000
#define EV64260_PCI0_IO_SIZE 0x01000000
#define EV64260_PCI0_MEM_CPU_BASE 0x80000000
#define EV64260_PCI0_MEM_PCI_BASE 0x80000000
#define EV64260_PCI0_MEM_SIZE 0x10000000
#define EV64260_PCI1_IO_CPU_BASE (EV64260_PCI0_IO_CPU_BASE + \
EV64260_PCI0_IO_SIZE)
#define EV64260_PCI1_IO_PCI_BASE (EV64260_PCI0_IO_PCI_BASE + \
EV64260_PCI0_IO_SIZE)
#define EV64260_PCI1_IO_SIZE 0x01000000
#define EV64260_PCI1_MEM_CPU_BASE (EV64260_PCI0_MEM_CPU_BASE + \
EV64260_PCI0_MEM_SIZE)
#define EV64260_PCI1_MEM_PCI_BASE (EV64260_PCI0_MEM_PCI_BASE + \
EV64260_PCI0_MEM_SIZE)
#define EV64260_PCI1_MEM_SIZE 0x10000000
/* CPU Physical Memory Map setup (other than PCI) */
#define EV64260_EXT_FLASH_BASE 0xfc000000
#define EV64260_EMB_FLASH_BASE 0xfbf00000
#define EV64260_EXT_SRAM_BASE 0xfbd00000
#define EV64260_TODC_BASE 0xfbc00000
#define EV64260_UART_BASE 0xfbb00000
#define EV64260_EXT_FLASH_SIZE_ACTUAL 0x04000000 /* <= 64MB Extern FLASH */
#define EV64260_EMB_FLASH_SIZE_ACTUAL 0x00080000 /* 512KB of Embed FLASH */
#define EV64260_EXT_SRAM_SIZE_ACTUAL 0x00100000 /* 1MB SDRAM */
#define EV64260_TODC_SIZE_ACTUAL 0x00000020 /* 32 bytes for TODC */
#define EV64260_UART_SIZE_ACTUAL 0x00000040 /* 64 bytes for DUART */
#define EV64260_EXT_FLASH_SIZE max(GT64260_WINDOW_SIZE_MIN, \
EV64260_EXT_FLASH_SIZE_ACTUAL)
#define EV64260_EMB_FLASH_SIZE max(GT64260_WINDOW_SIZE_MIN, \
EV64260_EMB_FLASH_SIZE_ACTUAL)
#define EV64260_EXT_SRAM_SIZE max(GT64260_WINDOW_SIZE_MIN, \
EV64260_EXT_SRAM_SIZE_ACTUAL)
#define EV64260_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \
EV64260_TODC_SIZE_ACTUAL)
/* Assembler in bootwrapper blows up if 'max' is used */
#define EV64260_UART_SIZE GT64260_WINDOW_SIZE_MIN
#define EV64260_UART_END ((EV64260_UART_BASE + \
EV64260_UART_SIZE - 1) & 0xfff00000)
#define EV64260_TODC_BASE 0xfc800000
#define EV64260_TODC_LEN 0x00800000
#define EV64260_TODC_END (EV64260_TODC_BASE + \
EV64260_TODC_LEN - 1)
/* Board-specific IRQ info */
#define EV64260_UART_0_IRQ 85
#define EV64260_UART_1_IRQ 86
#define EV64260_PCI_0_IRQ 91
#define EV64260_PCI_1_IRQ 93
#define EV64260_UART_BASE 0xfd000000
#define EV64260_UART_LEN 0x00800000
#define EV64260_UART_END (EV64260_UART_BASE + \
EV64260_UART_LEN - 1)
/* Serial driver setup. */
/* Serial port setup */
#define EV64260_DEFAULT_BAUD 115200
#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
#define SERIAL_PORT_DFNS
#define EV64260_MPSC_CLK_SRC 8 /* TCLK */
#define EV64260_MPSC_CLK_FREQ 100000000 /* 100MHz clk */
#else
#define EV64260_SERIAL_0 (EV64260_UART_BASE + 0x20)
#define EV64260_SERIAL_1 EV64260_UART_BASE
#define BASE_BAUD ( 3686400 / 16 )
#define BASE_BAUD (EV64260_DEFAULT_BAUD * 2)
#ifdef CONFIG_SERIAL_MANY_PORTS
#define RS_TABLE_SIZE 64
......@@ -50,18 +115,14 @@
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
#endif
#if !defined(CONFIG_GT64260_CONSOLE)
/* Required for bootloader's ns16550.c code */
#define STD_SERIAL_PORT_DFNS \
{ 0, BASE_BAUD, EV64260_SERIAL_0, 85, STD_COM_FLAGS, /* ttyS0 */\
iomem_base: (u8 *)EV64260_SERIAL_0, \
{ 0, BASE_BAUD, EV64260_SERIAL_0, EV64260_UART_0_IRQ, STD_COM_FLAGS, \
iomem_base: (u8 *)EV64260_SERIAL_0, /* ttyS0 */ \
iomem_reg_shift: 2, \
io_type: SERIAL_IO_MEM },
#define SERIAL_PORT_DFNS \
STD_SERIAL_PORT_DFNS
#else
#define SERIAL_PORT_DFNS
#endif
#endif /* __PPC_PLATFORMS_EV64260_H */
arch/ppc/platforms/ev64260_setup.c deleted 100644 → 0
View file @ fe7c9be8
This diff is collapsed.
arch/ppc/syslib/Makefile
View file @ 216df828
......@@ -40,8 +40,7 @@ obj-$(CONFIG_PPC_PREP) += open_pic.o indirect_pci.o i8259.o todc_time.o
obj-$(CONFIG_ADIR) += i8259.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_EBONY) += indirect_pci.o pci_auto.o todc_time.o
obj-$(CONFIG_EV64260) += gt64260_common.o gt64260_pic.o \
indirect_pci.o todc_time.o pci_auto.o
obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o
obj-$(CONFIG_GEMINI) += open_pic.o indirect_pci.o
obj-$(CONFIG_GT64260) += gt64260_pic.o
obj-$(CONFIG_K2) += i8259.o indirect_pci.o todc_time.o \
......
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