Commit 217c6d21 authored by Bjorn Helgaas's avatar Bjorn Helgaas

Merge branches 'pci/host-armada', 'pci/host-artpec', 'pci/host-dra7xx',...

Merge branches 'pci/host-armada', 'pci/host-artpec', 'pci/host-dra7xx', 'pci/host-exynos', 'pci/host-hisi', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-layerscape', 'pci/host-qcom' and 'pci/host-spear' into next

* pci/host-armada:
  MAINTAINERS: Add maintainer for the PCIe Marvell Armada 8K driver
  PCI: armada: Reorder struct armada8k_pcie
  PCI: armada: Pass device-specific struct to internal functions
  PCI: armada: Use generic DesignWare accessors
  PCI: armada: Remove redundant struct armada8k_pcie.base
  PCI: armada: Add local base pointer
  PCI: armada: Remove unused platform data

* pci/host-artpec:
  PCI: artpec6: Add resource name comments
  PCI: artpec6: Pass device-specific struct to internal functions
  PCI: artpec6: Remove unnecessary artpec6_pcie_link_up()
  PCI: artpec6: Use generic DesignWare accessors
  PCI: artpec6: Add register accessors
  PCI: artpec6: Remove unused platform data
  PCI: artpec6: Add local struct device pointers

* pci/host-dra7xx:
  PCI: dra7xx: Reorder struct dra7xx_pcie
  PCI: dra7xx: Move struct pcie_port setup to probe function
  PCI: dra7xx: Pass device-specific struct to internal functions
  PCI: dra7xx: Use generic DesignWare accessors
  PCI: dra7xx: Set drvdata at end of probe function
  PCI: dra7xx: Remove redundant struct device pointer from dra7xx_pcie
  PCI: dra7xx: Add local struct device pointers

* pci/host-exynos:
  PCI: exynos: Reorder struct exynos_pcie
  PCI: exynos: Pass device-specific struct to internal functions
  PCI: exynos: Name private struct pointer "exynos_pcie" consistently
  PCI: exynos: Uninline register accessors
  PCI: exynos: Add local struct device pointers

* pci/host-hisi:
  PCI: hisi: Reorder struct hisi_pcie
  PCI: hisi: Pass device-specific struct to internal functions
  PCI: hisi: Include register block base in PCIE_SYS_STATE4 address
  PCI: hisi: Use generic DesignWare accessors
  PCI: hisi: Remove redundant struct hisi_pcie.reg_base
  PCI: hisi: Name private struct pointer "hisi_pcie" consistently
  PCI: hisi: Remove unused platform data
  PCI: hisi: Add local struct device pointers

* pci/host-imx6:
  PCI: imx6: Remove unused return values
  PCI: imx6: Reorder struct imx6_pcie
  PCI: imx6: Use generic DesignWare accessors
  PCI: imx6: Pass device-specific struct to internal functions
  PCI: imx6: Pass struct imx6_pcie to PHY accessors
  PCI: imx6: Removed unused struct imx6_pcie.mem_base
  PCI: imx6: Remove redundant of_node pointer
  PCI: imx6: Add local struct device pointers

* pci/host-keystone:
  PCI: keystone: Reorder struct keystone_pcie
  PCI: keystone: Add app register accessors
  PCI: keystone: Pass keystone_pcie, not va_app_base, to DBI functions
  PCI: keystone: Pass keystone_pcie, not address, to IRQ functions
  PCI: keystone: Use generic DesignWare accessors
  PCI: keystone: Add local struct device pointers

* pci/host-layerscape:
  PCI: layerscape: Reorder struct ls_pcie
  PCI: layerscape: Remove unused ls_add_pcie_port() platform_device arg
  PCI: layerscape: Move struct pcie_port setup to probe function
  PCI: layerscape: Pass device-specific struct to internal functions
  PCI: layerscape: Remove redundant struct ls_pcie.dbi
  PCI: layerscape: Remove unused platform data
  PCI: layerscape: Add local struct device pointers

* pci/host-qcom:
  PCI: qcom: Reorder struct qcom_pcie
  PCI: qcom: Remove redundant struct qcom_pcie.dev
  PCI: qcom: Remove redundant struct qcom_pcie.dbi
  PCI: qcom: Remove unused platform data

* pci/host-spear:
  PCI: spear: Clean up struct device usage
  PCI: spear: Reorder struct spear13xx_pcie
  PCI: spear: Pass device-specific struct to internal functions
  PCI: spear: Remove unused constants
...@@ -8936,6 +8936,14 @@ S: Maintained ...@@ -8936,6 +8936,14 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/versatile.txt F: Documentation/devicetree/bindings/pci/versatile.txt
F: drivers/pci/host/pci-versatile.c F: drivers/pci/host/pci-versatile.c
PCI DRIVER FOR ARMADA 8K
M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
L: linux-pci@vger.kernel.org
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/pci/pci-armada8k.txt
F: drivers/pci/host/pcie-armada8k.c
PCI DRIVER FOR APPLIEDMICRO XGENE PCI DRIVER FOR APPLIEDMICRO XGENE
M: Tanmay Inamdar <tinamdar@apm.com> M: Tanmay Inamdar <tinamdar@apm.com>
L: linux-pci@vger.kernel.org L: linux-pci@vger.kernel.org
......
...@@ -64,11 +64,10 @@ ...@@ -64,11 +64,10 @@
#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
struct dra7xx_pcie { struct dra7xx_pcie {
void __iomem *base;
struct phy **phy;
int phy_count;
struct device *dev;
struct pcie_port pp; struct pcie_port pp;
void __iomem *base; /* DT ti_conf */
int phy_count; /* DT phy-names count */
struct phy **phy;
}; };
#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp) #define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
...@@ -84,17 +83,6 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, ...@@ -84,17 +83,6 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
writel(value, pcie->base + offset); writel(value, pcie->base + offset);
} }
static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
{
return readl(pp->dbi_base + offset);
}
static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
u32 value)
{
writel(value, pp->dbi_base + offset);
}
static int dra7xx_pcie_link_up(struct pcie_port *pp) static int dra7xx_pcie_link_up(struct pcie_port *pp)
{ {
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
...@@ -103,13 +91,14 @@ static int dra7xx_pcie_link_up(struct pcie_port *pp) ...@@ -103,13 +91,14 @@ static int dra7xx_pcie_link_up(struct pcie_port *pp)
return !!(reg & LINK_UP); return !!(reg & LINK_UP);
} }
static int dra7xx_pcie_establish_link(struct pcie_port *pp) static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
{ {
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); struct pcie_port *pp = &dra7xx->pp;
struct device *dev = pp->dev;
u32 reg; u32 reg;
if (dw_pcie_link_up(pp)) { if (dw_pcie_link_up(pp)) {
dev_err(pp->dev, "link is already up\n"); dev_err(dev, "link is already up\n");
return 0; return 0;
} }
...@@ -120,10 +109,8 @@ static int dra7xx_pcie_establish_link(struct pcie_port *pp) ...@@ -120,10 +109,8 @@ static int dra7xx_pcie_establish_link(struct pcie_port *pp)
return dw_pcie_wait_for_link(pp); return dw_pcie_wait_for_link(pp);
} }
static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp) static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
{ {
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
~INTERRUPTS); ~INTERRUPTS);
dra7xx_pcie_writel(dra7xx, dra7xx_pcie_writel(dra7xx,
...@@ -142,6 +129,8 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp) ...@@ -142,6 +129,8 @@ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
static void dra7xx_pcie_host_init(struct pcie_port *pp) static void dra7xx_pcie_host_init(struct pcie_port *pp)
{ {
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR; pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR; pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR; pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
...@@ -149,10 +138,10 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp) ...@@ -149,10 +138,10 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
dw_pcie_setup_rc(pp); dw_pcie_setup_rc(pp);
dra7xx_pcie_establish_link(pp); dra7xx_pcie_establish_link(dra7xx);
if (IS_ENABLED(CONFIG_PCI_MSI)) if (IS_ENABLED(CONFIG_PCI_MSI))
dw_pcie_msi_init(pp); dw_pcie_msi_init(pp);
dra7xx_pcie_enable_interrupts(pp); dra7xx_pcie_enable_interrupts(dra7xx);
} }
static struct pcie_host_ops dra7xx_pcie_host_ops = { static struct pcie_host_ops dra7xx_pcie_host_ops = {
...@@ -196,8 +185,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) ...@@ -196,8 +185,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
{ {
struct pcie_port *pp = arg; struct dra7xx_pcie *dra7xx = arg;
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); struct pcie_port *pp = &dra7xx->pp;
u32 reg; u32 reg;
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
...@@ -223,51 +212,51 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) ...@@ -223,51 +212,51 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
{ {
struct dra7xx_pcie *dra7xx = arg; struct dra7xx_pcie *dra7xx = arg;
struct device *dev = dra7xx->pp.dev;
u32 reg; u32 reg;
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
if (reg & ERR_SYS) if (reg & ERR_SYS)
dev_dbg(dra7xx->dev, "System Error\n"); dev_dbg(dev, "System Error\n");
if (reg & ERR_FATAL) if (reg & ERR_FATAL)
dev_dbg(dra7xx->dev, "Fatal Error\n"); dev_dbg(dev, "Fatal Error\n");
if (reg & ERR_NONFATAL) if (reg & ERR_NONFATAL)
dev_dbg(dra7xx->dev, "Non Fatal Error\n"); dev_dbg(dev, "Non Fatal Error\n");
if (reg & ERR_COR) if (reg & ERR_COR)
dev_dbg(dra7xx->dev, "Correctable Error\n"); dev_dbg(dev, "Correctable Error\n");
if (reg & ERR_AXI) if (reg & ERR_AXI)
dev_dbg(dra7xx->dev, "AXI tag lookup fatal Error\n"); dev_dbg(dev, "AXI tag lookup fatal Error\n");
if (reg & ERR_ECRC) if (reg & ERR_ECRC)
dev_dbg(dra7xx->dev, "ECRC Error\n"); dev_dbg(dev, "ECRC Error\n");
if (reg & PME_TURN_OFF) if (reg & PME_TURN_OFF)
dev_dbg(dra7xx->dev, dev_dbg(dev,
"Power Management Event Turn-Off message received\n"); "Power Management Event Turn-Off message received\n");
if (reg & PME_TO_ACK) if (reg & PME_TO_ACK)
dev_dbg(dra7xx->dev, dev_dbg(dev,
"Power Management Turn-Off Ack message received\n"); "Power Management Turn-Off Ack message received\n");
if (reg & PM_PME) if (reg & PM_PME)
dev_dbg(dra7xx->dev, dev_dbg(dev, "PM Power Management Event message received\n");
"PM Power Management Event message received\n");
if (reg & LINK_REQ_RST) if (reg & LINK_REQ_RST)
dev_dbg(dra7xx->dev, "Link Request Reset\n"); dev_dbg(dev, "Link Request Reset\n");
if (reg & LINK_UP_EVT) if (reg & LINK_UP_EVT)
dev_dbg(dra7xx->dev, "Link-up state change\n"); dev_dbg(dev, "Link-up state change\n");
if (reg & CFG_BME_EVT) if (reg & CFG_BME_EVT)
dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n"); dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
if (reg & CFG_MSE_EVT) if (reg & CFG_MSE_EVT)
dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n"); dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg); dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
...@@ -278,13 +267,9 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, ...@@ -278,13 +267,9 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
struct platform_device *pdev) struct platform_device *pdev)
{ {
int ret; int ret;
struct pcie_port *pp; struct pcie_port *pp = &dra7xx->pp;
struct device *dev = pp->dev;
struct resource *res; struct resource *res;
struct device *dev = &pdev->dev;
pp = &dra7xx->pp;
pp->dev = dev;
pp->ops = &dra7xx_pcie_host_ops;
pp->irq = platform_get_irq(pdev, 1); pp->irq = platform_get_irq(pdev, 1);
if (pp->irq < 0) { if (pp->irq < 0) {
...@@ -292,12 +277,11 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, ...@@ -292,12 +277,11 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
return -EINVAL; return -EINVAL;
} }
ret = devm_request_irq(&pdev->dev, pp->irq, ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
dra7xx_pcie_msi_irq_handler,
IRQF_SHARED | IRQF_NO_THREAD, IRQF_SHARED | IRQF_NO_THREAD,
"dra7-pcie-msi", pp); "dra7-pcie-msi", dra7xx);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to request irq\n"); dev_err(dev, "failed to request irq\n");
return ret; return ret;
} }
...@@ -314,7 +298,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx, ...@@ -314,7 +298,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
ret = dw_pcie_host_init(pp); ret = dw_pcie_host_init(pp);
if (ret) { if (ret) {
dev_err(dra7xx->dev, "failed to initialize host\n"); dev_err(dev, "failed to initialize host\n");
return ret; return ret;
} }
...@@ -332,6 +316,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) ...@@ -332,6 +316,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
void __iomem *base; void __iomem *base;
struct resource *res; struct resource *res;
struct dra7xx_pcie *dra7xx; struct dra7xx_pcie *dra7xx;
struct pcie_port *pp;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node; struct device_node *np = dev->of_node;
char name[10]; char name[10];
...@@ -343,6 +328,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) ...@@ -343,6 +328,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
if (!dra7xx) if (!dra7xx)
return -ENOMEM; return -ENOMEM;
pp = &dra7xx->pp;
pp->dev = dev;
pp->ops = &dra7xx_pcie_host_ops;
irq = platform_get_irq(pdev, 0); irq = platform_get_irq(pdev, 0);
if (irq < 0) { if (irq < 0) {
dev_err(dev, "missing IRQ resource\n"); dev_err(dev, "missing IRQ resource\n");
...@@ -390,7 +379,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) ...@@ -390,7 +379,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
dra7xx->base = base; dra7xx->base = base;
dra7xx->phy = phy; dra7xx->phy = phy;
dra7xx->dev = dev;
dra7xx->phy_count = phy_count; dra7xx->phy_count = phy_count;
pm_runtime_enable(dev); pm_runtime_enable(dev);
...@@ -407,7 +395,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) ...@@ -407,7 +395,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags, ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags,
"pcie_reset"); "pcie_reset");
if (ret) { if (ret) {
dev_err(&pdev->dev, "gpio%d request failed, ret %d\n", dev_err(dev, "gpio%d request failed, ret %d\n",
gpio_sel, ret); gpio_sel, ret);
goto err_gpio; goto err_gpio;
} }
...@@ -420,12 +408,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) ...@@ -420,12 +408,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
reg &= ~LTSSM_EN; reg &= ~LTSSM_EN;
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
platform_set_drvdata(pdev, dra7xx);
ret = dra7xx_add_pcie_port(dra7xx, pdev); ret = dra7xx_add_pcie_port(dra7xx, pdev);
if (ret < 0) if (ret < 0)
goto err_gpio; goto err_gpio;
platform_set_drvdata(pdev, dra7xx);
return 0; return 0;
err_gpio: err_gpio:
...@@ -451,9 +438,9 @@ static int dra7xx_pcie_suspend(struct device *dev) ...@@ -451,9 +438,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
u32 val; u32 val;
/* clear MSE */ /* clear MSE */
val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND); val = dw_pcie_readl_rc(pp, PCI_COMMAND);
val &= ~PCI_COMMAND_MEMORY; val &= ~PCI_COMMAND_MEMORY;
dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val); dw_pcie_writel_rc(pp, PCI_COMMAND, val);
return 0; return 0;
} }
...@@ -465,9 +452,9 @@ static int dra7xx_pcie_resume(struct device *dev) ...@@ -465,9 +452,9 @@ static int dra7xx_pcie_resume(struct device *dev)
u32 val; u32 val;
/* set MSE */ /* set MSE */
val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND); val = dw_pcie_readl_rc(pp, PCI_COMMAND);
val |= PCI_COMMAND_MEMORY; val |= PCI_COMMAND_MEMORY;
dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val); dw_pcie_writel_rc(pp, PCI_COMMAND, val);
return 0; return 0;
} }
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
...@@ -89,12 +89,13 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs); ...@@ -89,12 +89,13 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
{ {
struct pcie_port *pp = &ks_pcie->pp; struct pcie_port *pp = &ks_pcie->pp;
struct device *dev = pp->dev;
unsigned int retries; unsigned int retries;
dw_pcie_setup_rc(pp); dw_pcie_setup_rc(pp);
if (dw_pcie_link_up(pp)) { if (dw_pcie_link_up(pp)) {
dev_err(pp->dev, "Link already up\n"); dev_err(dev, "Link already up\n");
return 0; return 0;
} }
...@@ -105,7 +106,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) ...@@ -105,7 +106,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
return 0; return 0;
} }
dev_err(pp->dev, "phy link never came up\n"); dev_err(dev, "phy link never came up\n");
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -115,9 +116,10 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc) ...@@ -115,9 +116,10 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
u32 offset = irq - ks_pcie->msi_host_irqs[0]; u32 offset = irq - ks_pcie->msi_host_irqs[0];
struct pcie_port *pp = &ks_pcie->pp; struct pcie_port *pp = &ks_pcie->pp;
struct device *dev = pp->dev;
struct irq_chip *chip = irq_desc_get_chip(desc); struct irq_chip *chip = irq_desc_get_chip(desc);
dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq); dev_dbg(dev, "%s, irq %d\n", __func__, irq);
/* /*
* The chained irq handler installation would have replaced normal * The chained irq handler installation would have replaced normal
...@@ -142,10 +144,11 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) ...@@ -142,10 +144,11 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
unsigned int irq = irq_desc_get_irq(desc); unsigned int irq = irq_desc_get_irq(desc);
struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
struct pcie_port *pp = &ks_pcie->pp; struct pcie_port *pp = &ks_pcie->pp;
struct device *dev = pp->dev;
u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
struct irq_chip *chip = irq_desc_get_chip(desc); struct irq_chip *chip = irq_desc_get_chip(desc);
dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq); dev_dbg(dev, ": Handling legacy irq %d\n", irq);
/* /*
* The chained irq handler installation would have replaced normal * The chained irq handler installation would have replaced normal
...@@ -234,7 +237,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) ...@@ -234,7 +237,7 @@ static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
} }
if (ks_pcie->error_irq > 0) if (ks_pcie->error_irq > 0)
ks_dw_pcie_enable_error_irq(ks_pcie->va_app_base); ks_dw_pcie_enable_error_irq(ks_pcie);
} }
/* /*
...@@ -302,14 +305,14 @@ static irqreturn_t pcie_err_irq_handler(int irq, void *priv) ...@@ -302,14 +305,14 @@ static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
{ {
struct keystone_pcie *ks_pcie = priv; struct keystone_pcie *ks_pcie = priv;
return ks_dw_pcie_handle_error_irq(ks_pcie->pp.dev, return ks_dw_pcie_handle_error_irq(ks_pcie);
ks_pcie->va_app_base);
} }
static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
struct platform_device *pdev) struct platform_device *pdev)
{ {
struct pcie_port *pp = &ks_pcie->pp; struct pcie_port *pp = &ks_pcie->pp;
struct device *dev = pp->dev;
int ret; int ret;
ret = ks_pcie_get_irq_controller_info(ks_pcie, ret = ks_pcie_get_irq_controller_info(ks_pcie,
...@@ -332,12 +335,12 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, ...@@ -332,12 +335,12 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
*/ */
ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0); ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
if (ks_pcie->error_irq <= 0) if (ks_pcie->error_irq <= 0)
dev_info(&pdev->dev, "no error IRQ defined\n"); dev_info(dev, "no error IRQ defined\n");
else { else {
ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler, ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
IRQF_SHARED, "pcie-error-irq", ks_pcie); IRQF_SHARED, "pcie-error-irq", ks_pcie);
if (ret < 0) { if (ret < 0) {
dev_err(&pdev->dev, "failed to request error IRQ %d\n", dev_err(dev, "failed to request error IRQ %d\n",
ks_pcie->error_irq); ks_pcie->error_irq);
return ret; return ret;
} }
...@@ -347,7 +350,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, ...@@ -347,7 +350,7 @@ static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
pp->ops = &keystone_pcie_host_ops; pp->ops = &keystone_pcie_host_ops;
ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np); ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to initialize host\n"); dev_err(dev, "failed to initialize host\n");
return ret; return ret;
} }
...@@ -381,12 +384,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ...@@ -381,12 +384,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
struct phy *phy; struct phy *phy;
int ret; int ret;
ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie), ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
GFP_KERNEL);
if (!ks_pcie) if (!ks_pcie)
return -ENOMEM; return -ENOMEM;
pp = &ks_pcie->pp; pp = &ks_pcie->pp;
pp->dev = dev;
/* initialize SerDes Phy if present */ /* initialize SerDes Phy if present */
phy = devm_phy_get(dev, "pcie-phy"); phy = devm_phy_get(dev, "pcie-phy");
...@@ -408,7 +411,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ...@@ -408,7 +411,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
devm_iounmap(dev, reg_p); devm_iounmap(dev, reg_p);
devm_release_mem_region(dev, res->start, resource_size(res)); devm_release_mem_region(dev, res->start, resource_size(res));
pp->dev = dev;
ks_pcie->np = dev->of_node; ks_pcie->np = dev->of_node;
platform_set_drvdata(pdev, ks_pcie); platform_set_drvdata(pdev, ks_pcie);
ks_pcie->clk = devm_clk_get(dev, "pcie"); ks_pcie->clk = devm_clk_get(dev, "pcie");
......
...@@ -17,8 +17,8 @@ ...@@ -17,8 +17,8 @@
#define MAX_LEGACY_HOST_IRQS 4 #define MAX_LEGACY_HOST_IRQS 4
struct keystone_pcie { struct keystone_pcie {
struct pcie_port pp; /* pp.dbi_base is DT 0th res */
struct clk *clk; struct clk *clk;
struct pcie_port pp;
/* PCI Device ID */ /* PCI Device ID */
u32 device_id; u32 device_id;
int num_legacy_host_irqs; int num_legacy_host_irqs;
...@@ -34,7 +34,7 @@ struct keystone_pcie { ...@@ -34,7 +34,7 @@ struct keystone_pcie {
int error_irq; int error_irq;
/* Application register space */ /* Application register space */
void __iomem *va_app_base; void __iomem *va_app_base; /* DT 1st resource */
struct resource app; struct resource app;
}; };
...@@ -45,9 +45,8 @@ phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp); ...@@ -45,9 +45,8 @@ phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
/* Keystone specific PCI controller APIs */ /* Keystone specific PCI controller APIs */
void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie); void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset); void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
void ks_dw_pcie_enable_error_irq(void __iomem *reg_base); void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie);
irqreturn_t ks_dw_pcie_handle_error_irq(struct device *dev, irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie);
void __iomem *reg_base);
int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
struct device_node *msi_intc_np); struct device_node *msi_intc_np);
int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
......
...@@ -45,10 +45,9 @@ struct ls_pcie_drvdata { ...@@ -45,10 +45,9 @@ struct ls_pcie_drvdata {
}; };
struct ls_pcie { struct ls_pcie {
void __iomem *dbi; struct pcie_port pp; /* pp.dbi_base is DT regs */
void __iomem *lut; void __iomem *lut;
struct regmap *scfg; struct regmap *scfg;
struct pcie_port pp;
const struct ls_pcie_drvdata *drvdata; const struct ls_pcie_drvdata *drvdata;
int index; int index;
}; };
...@@ -59,7 +58,7 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie) ...@@ -59,7 +58,7 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
{ {
u32 header_type; u32 header_type;
header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE); header_type = ioread8(pcie->pp.dbi_base + PCI_HEADER_TYPE);
header_type &= 0x7f; header_type &= 0x7f;
return header_type == PCI_HEADER_TYPE_BRIDGE; return header_type == PCI_HEADER_TYPE_BRIDGE;
...@@ -68,13 +67,13 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie) ...@@ -68,13 +67,13 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
/* Clear multi-function bit */ /* Clear multi-function bit */
static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
{ {
iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->pp.dbi_base + PCI_HEADER_TYPE);
} }
/* Fix class value */ /* Fix class value */
static void ls_pcie_fix_class(struct ls_pcie *pcie) static void ls_pcie_fix_class(struct ls_pcie *pcie)
{ {
iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->pp.dbi_base + PCI_CLASS_DEVICE);
} }
/* Drop MSG TLP except for Vendor MSG */ /* Drop MSG TLP except for Vendor MSG */
...@@ -82,9 +81,9 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) ...@@ -82,9 +81,9 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
{ {
u32 val; u32 val;
val = ioread32(pcie->dbi + PCIE_STRFMR1); val = ioread32(pcie->pp.dbi_base + PCIE_STRFMR1);
val &= 0xDFFFFFFF; val &= 0xDFFFFFFF;
iowrite32(val, pcie->dbi + PCIE_STRFMR1); iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
} }
static int ls1021_pcie_link_up(struct pcie_port *pp) static int ls1021_pcie_link_up(struct pcie_port *pp)
...@@ -106,18 +105,19 @@ static int ls1021_pcie_link_up(struct pcie_port *pp) ...@@ -106,18 +105,19 @@ static int ls1021_pcie_link_up(struct pcie_port *pp)
static void ls1021_pcie_host_init(struct pcie_port *pp) static void ls1021_pcie_host_init(struct pcie_port *pp)
{ {
struct device *dev = pp->dev;
struct ls_pcie *pcie = to_ls_pcie(pp); struct ls_pcie *pcie = to_ls_pcie(pp);
u32 index[2]; u32 index[2];
pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
"fsl,pcie-scfg"); "fsl,pcie-scfg");
if (IS_ERR(pcie->scfg)) { if (IS_ERR(pcie->scfg)) {
dev_err(pp->dev, "No syscfg phandle specified\n"); dev_err(dev, "No syscfg phandle specified\n");
pcie->scfg = NULL; pcie->scfg = NULL;
return; return;
} }
if (of_property_read_u32_array(pp->dev->of_node, if (of_property_read_u32_array(dev->of_node,
"fsl,pcie-scfg", index, 2)) { "fsl,pcie-scfg", index, 2)) {
pcie->scfg = NULL; pcie->scfg = NULL;
return; return;
...@@ -148,18 +148,19 @@ static void ls_pcie_host_init(struct pcie_port *pp) ...@@ -148,18 +148,19 @@ static void ls_pcie_host_init(struct pcie_port *pp)
{ {
struct ls_pcie *pcie = to_ls_pcie(pp); struct ls_pcie *pcie = to_ls_pcie(pp);
iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); iowrite32(1, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
ls_pcie_fix_class(pcie); ls_pcie_fix_class(pcie);
ls_pcie_clear_multifunction(pcie); ls_pcie_clear_multifunction(pcie);
ls_pcie_drop_msg_tlp(pcie); ls_pcie_drop_msg_tlp(pcie);
iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
} }
static int ls_pcie_msi_host_init(struct pcie_port *pp, static int ls_pcie_msi_host_init(struct pcie_port *pp,
struct msi_controller *chip) struct msi_controller *chip)
{ {
struct device *dev = pp->dev;
struct device_node *np = dev->of_node;
struct device_node *msi_node; struct device_node *msi_node;
struct device_node *np = pp->dev->of_node;
/* /*
* The MSI domain is set by the generic of_msi_configure(). This * The MSI domain is set by the generic of_msi_configure(). This
...@@ -169,7 +170,7 @@ static int ls_pcie_msi_host_init(struct pcie_port *pp, ...@@ -169,7 +170,7 @@ static int ls_pcie_msi_host_init(struct pcie_port *pp,
*/ */
msi_node = of_parse_phandle(np, "msi-parent", 0); msi_node = of_parse_phandle(np, "msi-parent", 0);
if (!msi_node) { if (!msi_node) {
dev_err(pp->dev, "failed to find msi-parent\n"); dev_err(dev, "failed to find msi-parent\n");
return -EINVAL; return -EINVAL;
} }
...@@ -212,19 +213,15 @@ static const struct of_device_id ls_pcie_of_match[] = { ...@@ -212,19 +213,15 @@ static const struct of_device_id ls_pcie_of_match[] = {
{ }, { },
}; };
static int __init ls_add_pcie_port(struct pcie_port *pp, static int __init ls_add_pcie_port(struct ls_pcie *pcie)
struct platform_device *pdev)
{ {
struct pcie_port *pp = &pcie->pp;
struct device *dev = pp->dev;
int ret; int ret;
struct ls_pcie *pcie = to_ls_pcie(pp);
pp->dev = &pdev->dev;
pp->dbi_base = pcie->dbi;
pp->ops = pcie->drvdata->ops;
ret = dw_pcie_host_init(pp); ret = dw_pcie_host_init(pp);
if (ret) { if (ret) {
dev_err(pp->dev, "failed to initialize host\n"); dev_err(dev, "failed to initialize host\n");
return ret; return ret;
} }
...@@ -233,38 +230,42 @@ static int __init ls_add_pcie_port(struct pcie_port *pp, ...@@ -233,38 +230,42 @@ static int __init ls_add_pcie_port(struct pcie_port *pp,
static int __init ls_pcie_probe(struct platform_device *pdev) static int __init ls_pcie_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev;
const struct of_device_id *match; const struct of_device_id *match;
struct ls_pcie *pcie; struct ls_pcie *pcie;
struct pcie_port *pp;
struct resource *dbi_base; struct resource *dbi_base;
int ret; int ret;
match = of_match_device(ls_pcie_of_match, &pdev->dev); match = of_match_device(ls_pcie_of_match, dev);
if (!match) if (!match)
return -ENODEV; return -ENODEV;
pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
if (!pcie) if (!pcie)
return -ENOMEM; return -ENOMEM;
pp = &pcie->pp;
pp->dev = dev;
pp->ops = pcie->drvdata->ops;
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base);
if (IS_ERR(pcie->dbi)) { if (IS_ERR(pcie->pp.dbi_base)) {
dev_err(&pdev->dev, "missing *regs* space\n"); dev_err(dev, "missing *regs* space\n");
return PTR_ERR(pcie->dbi); return PTR_ERR(pcie->pp.dbi_base);
} }
pcie->drvdata = match->data; pcie->drvdata = match->data;
pcie->lut = pcie->dbi + pcie->drvdata->lut_offset; pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;
if (!ls_pcie_is_bridge(pcie)) if (!ls_pcie_is_bridge(pcie))
return -ENODEV; return -ENODEV;
ret = ls_add_pcie_port(&pcie->pp, pdev); ret = ls_add_pcie_port(pcie);
if (ret < 0) if (ret < 0)
return ret; return ret;
platform_set_drvdata(pdev, pcie);
return 0; return 0;
} }
......
...@@ -29,34 +29,33 @@ ...@@ -29,34 +29,33 @@
#include "pcie-designware.h" #include "pcie-designware.h"
struct armada8k_pcie { struct armada8k_pcie {
void __iomem *base; struct pcie_port pp; /* pp.dbi_base is DT ctrl */
struct clk *clk; struct clk *clk;
struct pcie_port pp;
}; };
#define PCIE_VENDOR_REGS_OFFSET 0x8000 #define PCIE_VENDOR_REGS_OFFSET 0x8000
#define PCIE_GLOBAL_CONTROL_REG 0x0 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
#define PCIE_APP_LTSSM_EN BIT(2) #define PCIE_APP_LTSSM_EN BIT(2)
#define PCIE_DEVICE_TYPE_SHIFT 4 #define PCIE_DEVICE_TYPE_SHIFT 4
#define PCIE_DEVICE_TYPE_MASK 0xF #define PCIE_DEVICE_TYPE_MASK 0xF
#define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */ #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
#define PCIE_GLOBAL_STATUS_REG 0x8 #define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8)
#define PCIE_GLB_STS_RDLH_LINK_UP BIT(1) #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1)
#define PCIE_GLB_STS_PHY_LINK_UP BIT(9) #define PCIE_GLB_STS_PHY_LINK_UP BIT(9)
#define PCIE_GLOBAL_INT_CAUSE1_REG 0x1C #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C)
#define PCIE_GLOBAL_INT_MASK1_REG 0x20 #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20)
#define PCIE_INT_A_ASSERT_MASK BIT(9) #define PCIE_INT_A_ASSERT_MASK BIT(9)
#define PCIE_INT_B_ASSERT_MASK BIT(10) #define PCIE_INT_B_ASSERT_MASK BIT(10)
#define PCIE_INT_C_ASSERT_MASK BIT(11) #define PCIE_INT_C_ASSERT_MASK BIT(11)
#define PCIE_INT_D_ASSERT_MASK BIT(12) #define PCIE_INT_D_ASSERT_MASK BIT(12)
#define PCIE_ARCACHE_TRC_REG 0x50 #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
#define PCIE_AWCACHE_TRC_REG 0x54 #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
#define PCIE_ARUSER_REG 0x5C #define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C)
#define PCIE_AWUSER_REG 0x60 #define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60)
/* /*
* AR/AW Cache defauls: Normal memory, Write-Back, Read / Write * AR/AW Cache defauls: Normal memory, Write-Back, Read / Write
* allocate * allocate
...@@ -72,11 +71,10 @@ struct armada8k_pcie { ...@@ -72,11 +71,10 @@ struct armada8k_pcie {
static int armada8k_pcie_link_up(struct pcie_port *pp) static int armada8k_pcie_link_up(struct pcie_port *pp)
{ {
struct armada8k_pcie *pcie = to_armada8k_pcie(pp);
u32 reg; u32 reg;
u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
reg = readl(pcie->base + PCIE_GLOBAL_STATUS_REG); reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_STATUS_REG);
if ((reg & mask) == mask) if ((reg & mask) == mask)
return 1; return 1;
...@@ -85,51 +83,50 @@ static int armada8k_pcie_link_up(struct pcie_port *pp) ...@@ -85,51 +83,50 @@ static int armada8k_pcie_link_up(struct pcie_port *pp)
return 0; return 0;
} }
static void armada8k_pcie_establish_link(struct pcie_port *pp) static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
{ {
struct armada8k_pcie *pcie = to_armada8k_pcie(pp); struct pcie_port *pp = &pcie->pp;
void __iomem *base = pcie->base;
u32 reg; u32 reg;
if (!dw_pcie_link_up(pp)) { if (!dw_pcie_link_up(pp)) {
/* Disable LTSSM state machine to enable configuration */ /* Disable LTSSM state machine to enable configuration */
reg = readl(base + PCIE_GLOBAL_CONTROL_REG); reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG);
reg &= ~(PCIE_APP_LTSSM_EN); reg &= ~(PCIE_APP_LTSSM_EN);
writel(reg, base + PCIE_GLOBAL_CONTROL_REG); dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg);
} }
/* Set the device to root complex mode */ /* Set the device to root complex mode */
reg = readl(base + PCIE_GLOBAL_CONTROL_REG); reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG);
reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
writel(reg, base + PCIE_GLOBAL_CONTROL_REG); dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg);
/* Set the PCIe master AxCache attributes */ /* Set the PCIe master AxCache attributes */
writel(ARCACHE_DEFAULT_VALUE, base + PCIE_ARCACHE_TRC_REG); dw_pcie_writel_rc(pp, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
writel(AWCACHE_DEFAULT_VALUE, base + PCIE_AWCACHE_TRC_REG); dw_pcie_writel_rc(pp, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
/* Set the PCIe master AxDomain attributes */ /* Set the PCIe master AxDomain attributes */
reg = readl(base + PCIE_ARUSER_REG); reg = dw_pcie_readl_rc(pp, PCIE_ARUSER_REG);
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
writel(reg, base + PCIE_ARUSER_REG); dw_pcie_writel_rc(pp, PCIE_ARUSER_REG, reg);
reg = readl(base + PCIE_AWUSER_REG); reg = dw_pcie_readl_rc(pp, PCIE_AWUSER_REG);
reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
writel(reg, base + PCIE_AWUSER_REG); dw_pcie_writel_rc(pp, PCIE_AWUSER_REG, reg);
/* Enable INT A-D interrupts */ /* Enable INT A-D interrupts */
reg = readl(base + PCIE_GLOBAL_INT_MASK1_REG); reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_INT_MASK1_REG);
reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
writel(reg, base + PCIE_GLOBAL_INT_MASK1_REG); dw_pcie_writel_rc(pp, PCIE_GLOBAL_INT_MASK1_REG, reg);
if (!dw_pcie_link_up(pp)) { if (!dw_pcie_link_up(pp)) {
/* Configuration done. Start LTSSM */ /* Configuration done. Start LTSSM */
reg = readl(base + PCIE_GLOBAL_CONTROL_REG); reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG);
reg |= PCIE_APP_LTSSM_EN; reg |= PCIE_APP_LTSSM_EN;
writel(reg, base + PCIE_GLOBAL_CONTROL_REG); dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg);
} }
/* Wait until the link becomes active again */ /* Wait until the link becomes active again */
...@@ -139,15 +136,16 @@ static void armada8k_pcie_establish_link(struct pcie_port *pp) ...@@ -139,15 +136,16 @@ static void armada8k_pcie_establish_link(struct pcie_port *pp)
static void armada8k_pcie_host_init(struct pcie_port *pp) static void armada8k_pcie_host_init(struct pcie_port *pp)
{ {
struct armada8k_pcie *pcie = to_armada8k_pcie(pp);
dw_pcie_setup_rc(pp); dw_pcie_setup_rc(pp);
armada8k_pcie_establish_link(pp); armada8k_pcie_establish_link(pcie);
} }
static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
{ {
struct pcie_port *pp = arg; struct armada8k_pcie *pcie = arg;
struct armada8k_pcie *pcie = to_armada8k_pcie(pp); struct pcie_port *pp = &pcie->pp;
void __iomem *base = pcie->base;
u32 val; u32 val;
/* /*
...@@ -155,8 +153,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) ...@@ -155,8 +153,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
* PCI device. However, they are also latched into the PCIe * PCI device. However, they are also latched into the PCIe
* controller, so we simply discard them. * controller, so we simply discard them.
*/ */
val = readl(base + PCIE_GLOBAL_INT_CAUSE1_REG); val = dw_pcie_readl_rc(pp, PCIE_GLOBAL_INT_CAUSE1_REG);
writel(val, base + PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_rc(pp, PCIE_GLOBAL_INT_CAUSE1_REG, val);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
...@@ -166,9 +164,10 @@ static struct pcie_host_ops armada8k_pcie_host_ops = { ...@@ -166,9 +164,10 @@ static struct pcie_host_ops armada8k_pcie_host_ops = {
.host_init = armada8k_pcie_host_init, .host_init = armada8k_pcie_host_init,
}; };
static int armada8k_add_pcie_port(struct pcie_port *pp, static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
struct platform_device *pdev) struct platform_device *pdev)
{ {
struct pcie_port *pp = &pcie->pp;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
int ret; int ret;
...@@ -182,7 +181,7 @@ static int armada8k_add_pcie_port(struct pcie_port *pp, ...@@ -182,7 +181,7 @@ static int armada8k_add_pcie_port(struct pcie_port *pp,
} }
ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler, ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler,
IRQF_SHARED, "armada8k-pcie", pp); IRQF_SHARED, "armada8k-pcie", pcie);
if (ret) { if (ret) {
dev_err(dev, "failed to request irq %d\n", pp->irq); dev_err(dev, "failed to request irq %d\n", pp->irq);
return ret; return ret;
...@@ -217,7 +216,6 @@ static int armada8k_pcie_probe(struct platform_device *pdev) ...@@ -217,7 +216,6 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
pp = &pcie->pp; pp = &pcie->pp;
pp->dev = dev; pp->dev = dev;
platform_set_drvdata(pdev, pcie);
/* Get the dw-pcie unit configuration/control registers base. */ /* Get the dw-pcie unit configuration/control registers base. */
base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
...@@ -228,9 +226,7 @@ static int armada8k_pcie_probe(struct platform_device *pdev) ...@@ -228,9 +226,7 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
goto fail; goto fail;
} }
pcie->base = pp->dbi_base + PCIE_VENDOR_REGS_OFFSET; ret = armada8k_add_pcie_port(pcie, pdev);
ret = armada8k_add_pcie_port(pp, pdev);
if (ret) if (ret)
goto fail; goto fail;
......
...@@ -27,9 +27,9 @@ ...@@ -27,9 +27,9 @@
#define to_artpec6_pcie(x) container_of(x, struct artpec6_pcie, pp) #define to_artpec6_pcie(x) container_of(x, struct artpec6_pcie, pp)
struct artpec6_pcie { struct artpec6_pcie {
struct pcie_port pp; struct pcie_port pp; /* pp.dbi_base is DT dbi */
struct regmap *regmap; struct regmap *regmap; /* DT axis,syscon-pcie */
void __iomem *phy_base; void __iomem *phy_base; /* DT phy */
}; };
/* PCIe Port Logic registers (memory-mapped) */ /* PCIe Port Logic registers (memory-mapped) */
...@@ -65,18 +65,31 @@ struct artpec6_pcie { ...@@ -65,18 +65,31 @@ struct artpec6_pcie {
#define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff #define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff
static int artpec6_pcie_establish_link(struct pcie_port *pp) static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
{ {
struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pp); u32 val;
regmap_read(artpec6_pcie->regmap, offset, &val);
return val;
}
static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
{
regmap_write(artpec6_pcie->regmap, offset, val);
}
static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
{
struct pcie_port *pp = &artpec6_pcie->pp;
u32 val; u32 val;
unsigned int retries; unsigned int retries;
/* Hold DW core in reset */ /* Hold DW core in reset */
regmap_read(artpec6_pcie->regmap, PCIECFG, &val); val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
val |= PCIECFG_CORE_RESET_REQ; val |= PCIECFG_CORE_RESET_REQ;
regmap_write(artpec6_pcie->regmap, PCIECFG, val); artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
regmap_read(artpec6_pcie->regmap, PCIECFG, &val); val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */ val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
PCIECFG_MODE_TX_DRV_EN | PCIECFG_MODE_TX_DRV_EN |
PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */ PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */
...@@ -84,27 +97,27 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp) ...@@ -84,27 +97,27 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp)
val |= PCIECFG_REFCLK_ENABLE; val |= PCIECFG_REFCLK_ENABLE;
val &= ~PCIECFG_DBG_OEN; val &= ~PCIECFG_DBG_OEN;
val &= ~PCIECFG_CLKREQ_B; val &= ~PCIECFG_CLKREQ_B;
regmap_write(artpec6_pcie->regmap, PCIECFG, val); artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
usleep_range(5000, 6000); usleep_range(5000, 6000);
regmap_read(artpec6_pcie->regmap, NOCCFG, &val); val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
val |= NOCCFG_ENABLE_CLK_PCIE; val |= NOCCFG_ENABLE_CLK_PCIE;
regmap_write(artpec6_pcie->regmap, NOCCFG, val); artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
usleep_range(20, 30); usleep_range(20, 30);
regmap_read(artpec6_pcie->regmap, PCIECFG, &val); val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE; val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
regmap_write(artpec6_pcie->regmap, PCIECFG, val); artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
usleep_range(6000, 7000); usleep_range(6000, 7000);
regmap_read(artpec6_pcie->regmap, NOCCFG, &val); val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
val &= ~NOCCFG_POWER_PCIE_IDLEREQ; val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
regmap_write(artpec6_pcie->regmap, NOCCFG, val); artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
retries = 50; retries = 50;
do { do {
usleep_range(1000, 2000); usleep_range(1000, 2000);
regmap_read(artpec6_pcie->regmap, NOCCFG, &val); val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
retries--; retries--;
} while (retries && } while (retries &&
(val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE))); (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
...@@ -117,16 +130,16 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp) ...@@ -117,16 +130,16 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp)
} while (retries && !(val & PHY_COSPLLLOCK)); } while (retries && !(val & PHY_COSPLLLOCK));
/* Take DW core out of reset */ /* Take DW core out of reset */
regmap_read(artpec6_pcie->regmap, PCIECFG, &val); val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
val &= ~PCIECFG_CORE_RESET_REQ; val &= ~PCIECFG_CORE_RESET_REQ;
regmap_write(artpec6_pcie->regmap, PCIECFG, val); artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
usleep_range(100, 200); usleep_range(100, 200);
/* /*
* Enable writing to config regs. This is required as the Synopsys * Enable writing to config regs. This is required as the Synopsys
* driver changes the class code. That register needs DBI write enable. * driver changes the class code. That register needs DBI write enable.
*/ */
writel(DBI_RO_WR_EN, pp->dbi_base + MISC_CONTROL_1_OFF); dw_pcie_writel_rc(pp, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR; pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR; pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
...@@ -137,78 +150,69 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp) ...@@ -137,78 +150,69 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp)
dw_pcie_setup_rc(pp); dw_pcie_setup_rc(pp);
/* assert LTSSM enable */ /* assert LTSSM enable */
regmap_read(artpec6_pcie->regmap, PCIECFG, &val); val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
val |= PCIECFG_LTSSM_ENABLE; val |= PCIECFG_LTSSM_ENABLE;
regmap_write(artpec6_pcie->regmap, PCIECFG, val); artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
/* check if the link is up or not */ /* check if the link is up or not */
if (!dw_pcie_wait_for_link(pp)) if (!dw_pcie_wait_for_link(pp))
return 0; return 0;
dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0),
readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1));
return -ETIMEDOUT; return -ETIMEDOUT;
} }
static void artpec6_pcie_enable_interrupts(struct pcie_port *pp) static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
{ {
struct pcie_port *pp = &artpec6_pcie->pp;
if (IS_ENABLED(CONFIG_PCI_MSI)) if (IS_ENABLED(CONFIG_PCI_MSI))
dw_pcie_msi_init(pp); dw_pcie_msi_init(pp);
} }
static void artpec6_pcie_host_init(struct pcie_port *pp) static void artpec6_pcie_host_init(struct pcie_port *pp)
{ {
artpec6_pcie_establish_link(pp); struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pp);
artpec6_pcie_enable_interrupts(pp);
}
static int artpec6_pcie_link_up(struct pcie_port *pp)
{
u32 rc;
/*
* Get status from Synopsys IP
* link is debug bit 36, debug register 1 starts at bit 32
*/
rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
if (rc)
return 1;
return 0; artpec6_pcie_establish_link(artpec6_pcie);
artpec6_pcie_enable_interrupts(artpec6_pcie);
} }
static struct pcie_host_ops artpec6_pcie_host_ops = { static struct pcie_host_ops artpec6_pcie_host_ops = {
.link_up = artpec6_pcie_link_up,
.host_init = artpec6_pcie_host_init, .host_init = artpec6_pcie_host_init,
}; };
static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg) static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
{ {
struct pcie_port *pp = arg; struct artpec6_pcie *artpec6_pcie = arg;
struct pcie_port *pp = &artpec6_pcie->pp;
return dw_handle_msi_irq(pp); return dw_handle_msi_irq(pp);
} }
static int artpec6_add_pcie_port(struct pcie_port *pp, static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
struct platform_device *pdev) struct platform_device *pdev)
{ {
struct pcie_port *pp = &artpec6_pcie->pp;
struct device *dev = pp->dev;
int ret; int ret;
if (IS_ENABLED(CONFIG_PCI_MSI)) { if (IS_ENABLED(CONFIG_PCI_MSI)) {
pp->msi_irq = platform_get_irq_byname(pdev, "msi"); pp->msi_irq = platform_get_irq_byname(pdev, "msi");
if (pp->msi_irq <= 0) { if (pp->msi_irq <= 0) {
dev_err(&pdev->dev, "failed to get MSI irq\n"); dev_err(dev, "failed to get MSI irq\n");
return -ENODEV; return -ENODEV;
} }
ret = devm_request_irq(&pdev->dev, pp->msi_irq, ret = devm_request_irq(dev, pp->msi_irq,
artpec6_pcie_msi_handler, artpec6_pcie_msi_handler,
IRQF_SHARED | IRQF_NO_THREAD, IRQF_SHARED | IRQF_NO_THREAD,
"artpec6-pcie-msi", pp); "artpec6-pcie-msi", artpec6_pcie);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to request MSI irq\n"); dev_err(dev, "failed to request MSI irq\n");
return ret; return ret;
} }
} }
...@@ -218,7 +222,7 @@ static int artpec6_add_pcie_port(struct pcie_port *pp, ...@@ -218,7 +222,7 @@ static int artpec6_add_pcie_port(struct pcie_port *pp,
ret = dw_pcie_host_init(pp); ret = dw_pcie_host_init(pp);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to initialize host\n"); dev_err(dev, "failed to initialize host\n");
return ret; return ret;
} }
...@@ -227,41 +231,40 @@ static int artpec6_add_pcie_port(struct pcie_port *pp, ...@@ -227,41 +231,40 @@ static int artpec6_add_pcie_port(struct pcie_port *pp,
static int artpec6_pcie_probe(struct platform_device *pdev) static int artpec6_pcie_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev;
struct artpec6_pcie *artpec6_pcie; struct artpec6_pcie *artpec6_pcie;
struct pcie_port *pp; struct pcie_port *pp;
struct resource *dbi_base; struct resource *dbi_base;
struct resource *phy_base; struct resource *phy_base;
int ret; int ret;
artpec6_pcie = devm_kzalloc(&pdev->dev, sizeof(*artpec6_pcie), artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
GFP_KERNEL);
if (!artpec6_pcie) if (!artpec6_pcie)
return -ENOMEM; return -ENOMEM;
pp = &artpec6_pcie->pp; pp = &artpec6_pcie->pp;
pp->dev = &pdev->dev; pp->dev = dev;
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
if (IS_ERR(pp->dbi_base)) if (IS_ERR(pp->dbi_base))
return PTR_ERR(pp->dbi_base); return PTR_ERR(pp->dbi_base);
phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
artpec6_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base); artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
if (IS_ERR(artpec6_pcie->phy_base)) if (IS_ERR(artpec6_pcie->phy_base))
return PTR_ERR(artpec6_pcie->phy_base); return PTR_ERR(artpec6_pcie->phy_base);
artpec6_pcie->regmap = artpec6_pcie->regmap =
syscon_regmap_lookup_by_phandle(pdev->dev.of_node, syscon_regmap_lookup_by_phandle(dev->of_node,
"axis,syscon-pcie"); "axis,syscon-pcie");
if (IS_ERR(artpec6_pcie->regmap)) if (IS_ERR(artpec6_pcie->regmap))
return PTR_ERR(artpec6_pcie->regmap); return PTR_ERR(artpec6_pcie->regmap);
ret = artpec6_add_pcie_port(pp, pdev); ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
if (ret < 0) if (ret < 0)
return ret; return ret;
platform_set_drvdata(pdev, artpec6_pcie);
return 0; return 0;
} }
......
...@@ -22,51 +22,38 @@ ...@@ -22,51 +22,38 @@
#include "pcie-designware.h" #include "pcie-designware.h"
#define PCIE_LTSSM_LINKUP_STATE 0x11 #define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818
#define PCIE_LTSSM_STATE_MASK 0x3F #define PCIE_HIP06_CTRL_OFF 0x1000
#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818 #define PCIE_SYS_STATE4 (PCIE_HIP06_CTRL_OFF + 0x31c)
#define PCIE_SYS_STATE4 0x31c #define PCIE_LTSSM_LINKUP_STATE 0x11
#define PCIE_HIP06_CTRL_OFF 0x1000 #define PCIE_LTSSM_STATE_MASK 0x3F
#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp) #define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp)
struct hisi_pcie; struct hisi_pcie;
struct pcie_soc_ops { struct pcie_soc_ops {
int (*hisi_pcie_link_up)(struct hisi_pcie *pcie); int (*hisi_pcie_link_up)(struct hisi_pcie *hisi_pcie);
}; };
struct hisi_pcie { struct hisi_pcie {
struct pcie_port pp; /* pp.dbi_base is DT rc_dbi */
struct regmap *subctrl; struct regmap *subctrl;
void __iomem *reg_base;
u32 port_id; u32 port_id;
struct pcie_port pp;
struct pcie_soc_ops *soc_ops; struct pcie_soc_ops *soc_ops;
}; };
static inline void hisi_pcie_apb_writel(struct hisi_pcie *pcie,
u32 val, u32 reg)
{
writel(val, pcie->reg_base + reg);
}
static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *pcie, u32 reg)
{
return readl(pcie->reg_base + reg);
}
/* HipXX PCIe host only supports 32-bit config access */ /* HipXX PCIe host only supports 32-bit config access */
static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size, static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
u32 *val) u32 *val)
{ {
u32 reg; u32 reg;
u32 reg_val; u32 reg_val;
struct hisi_pcie *pcie = to_hisi_pcie(pp);
void *walker = &reg_val; void *walker = &reg_val;
walker += (where & 0x3); walker += (where & 0x3);
reg = where & ~0x3; reg = where & ~0x3;
reg_val = hisi_pcie_apb_readl(pcie, reg); reg_val = dw_pcie_readl_rc(pp, reg);
if (size == 1) if (size == 1)
*val = *(u8 __force *) walker; *val = *(u8 __force *) walker;
...@@ -86,21 +73,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size, ...@@ -86,21 +73,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
{ {
u32 reg_val; u32 reg_val;
u32 reg; u32 reg;
struct hisi_pcie *pcie = to_hisi_pcie(pp);
void *walker = &reg_val; void *walker = &reg_val;
walker += (where & 0x3); walker += (where & 0x3);
reg = where & ~0x3; reg = where & ~0x3;
if (size == 4) if (size == 4)
hisi_pcie_apb_writel(pcie, val, reg); dw_pcie_writel_rc(pp, reg, val);
else if (size == 2) { else if (size == 2) {
reg_val = hisi_pcie_apb_readl(pcie, reg); reg_val = dw_pcie_readl_rc(pp, reg);
*(u16 __force *) walker = val; *(u16 __force *) walker = val;
hisi_pcie_apb_writel(pcie, reg_val, reg); dw_pcie_writel_rc(pp, reg, reg_val);
} else if (size == 1) { } else if (size == 1) {
reg_val = hisi_pcie_apb_readl(pcie, reg); reg_val = dw_pcie_readl_rc(pp, reg);
*(u8 __force *) walker = val; *(u8 __force *) walker = val;
hisi_pcie_apb_writel(pcie, reg_val, reg); dw_pcie_writel_rc(pp, reg, reg_val);
} else } else
return PCIBIOS_BAD_REGISTER_NUMBER; return PCIBIOS_BAD_REGISTER_NUMBER;
...@@ -119,10 +105,10 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie) ...@@ -119,10 +105,10 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie) static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
{ {
struct pcie_port *pp = &hisi_pcie->pp;
u32 val; u32 val;
val = hisi_pcie_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF + val = dw_pcie_readl_rc(pp, PCIE_SYS_STATE4);
PCIE_SYS_STATE4);
return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
} }
...@@ -140,19 +126,20 @@ static struct pcie_host_ops hisi_pcie_host_ops = { ...@@ -140,19 +126,20 @@ static struct pcie_host_ops hisi_pcie_host_ops = {
.link_up = hisi_pcie_link_up, .link_up = hisi_pcie_link_up,
}; };
static int hisi_add_pcie_port(struct pcie_port *pp, static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
struct platform_device *pdev) struct platform_device *pdev)
{ {
struct pcie_port *pp = &hisi_pcie->pp;
struct device *dev = pp->dev;
int ret; int ret;
u32 port_id; u32 port_id;
struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
if (of_property_read_u32(pdev->dev.of_node, "port-id", &port_id)) { if (of_property_read_u32(dev->of_node, "port-id", &port_id)) {
dev_err(&pdev->dev, "failed to read port-id\n"); dev_err(dev, "failed to read port-id\n");
return -EINVAL; return -EINVAL;
} }
if (port_id > 3) { if (port_id > 3) {
dev_err(&pdev->dev, "Invalid port-id: %d\n", port_id); dev_err(dev, "Invalid port-id: %d\n", port_id);
return -EINVAL; return -EINVAL;
} }
hisi_pcie->port_id = port_id; hisi_pcie->port_id = port_id;
...@@ -161,7 +148,7 @@ static int hisi_add_pcie_port(struct pcie_port *pp, ...@@ -161,7 +148,7 @@ static int hisi_add_pcie_port(struct pcie_port *pp,
ret = dw_pcie_host_init(pp); ret = dw_pcie_host_init(pp);
if (ret) { if (ret) {
dev_err(&pdev->dev, "failed to initialize host\n"); dev_err(dev, "failed to initialize host\n");
return ret; return ret;
} }
...@@ -170,6 +157,7 @@ static int hisi_add_pcie_port(struct pcie_port *pp, ...@@ -170,6 +157,7 @@ static int hisi_add_pcie_port(struct pcie_port *pp,
static int hisi_pcie_probe(struct platform_device *pdev) static int hisi_pcie_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev;
struct hisi_pcie *hisi_pcie; struct hisi_pcie *hisi_pcie;
struct pcie_port *pp; struct pcie_port *pp;
const struct of_device_id *match; const struct of_device_id *match;
...@@ -177,40 +165,36 @@ static int hisi_pcie_probe(struct platform_device *pdev) ...@@ -177,40 +165,36 @@ static int hisi_pcie_probe(struct platform_device *pdev)
struct device_driver *driver; struct device_driver *driver;
int ret; int ret;
hisi_pcie = devm_kzalloc(&pdev->dev, sizeof(*hisi_pcie), GFP_KERNEL); hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL);
if (!hisi_pcie) if (!hisi_pcie)
return -ENOMEM; return -ENOMEM;
pp = &hisi_pcie->pp; pp = &hisi_pcie->pp;
pp->dev = &pdev->dev; pp->dev = dev;
driver = (pdev->dev).driver; driver = dev->driver;
match = of_match_device(driver->of_match_table, &pdev->dev); match = of_match_device(driver->of_match_table, dev);
hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data; hisi_pcie->soc_ops = (struct pcie_soc_ops *) match->data;
hisi_pcie->subctrl = hisi_pcie->subctrl =
syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl"); syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl");
if (IS_ERR(hisi_pcie->subctrl)) { if (IS_ERR(hisi_pcie->subctrl)) {
dev_err(pp->dev, "cannot get subctrl base\n"); dev_err(dev, "cannot get subctrl base\n");
return PTR_ERR(hisi_pcie->subctrl); return PTR_ERR(hisi_pcie->subctrl);
} }
reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi"); reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
hisi_pcie->reg_base = devm_ioremap_resource(&pdev->dev, reg); pp->dbi_base = devm_ioremap_resource(dev, reg);
if (IS_ERR(hisi_pcie->reg_base)) { if (IS_ERR(pp->dbi_base)) {
dev_err(pp->dev, "cannot get rc_dbi base\n"); dev_err(dev, "cannot get rc_dbi base\n");
return PTR_ERR(hisi_pcie->reg_base); return PTR_ERR(pp->dbi_base);
} }
hisi_pcie->pp.dbi_base = hisi_pcie->reg_base; ret = hisi_add_pcie_port(hisi_pcie, pdev);
ret = hisi_add_pcie_port(pp, pdev);
if (ret) if (ret)
return ret; return ret;
platform_set_drvdata(pdev, hisi_pcie); dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
dev_warn(pp->dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
return 0; return 0;
} }
......
...@@ -86,12 +86,10 @@ struct qcom_pcie_ops { ...@@ -86,12 +86,10 @@ struct qcom_pcie_ops {
}; };
struct qcom_pcie { struct qcom_pcie {
struct pcie_port pp; struct pcie_port pp; /* pp.dbi_base is DT dbi */
struct device *dev; void __iomem *parf; /* DT parf */
void __iomem *elbi; /* DT elbi */
union qcom_pcie_resources res; union qcom_pcie_resources res;
void __iomem *parf;
void __iomem *dbi;
void __iomem *elbi;
struct phy *phy; struct phy *phy;
struct gpio_desc *reset; struct gpio_desc *reset;
struct qcom_pcie_ops *ops; struct qcom_pcie_ops *ops;
...@@ -136,7 +134,7 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie) ...@@ -136,7 +134,7 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
{ {
struct qcom_pcie_resources_v0 *res = &pcie->res.v0; struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
struct device *dev = pcie->dev; struct device *dev = pcie->pp.dev;
res->vdda = devm_regulator_get(dev, "vdda"); res->vdda = devm_regulator_get(dev, "vdda");
if (IS_ERR(res->vdda)) if (IS_ERR(res->vdda))
...@@ -188,7 +186,7 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) ...@@ -188,7 +186,7 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie) static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
{ {
struct qcom_pcie_resources_v1 *res = &pcie->res.v1; struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
struct device *dev = pcie->dev; struct device *dev = pcie->pp.dev;
res->vdda = devm_regulator_get(dev, "vdda"); res->vdda = devm_regulator_get(dev, "vdda");
if (IS_ERR(res->vdda)) if (IS_ERR(res->vdda))
...@@ -237,7 +235,7 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie) ...@@ -237,7 +235,7 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
static int qcom_pcie_init_v0(struct qcom_pcie *pcie) static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
{ {
struct qcom_pcie_resources_v0 *res = &pcie->res.v0; struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
struct device *dev = pcie->dev; struct device *dev = pcie->pp.dev;
u32 val; u32 val;
int ret; int ret;
...@@ -359,7 +357,7 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie) ...@@ -359,7 +357,7 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
static int qcom_pcie_init_v1(struct qcom_pcie *pcie) static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
{ {
struct qcom_pcie_resources_v1 *res = &pcie->res.v1; struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
struct device *dev = pcie->dev; struct device *dev = pcie->pp.dev;
int ret; int ret;
ret = reset_control_deassert(res->core); ret = reset_control_deassert(res->core);
...@@ -426,7 +424,7 @@ static int qcom_pcie_init_v1(struct qcom_pcie *pcie) ...@@ -426,7 +424,7 @@ static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
static int qcom_pcie_link_up(struct pcie_port *pp) static int qcom_pcie_link_up(struct pcie_port *pp)
{ {
struct qcom_pcie *pcie = to_qcom_pcie(pp); struct qcom_pcie *pcie = to_qcom_pcie(pp);
u16 val = readw(pcie->dbi + PCIE20_CAP + PCI_EXP_LNKSTA); u16 val = readw(pcie->pp.dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
return !!(val & PCI_EXP_LNKSTA_DLLLA); return !!(val & PCI_EXP_LNKSTA_DLLLA);
} }
...@@ -509,8 +507,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) ...@@ -509,8 +507,8 @@ static int qcom_pcie_probe(struct platform_device *pdev)
if (!pcie) if (!pcie)
return -ENOMEM; return -ENOMEM;
pp = &pcie->pp;
pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev); pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
pcie->dev = dev;
pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW); pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
if (IS_ERR(pcie->reset)) if (IS_ERR(pcie->reset))
...@@ -522,9 +520,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) ...@@ -522,9 +520,9 @@ static int qcom_pcie_probe(struct platform_device *pdev)
return PTR_ERR(pcie->parf); return PTR_ERR(pcie->parf);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
pcie->dbi = devm_ioremap_resource(dev, res); pp->dbi_base = devm_ioremap_resource(dev, res);
if (IS_ERR(pcie->dbi)) if (IS_ERR(pp->dbi_base))
return PTR_ERR(pcie->dbi); return PTR_ERR(pp->dbi_base);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
pcie->elbi = devm_ioremap_resource(dev, res); pcie->elbi = devm_ioremap_resource(dev, res);
...@@ -539,9 +537,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) ...@@ -539,9 +537,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
if (ret) if (ret)
return ret; return ret;
pp = &pcie->pp;
pp->dev = dev; pp->dev = dev;
pp->dbi_base = pcie->dbi;
pp->root_bus_nr = -1; pp->root_bus_nr = -1;
pp->ops = &qcom_pcie_dw_ops; pp->ops = &qcom_pcie_dw_ops;
...@@ -569,8 +565,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) ...@@ -569,8 +565,6 @@ static int qcom_pcie_probe(struct platform_device *pdev)
return ret; return ret;
} }
platform_set_drvdata(pdev, pcie);
return 0; return 0;
} }
......
...@@ -25,10 +25,10 @@ ...@@ -25,10 +25,10 @@
#include "pcie-designware.h" #include "pcie-designware.h"
struct spear13xx_pcie { struct spear13xx_pcie {
struct pcie_port pp; /* DT dbi is pp.dbi_base */
void __iomem *app_base; void __iomem *app_base;
struct phy *phy; struct phy *phy;
struct clk *clk; struct clk *clk;
struct pcie_port pp;
bool is_gen1; bool is_gen1;
}; };
...@@ -57,96 +57,26 @@ struct pcie_app_reg { ...@@ -57,96 +57,26 @@ struct pcie_app_reg {
}; };
/* CR0 ID */ /* CR0 ID */
#define RX_LANE_FLIP_EN_ID 0
#define TX_LANE_FLIP_EN_ID 1
#define SYS_AUX_PWR_DET_ID 2
#define APP_LTSSM_ENABLE_ID 3 #define APP_LTSSM_ENABLE_ID 3
#define SYS_ATTEN_BUTTON_PRESSED_ID 4
#define SYS_MRL_SENSOR_STATE_ID 5
#define SYS_PWR_FAULT_DET_ID 6
#define SYS_MRL_SENSOR_CHGED_ID 7
#define SYS_PRE_DET_CHGED_ID 8
#define SYS_CMD_CPLED_INT_ID 9
#define APP_INIT_RST_0_ID 11
#define APP_REQ_ENTR_L1_ID 12
#define APP_READY_ENTR_L23_ID 13
#define APP_REQ_EXIT_L1_ID 14
#define DEVICE_TYPE_EP (0 << 25)
#define DEVICE_TYPE_LEP (1 << 25)
#define DEVICE_TYPE_RC (4 << 25) #define DEVICE_TYPE_RC (4 << 25)
#define SYS_INT_ID 29
#define MISCTRL_EN_ID 30 #define MISCTRL_EN_ID 30
#define REG_TRANSLATION_ENABLE 31 #define REG_TRANSLATION_ENABLE 31
/* CR1 ID */
#define APPS_PM_XMT_TURNOFF_ID 2
#define APPS_PM_XMT_PME_ID 5
/* CR3 ID */ /* CR3 ID */
#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
#define XMLH_LTSSM_STATE_L0 0x11
#define XMLH_LTSSM_STATE_L0S 0x12
#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
#define XMLH_LTSSM_STATE_L1_IDLE 0x14
#define XMLH_LTSSM_STATE_L2_IDLE 0x15
#define XMLH_LTSSM_STATE_L2_WAKE 0x16
#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
#define XMLH_LTSSM_STATE_DISABLED 0x19
#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
#define XMLH_LTSSM_STATE_MASK 0x3F
#define XMLH_LINK_UP (1 << 6) #define XMLH_LINK_UP (1 << 6)
/* CR4 ID */
#define CFG_MSI_EN_ID 18
/* CR6 */ /* CR6 */
#define INTA_CTRL_INT (1 << 7)
#define INTB_CTRL_INT (1 << 8)
#define INTC_CTRL_INT (1 << 9)
#define INTD_CTRL_INT (1 << 10)
#define MSI_CTRL_INT (1 << 26) #define MSI_CTRL_INT (1 << 26)
/* CR19 ID */
#define VEN_MSI_REQ_ID 11
#define VEN_MSI_FUN_NUM_ID 8
#define VEN_MSI_TC_ID 5
#define VEN_MSI_VECTOR_ID 0
#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
#define EXP_CAP_ID_OFFSET 0x70 #define EXP_CAP_ID_OFFSET 0x70
#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp) #define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
static int spear13xx_pcie_establish_link(struct pcie_port *pp) static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
{ {
u32 val; struct pcie_port *pp = &spear13xx_pcie->pp;
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
u32 val;
u32 exp_cap_off = EXP_CAP_ID_OFFSET; u32 exp_cap_off = EXP_CAP_ID_OFFSET;
if (dw_pcie_link_up(pp)) { if (dw_pcie_link_up(pp)) {
...@@ -203,9 +133,9 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp) ...@@ -203,9 +133,9 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp)
static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
{ {
struct pcie_port *pp = arg; struct spear13xx_pcie *spear13xx_pcie = arg;
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
struct pcie_port *pp = &spear13xx_pcie->pp;
unsigned int status; unsigned int status;
status = readl(&app_reg->int_sts); status = readl(&app_reg->int_sts);
...@@ -220,9 +150,9 @@ static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) ...@@ -220,9 +150,9 @@ static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp) static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
{ {
struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); struct pcie_port *pp = &spear13xx_pcie->pp;
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
/* Enable MSI interrupt */ /* Enable MSI interrupt */
...@@ -246,8 +176,10 @@ static int spear13xx_pcie_link_up(struct pcie_port *pp) ...@@ -246,8 +176,10 @@ static int spear13xx_pcie_link_up(struct pcie_port *pp)
static void spear13xx_pcie_host_init(struct pcie_port *pp) static void spear13xx_pcie_host_init(struct pcie_port *pp)
{ {
spear13xx_pcie_establish_link(pp); struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
spear13xx_pcie_enable_interrupts(pp);
spear13xx_pcie_establish_link(spear13xx_pcie);
spear13xx_pcie_enable_interrupts(spear13xx_pcie);
} }
static struct pcie_host_ops spear13xx_pcie_host_ops = { static struct pcie_host_ops spear13xx_pcie_host_ops = {
...@@ -255,10 +187,11 @@ static struct pcie_host_ops spear13xx_pcie_host_ops = { ...@@ -255,10 +187,11 @@ static struct pcie_host_ops spear13xx_pcie_host_ops = {
.host_init = spear13xx_pcie_host_init, .host_init = spear13xx_pcie_host_init,
}; };
static int spear13xx_add_pcie_port(struct pcie_port *pp, static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
struct platform_device *pdev) struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev; struct pcie_port *pp = &spear13xx_pcie->pp;
struct device *dev = pp->dev;
int ret; int ret;
pp->irq = platform_get_irq(pdev, 0); pp->irq = platform_get_irq(pdev, 0);
...@@ -268,7 +201,7 @@ static int spear13xx_add_pcie_port(struct pcie_port *pp, ...@@ -268,7 +201,7 @@ static int spear13xx_add_pcie_port(struct pcie_port *pp,
} }
ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler, ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
IRQF_SHARED | IRQF_NO_THREAD, IRQF_SHARED | IRQF_NO_THREAD,
"spear1340-pcie", pp); "spear1340-pcie", spear13xx_pcie);
if (ret) { if (ret) {
dev_err(dev, "failed to request irq %d\n", pp->irq); dev_err(dev, "failed to request irq %d\n", pp->irq);
return ret; return ret;
...@@ -288,10 +221,10 @@ static int spear13xx_add_pcie_port(struct pcie_port *pp, ...@@ -288,10 +221,10 @@ static int spear13xx_add_pcie_port(struct pcie_port *pp,
static int spear13xx_pcie_probe(struct platform_device *pdev) static int spear13xx_pcie_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev;
struct spear13xx_pcie *spear13xx_pcie; struct spear13xx_pcie *spear13xx_pcie;
struct pcie_port *pp; struct pcie_port *pp;
struct device *dev = &pdev->dev; struct device_node *np = dev->of_node;
struct device_node *np = pdev->dev.of_node;
struct resource *dbi_base; struct resource *dbi_base;
int ret; int ret;
...@@ -323,7 +256,6 @@ static int spear13xx_pcie_probe(struct platform_device *pdev) ...@@ -323,7 +256,6 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
} }
pp = &spear13xx_pcie->pp; pp = &spear13xx_pcie->pp;
pp->dev = dev; pp->dev = dev;
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
...@@ -338,7 +270,7 @@ static int spear13xx_pcie_probe(struct platform_device *pdev) ...@@ -338,7 +270,7 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
if (of_property_read_bool(np, "st,pcie-is-gen1")) if (of_property_read_bool(np, "st,pcie-is-gen1"))
spear13xx_pcie->is_gen1 = true; spear13xx_pcie->is_gen1 = true;
ret = spear13xx_add_pcie_port(pp, pdev); ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
if (ret < 0) if (ret < 0)
goto fail_clk; goto fail_clk;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment