Commit 218a3f96 authored by Oder Chiou's avatar Oder Chiou Committed by Mark Brown

ASoC: rt5640: Rename the function of clock checking

In order to identify clearly, the patch renames the function
"check_sysclk1_source" to "is_sys_clk_from_pll".
Signed-off-by: default avatarOder Chiou <oder_chiou@realtek.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent 2f2a714c
......@@ -480,7 +480,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
return idx;
}
static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
unsigned int val;
......@@ -1273,22 +1273,22 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
{"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
{"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
{"Stereo ADC MIXL", NULL, "Stereo Filter"},
{"Stereo Filter", NULL, "PLL1", check_sysclk1_source},
{"Stereo Filter", NULL, "PLL1", is_sys_clk_from_pll},
{"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
{"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
{"Stereo ADC MIXR", NULL, "Stereo Filter"},
{"Stereo Filter", NULL, "PLL1", check_sysclk1_source},
{"Stereo Filter", NULL, "PLL1", is_sys_clk_from_pll},
{"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
{"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
{"Mono ADC MIXL", NULL, "Mono Left Filter"},
{"Mono Left Filter", NULL, "PLL1", check_sysclk1_source},
{"Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll},
{"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
{"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
{"Mono ADC MIXR", NULL, "Mono Right Filter"},
{"Mono Right Filter", NULL, "PLL1", check_sysclk1_source},
{"Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll},
{"IF2 ADC L", NULL, "Mono ADC MIXL"},
{"IF2 ADC R", NULL, "Mono ADC MIXR"},
......@@ -1377,13 +1377,13 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
{"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
{"DAC L1", NULL, "Stereo DAC MIXL"},
{"DAC L1", NULL, "PLL1", check_sysclk1_source},
{"DAC L1", NULL, "PLL1", is_sys_clk_from_pll},
{"DAC R1", NULL, "Stereo DAC MIXR"},
{"DAC R1", NULL, "PLL1", check_sysclk1_source},
{"DAC R1", NULL, "PLL1", is_sys_clk_from_pll},
{"DAC L2", NULL, "Mono DAC MIXL"},
{"DAC L2", NULL, "PLL1", check_sysclk1_source},
{"DAC L2", NULL, "PLL1", is_sys_clk_from_pll},
{"DAC R2", NULL, "Mono DAC MIXR"},
{"DAC R2", NULL, "PLL1", check_sysclk1_source},
{"DAC R2", NULL, "PLL1", is_sys_clk_from_pll},
{"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
{"SPK MIXL", "INL Switch", "INL VOL"},
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment