Commit 21b30c00 authored by Florian Fainelli's avatar Florian Fainelli Committed by Ralf Baechle

MIPS: BMIPS: Add Whirlwind (BMIPS5200) initialization code

Import bmips_5xxx_init.S from the stblinux-3.3 tree, and to make sure that this
would work nicely with a BMIPS multiplatform kernel (with BMIPS330, BMIPS43XX
and BMIPS5000 enabled), update soft_reset to check for the BMIPS5200 processor
id (PRID_IMP_BMIPS5200) and execute bmips_5xxx_init for these processors to
bring them online.

Tested on 7425, 7429 and 7435 with CPU hotplug. 7435 SMP still needs some
additional changes in the L1 interrupt area to work properly with interrupt
affinity.
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: john@phrozen.org
Cc: cernekee@gmail.com
Cc: jon.fraser@broadcom.com
Cc: jaedon.shin@gmail.com
Cc: dragan.stancevic@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/12377/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent cbbda6e7
...@@ -44,7 +44,7 @@ obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o ...@@ -44,7 +44,7 @@ obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o
obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP_UP) += smp-up.o obj-$(CONFIG_SMP_UP) += smp-up.o
obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o bmips_5xxx_init.o
obj-$(CONFIG_MIPS_MT) += mips-mt.o obj-$(CONFIG_MIPS_MT) += mips-mt.o
obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
......
This diff is collapsed.
...@@ -88,7 +88,7 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) ...@@ -88,7 +88,7 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
li k1, (1 << 19) li k1, (1 << 19)
mfc0 k0, CP0_STATUS mfc0 k0, CP0_STATUS
and k0, k1 and k0, k1
beqz k0, bmips_smp_entry beqz k0, soft_reset
#if defined(CONFIG_CPU_BMIPS5000) #if defined(CONFIG_CPU_BMIPS5000)
mfc0 k0, CP0_PRID mfc0 k0, CP0_PRID
...@@ -126,13 +126,48 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) ...@@ -126,13 +126,48 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
.set arch=r4000 .set arch=r4000
eret eret
#ifdef CONFIG_SMP
soft_reset:
#if defined(CONFIG_CPU_BMIPS5000)
mfc0 k0, CP0_PRID
andi k0, 0xff00
li k1, PRID_IMP_BMIPS5200
bne k0, k1, bmips_smp_entry
/* if running on TP 1, jump to bmips_smp_entry */
mfc0 k0, $22
li k1, (1 << 24)
and k1, k0
bnez k1, bmips_smp_entry
nop
/*
* running on TP0, can not be core 0 (the boot core).
* Check for soft reset. Indicates a warm boot
*/
mfc0 k0, $12
li k1, (1 << 20)
and k0, k1
beqz k0, bmips_smp_entry
/*
* Warm boot.
* Cache init is only done on TP0
*/
la k0, bmips_5xxx_init
jalr k0
nop
b bmips_smp_entry
nop
#endif
/*********************************************************************** /***********************************************************************
* CPU1 reset vector (used for the initial boot only) * CPU1 reset vector (used for the initial boot only)
* This is still part of bmips_reset_nmi_vec(). * This is still part of bmips_reset_nmi_vec().
***********************************************************************/ ***********************************************************************/
#ifdef CONFIG_SMP
bmips_smp_entry: bmips_smp_entry:
/* set up CP0 STATUS; enable FPU */ /* set up CP0 STATUS; enable FPU */
......
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