Commit 21e37283 authored by Dean Nelson's avatar Dean Nelson Committed by Tony Luck

[IA64-SGI] Define some additional SHub1 and Shub2 register symbols

Define some additional SHub1 and SHub2 register symbols.
Signed-off-by: default avatarDean Nelson <dcn@sgi.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent 7223a93a
...@@ -384,6 +384,17 @@ ...@@ -384,6 +384,17 @@
#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 #define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 #define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000
/* ==================================================================== */
/* Register "SH_IPI_ACCESS" */
/* CPU interrupt Access Permission Bits */
/* ==================================================================== */
#define SH1_IPI_ACCESS 0x0000000110060480
#define SH2_IPI_ACCESS0 0x0000000010060c00
#define SH2_IPI_ACCESS1 0x0000000010060c80
#define SH2_IPI_ACCESS2 0x0000000010060d00
#define SH2_IPI_ACCESS3 0x0000000010060d80
/* ==================================================================== */ /* ==================================================================== */
/* Register "SH_INT_CMPB" */ /* Register "SH_INT_CMPB" */
/* RTC Compare Value for Processor B */ /* RTC Compare Value for Processor B */
...@@ -429,6 +440,19 @@ ...@@ -429,6 +440,19 @@
#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff #define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff
/* ==================================================================== */
/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
/* privilege vector for acc=0 */
/* ==================================================================== */
#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300
/* ==================================================================== */
/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
/* privilege vector for acc=0 */
/* ==================================================================== */
#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300
/* ==================================================================== */ /* ==================================================================== */
/* Some MMRs are functionally identical (or close enough) on both SHUB1 */ /* Some MMRs are functionally identical (or close enough) on both SHUB1 */
......
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