Commit 229be9c1 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Shawn Guo

ARM: i.MX clk: Move clock check function in common location

This patch moves clock check function in common i.MX location
and switch i.MX clk drivers to use this new function.
Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent c349adde
...@@ -44,8 +44,6 @@ static void __iomem *ccm __initdata; ...@@ -44,8 +44,6 @@ static void __iomem *ccm __initdata;
static void __init _mx1_clocks_init(unsigned long fref) static void __init _mx1_clocks_init(unsigned long fref)
{ {
unsigned i;
clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref); clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
...@@ -72,10 +70,7 @@ static void __init _mx1_clocks_init(unsigned long fref) ...@@ -72,10 +70,7 @@ static void __init _mx1_clocks_init(unsigned long fref)
clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("imx1 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
} }
int __init mx1_clocks_init(unsigned long fref) int __init mx1_clocks_init(unsigned long fref)
......
...@@ -70,8 +70,6 @@ static struct clk *clk[clk_max]; ...@@ -70,8 +70,6 @@ static struct clk *clk[clk_max];
*/ */
int __init mx21_clocks_init(unsigned long lref, unsigned long href) int __init mx21_clocks_init(unsigned long lref, unsigned long href)
{ {
int i;
clk[ckil] = imx_clk_fixed("ckil", lref); clk[ckil] = imx_clk_fixed("ckil", lref);
clk[ckih] = imx_clk_fixed("ckih", href); clk[ckih] = imx_clk_fixed("ckih", href);
clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
...@@ -126,10 +124,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) ...@@ -126,10 +124,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("i.MX21 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[per1], "per1", NULL); clk_register_clkdev(clk[per1], "per1", NULL);
clk_register_clkdev(clk[per2], "per2", NULL); clk_register_clkdev(clk[per2], "per2", NULL);
......
...@@ -93,8 +93,6 @@ static struct clk *clk[clk_max]; ...@@ -93,8 +93,6 @@ static struct clk *clk[clk_max];
static int __init __mx25_clocks_init(unsigned long osc_rate) static int __init __mx25_clocks_init(unsigned long osc_rate)
{ {
int i;
clk[dummy] = imx_clk_fixed("dummy", 0); clk[dummy] = imx_clk_fixed("dummy", 0);
clk[osc] = imx_clk_fixed("osc", osc_rate); clk[osc] = imx_clk_fixed("osc", osc_rate);
clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
...@@ -224,10 +222,7 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) ...@@ -224,10 +222,7 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
/* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */ /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("i.MX25 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_prepare_enable(clk[emi_ahb]); clk_prepare_enable(clk[emi_ahb]);
......
...@@ -90,8 +90,6 @@ static struct clk_onecell_data clk_data; ...@@ -90,8 +90,6 @@ static struct clk_onecell_data clk_data;
static void __init _mx27_clocks_init(unsigned long fref) static void __init _mx27_clocks_init(unsigned long fref)
{ {
unsigned i;
BUG_ON(!ccm); BUG_ON(!ccm);
clk[dummy] = imx_clk_fixed("dummy", 0); clk[dummy] = imx_clk_fixed("dummy", 0);
...@@ -201,10 +199,7 @@ static void __init _mx27_clocks_init(unsigned long fref) ...@@ -201,10 +199,7 @@ static void __init _mx27_clocks_init(unsigned long fref)
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("i.MX27 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[cpu_div], NULL, "cpu0"); clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
......
...@@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data; ...@@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data;
int __init mx31_clocks_init(unsigned long fref) int __init mx31_clocks_init(unsigned long fref)
{ {
void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
int i;
struct device_node *np; struct device_node *np;
clk[dummy] = imx_clk_fixed("dummy", 0); clk[dummy] = imx_clk_fixed("dummy", 0);
...@@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref) ...@@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref)
clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("imx31 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
......
...@@ -75,7 +75,6 @@ int __init mx35_clocks_init(void) ...@@ -75,7 +75,6 @@ int __init mx35_clocks_init(void)
u32 pdr0, consumer_sel, hsp_sel; u32 pdr0, consumer_sel, hsp_sel;
struct arm_ahb_div *aad; struct arm_ahb_div *aad;
unsigned char *hsp_div; unsigned char *hsp_div;
u32 i;
pdr0 = __raw_readl(base + MXC_CCM_PDR0); pdr0 = __raw_readl(base + MXC_CCM_PDR0);
consumer_sel = (pdr0 >> 16) & 0xf; consumer_sel = (pdr0 >> 16) & 0xf;
...@@ -200,10 +199,7 @@ int __init mx35_clocks_init(void) ...@@ -200,10 +199,7 @@ int __init mx35_clocks_init(void)
clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("i.MX35 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
......
...@@ -131,8 +131,6 @@ static struct clk_onecell_data clk_data; ...@@ -131,8 +131,6 @@ static struct clk_onecell_data clk_data;
static void __init mx5_clocks_common_init(void __iomem *ccm_base) static void __init mx5_clocks_common_init(void __iomem *ccm_base)
{ {
int i;
imx5_pm_set_ccm_base(ccm_base); imx5_pm_set_ccm_base(ccm_base);
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
...@@ -287,11 +285,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base) ...@@ -287,11 +285,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
for (i = 0; i < ARRAY_SIZE(clk); i++)
if (IS_ERR(clk[i]))
pr_err("i.MX5 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0"); clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1"); clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
...@@ -366,7 +359,6 @@ static void __init mx50_clocks_init(struct device_node *np) ...@@ -366,7 +359,6 @@ static void __init mx50_clocks_init(struct device_node *np)
void __iomem *ccm_base; void __iomem *ccm_base;
void __iomem *pll_base; void __iomem *pll_base;
unsigned long r; unsigned long r;
int i;
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
WARN_ON(!pll_base); WARN_ON(!pll_base);
...@@ -383,6 +375,8 @@ static void __init mx50_clocks_init(struct device_node *np) ...@@ -383,6 +375,8 @@ static void __init mx50_clocks_init(struct device_node *np)
ccm_base = of_iomap(np, 0); ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base); WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
...@@ -403,17 +397,12 @@ static void __init mx50_clocks_init(struct device_node *np) ...@@ -403,17 +397,12 @@ static void __init mx50_clocks_init(struct device_node *np)
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("i.MX50 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_data.clks = clk; clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk); clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mx5_clocks_common_init(ccm_base);
/* set SDHC root clock to 200MHZ*/ /* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
...@@ -433,7 +422,6 @@ static void __init mx51_clocks_init(struct device_node *np) ...@@ -433,7 +422,6 @@ static void __init mx51_clocks_init(struct device_node *np)
{ {
void __iomem *ccm_base; void __iomem *ccm_base;
void __iomem *pll_base; void __iomem *pll_base;
int i;
u32 val; u32 val;
pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K); pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
...@@ -451,6 +439,8 @@ static void __init mx51_clocks_init(struct device_node *np) ...@@ -451,6 +439,8 @@ static void __init mx51_clocks_init(struct device_node *np)
ccm_base = of_iomap(np, 0); ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base); WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
...@@ -483,17 +473,12 @@ static void __init mx51_clocks_init(struct device_node *np) ...@@ -483,17 +473,12 @@ static void __init mx51_clocks_init(struct device_node *np)
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("i.MX51 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_data.clks = clk; clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk); clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mx5_clocks_common_init(ccm_base);
clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0"); clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
...@@ -546,7 +531,6 @@ static void __init mx53_clocks_init(struct device_node *np) ...@@ -546,7 +531,6 @@ static void __init mx53_clocks_init(struct device_node *np)
{ {
void __iomem *ccm_base; void __iomem *ccm_base;
void __iomem *pll_base; void __iomem *pll_base;
int i;
unsigned long r; unsigned long r;
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
...@@ -568,6 +552,8 @@ static void __init mx53_clocks_init(struct device_node *np) ...@@ -568,6 +552,8 @@ static void __init mx53_clocks_init(struct device_node *np)
ccm_base = of_iomap(np, 0); ccm_base = of_iomap(np, 0);
WARN_ON(!ccm_base); WARN_ON(!ccm_base);
mx5_clocks_common_init(ccm_base);
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
...@@ -617,17 +603,12 @@ static void __init mx53_clocks_init(struct device_node *np) ...@@ -617,17 +603,12 @@ static void __init mx53_clocks_init(struct device_node *np)
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("i.MX53 clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_data.clks = clk; clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk); clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
mx5_clocks_common_init(ccm_base);
clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2"); clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0"); clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0"); clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
......
...@@ -433,10 +433,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -433,10 +433,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
for (i = 0; i < ARRAY_SIZE(clk); i++) imx_check_clocks(clk, ARRAY_SIZE(clk));
if (IS_ERR(clk[i]))
pr_err("i.MX6q clk %d: register failed with %ld\n",
i, PTR_ERR(clk[i]));
clk_data.clks = clk; clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk); clk_data.clk_num = ARRAY_SIZE(clk);
......
...@@ -348,10 +348,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) ...@@ -348,10 +348,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
for (i = 0; i < ARRAY_SIZE(clks); i++) imx_check_clocks(clks, ARRAY_SIZE(clks));
if (IS_ERR(clks[i]))
pr_err("i.MX6SL clk %d: register failed with %ld\n",
i, PTR_ERR(clks[i]));
clk_data.clks = clks; clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks); clk_data.clk_num = ARRAY_SIZE(clks);
......
...@@ -443,9 +443,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -443,9 +443,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
/* mask handshake of mmdc */ /* mask handshake of mmdc */
writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
for (i = 0; i < ARRAY_SIZE(clks); i++) imx_check_clocks(clks, ARRAY_SIZE(clks));
if (IS_ERR(clks[i]))
pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
clk_data.clks = clks; clk_data.clks = clks;
clk_data.clk_num = ARRAY_SIZE(clks); clk_data.clk_num = ARRAY_SIZE(clks);
......
...@@ -303,6 +303,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) ...@@ -303,6 +303,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
......
...@@ -7,6 +7,16 @@ ...@@ -7,6 +7,16 @@
DEFINE_SPINLOCK(imx_ccm_lock); DEFINE_SPINLOCK(imx_ccm_lock);
void __init imx_check_clocks(struct clk *clks[], unsigned int count)
{
unsigned i;
for (i = 0; i < count; i++)
if (IS_ERR(clks[i]))
pr_err("i.MX clk %u: register failed with %ld\n",
i, PTR_ERR(clks[i]));
}
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
{ {
struct of_phandle_args phandle; struct of_phandle_args phandle;
......
...@@ -6,6 +6,8 @@ ...@@ -6,6 +6,8 @@
extern spinlock_t imx_ccm_lock; extern spinlock_t imx_ccm_lock;
void imx_check_clocks(struct clk *clks[], unsigned int count);
extern void imx_cscmr1_fixup(u32 *val); extern void imx_cscmr1_fixup(u32 *val);
struct clk *imx_clk_pllv1(const char *name, const char *parent, struct clk *imx_clk_pllv1(const char *name, const char *parent,
......
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