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nexedi
linux
Commits
24b1d5fe
Commit
24b1d5fe
authored
Jun 30, 2002
by
David Mosberger
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ia64: Don't inherit all PSR bits across fork() & exec().
parent
afb89291
Changes
3
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3 changed files
with
16 additions
and
6 deletions
+16
-6
arch/ia64/kernel/process.c
arch/ia64/kernel/process.c
+5
-0
include/asm-ia64/kregs.h
include/asm-ia64/kregs.h
+9
-0
include/asm-ia64/processor.h
include/asm-ia64/processor.h
+2
-6
No files found.
arch/ia64/kernel/process.c
View file @
24b1d5fe
...
...
@@ -325,6 +325,11 @@ copy_thread (int nr, unsigned long clone_flags,
/* copy parts of thread_struct: */
p
->
thread
.
ksp
=
(
unsigned
long
)
child_stack
-
16
;
/* stop some PSR bits from being inherited: */
child_ptregs
->
cr_ipsr
=
((
child_ptregs
->
cr_ipsr
|
IA64_PSR_BITS_TO_SET
)
&
~
IA64_PSR_BITS_TO_CLEAR
);
/*
* NOTE: The calling convention considers all floating point
* registers in the high partition (fph) to be scratch. Since
...
...
include/asm-ia64/kregs.h
View file @
24b1d5fe
...
...
@@ -64,6 +64,15 @@
#define IA64_PSR_RI_BIT 41
#define IA64_PSR_ED_BIT 43
#define IA64_PSR_BN_BIT 44
#define IA64_PSR_IA (__IA64_UL(1) << IA64_PSR_IA_BIT)
/* A mask of PSR bits that we generally don't want to inherit across a clone2() or an
execve(). Only list flags here that need to be cleared/set for BOTH clone2() and
execve(). */
#define IA64_PSR_BITS_TO_CLEAR (IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \
IA64_PSR_TB | IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA)
#define IA64_PSR_BITS_TO_SET (IA64_PSR_DFH)
#define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
#define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
...
...
include/asm-ia64/processor.h
View file @
24b1d5fe
...
...
@@ -270,12 +270,8 @@ struct thread_struct {
#define start_thread(regs,new_ip,new_sp) do { \
set_fs(USER_DS); \
ia64_psr(regs)->dfh = 1;
/* disable fph */
\
ia64_psr(regs)->mfh = 0;
/* clear mfh */
\
ia64_psr(regs)->cpl = 3;
/* set user mode */
\
ia64_psr(regs)->ri = 0;
/* clear return slot number */
\
ia64_psr(regs)->is = 0;
/* IA-64 instruction set */
\
ia64_psr(regs)->sp = 1;
/* enforce secure perfmon */
\
regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL | IA64_PSR_SP)) \
& ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \
regs->cr_iip = new_ip; \
regs->ar_rsc = 0xf;
/* eager mode, privilege level 3 */
\
regs->ar_rnat = 0; \
...
...
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