Commit 2730fa0d authored by Dave Airlie's avatar Dave Airlie

Merge branch 'drm-fixes-3.18' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

- fix missing crtc unlock in MC setup
- set optimal CE ram config
- use gart rather than vram for DMA IB tests to avoid coherency issues with HDP
- fix a crasher with laptop mode and TDP scripts

* 'drm-fixes-3.18' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: add missing crtc unlock when setting up the MC
  drm/radeon: use gart for DMA IB tests
  drm/radeon: make sure mode init is complete in bandwidth_update
  drm/radeon: set correct CE ram size for CIK
parents ed78bb84 f0d7bfb9
...@@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev) ...@@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev)
/* init the CE partitions. CE only used for gfx on CIK */ /* init the CE partitions. CE only used for gfx on CIK */
radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
radeon_ring_write(ring, 0xc000); radeon_ring_write(ring, 0x8000);
radeon_ring_write(ring, 0xc000); radeon_ring_write(ring, 0x8000);
/* setup clear context state */ /* setup clear context state */
radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
...@@ -9447,6 +9447,9 @@ void dce8_bandwidth_update(struct radeon_device *rdev) ...@@ -9447,6 +9447,9 @@ void dce8_bandwidth_update(struct radeon_device *rdev)
u32 num_heads = 0, lb_size; u32 num_heads = 0, lb_size;
int i; int i;
if (!rdev->mode_info.mode_config_initialized)
return;
radeon_update_display_priority(rdev); radeon_update_display_priority(rdev);
for (i = 0; i < rdev->num_crtc; i++) { for (i = 0; i < rdev->num_crtc; i++) {
......
...@@ -667,17 +667,20 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) ...@@ -667,17 +667,20 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
{ {
struct radeon_ib ib; struct radeon_ib ib;
unsigned i; unsigned i;
unsigned index;
int r; int r;
void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
u32 tmp = 0; u32 tmp = 0;
u64 gpu_addr;
if (!ptr) { if (ring->idx == R600_RING_TYPE_DMA_INDEX)
DRM_ERROR("invalid vram scratch pointer\n"); index = R600_WB_DMA_RING_TEST_OFFSET;
return -EINVAL; else
} index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
gpu_addr = rdev->wb.gpu_addr + index;
tmp = 0xCAFEDEAD; tmp = 0xCAFEDEAD;
writel(tmp, ptr); rdev->wb.wb[index/4] = cpu_to_le32(tmp);
r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
if (r) { if (r) {
...@@ -686,8 +689,8 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) ...@@ -686,8 +689,8 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
} }
ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; ib.ptr[1] = lower_32_bits(gpu_addr);
ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr); ib.ptr[2] = upper_32_bits(gpu_addr);
ib.ptr[3] = 1; ib.ptr[3] = 1;
ib.ptr[4] = 0xDEADBEEF; ib.ptr[4] = 0xDEADBEEF;
ib.length_dw = 5; ib.length_dw = 5;
...@@ -704,7 +707,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) ...@@ -704,7 +707,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
return r; return r;
} }
for (i = 0; i < rdev->usec_timeout; i++) { for (i = 0; i < rdev->usec_timeout; i++) {
tmp = readl(ptr); tmp = le32_to_cpu(rdev->wb.wb[index/4]);
if (tmp == 0xDEADBEEF) if (tmp == 0xDEADBEEF)
break; break;
DRM_UDELAY(1); DRM_UDELAY(1);
......
...@@ -2345,6 +2345,9 @@ void evergreen_bandwidth_update(struct radeon_device *rdev) ...@@ -2345,6 +2345,9 @@ void evergreen_bandwidth_update(struct radeon_device *rdev)
u32 num_heads = 0, lb_size; u32 num_heads = 0, lb_size;
int i; int i;
if (!rdev->mode_info.mode_config_initialized)
return;
radeon_update_display_priority(rdev); radeon_update_display_priority(rdev);
for (i = 0; i < rdev->num_crtc; i++) { for (i = 0; i < rdev->num_crtc; i++) {
...@@ -2552,6 +2555,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav ...@@ -2552,6 +2555,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
} }
} else { } else {
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
......
...@@ -3207,6 +3207,9 @@ void r100_bandwidth_update(struct radeon_device *rdev) ...@@ -3207,6 +3207,9 @@ void r100_bandwidth_update(struct radeon_device *rdev)
uint32_t pixel_bytes1 = 0; uint32_t pixel_bytes1 = 0;
uint32_t pixel_bytes2 = 0; uint32_t pixel_bytes2 = 0;
if (!rdev->mode_info.mode_config_initialized)
return;
radeon_update_display_priority(rdev); radeon_update_display_priority(rdev);
if (rdev->mode_info.crtcs[0]->base.enabled) { if (rdev->mode_info.crtcs[0]->base.enabled) {
......
...@@ -338,17 +338,17 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) ...@@ -338,17 +338,17 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
{ {
struct radeon_ib ib; struct radeon_ib ib;
unsigned i; unsigned i;
unsigned index;
int r; int r;
void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
u32 tmp = 0; u32 tmp = 0;
u64 gpu_addr;
if (!ptr) { if (ring->idx == R600_RING_TYPE_DMA_INDEX)
DRM_ERROR("invalid vram scratch pointer\n"); index = R600_WB_DMA_RING_TEST_OFFSET;
return -EINVAL; else
} index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
tmp = 0xCAFEDEAD; gpu_addr = rdev->wb.gpu_addr + index;
writel(tmp, ptr);
r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
if (r) { if (r) {
...@@ -357,8 +357,8 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) ...@@ -357,8 +357,8 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
} }
ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; ib.ptr[1] = lower_32_bits(gpu_addr);
ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
ib.ptr[3] = 0xDEADBEEF; ib.ptr[3] = 0xDEADBEEF;
ib.length_dw = 4; ib.length_dw = 4;
...@@ -374,7 +374,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) ...@@ -374,7 +374,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
return r; return r;
} }
for (i = 0; i < rdev->usec_timeout; i++) { for (i = 0; i < rdev->usec_timeout; i++) {
tmp = readl(ptr); tmp = le32_to_cpu(rdev->wb.wb[index/4]);
if (tmp == 0xDEADBEEF) if (tmp == 0xDEADBEEF)
break; break;
DRM_UDELAY(1); DRM_UDELAY(1);
......
...@@ -879,6 +879,9 @@ void rs600_bandwidth_update(struct radeon_device *rdev) ...@@ -879,6 +879,9 @@ void rs600_bandwidth_update(struct radeon_device *rdev)
u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
/* FIXME: implement full support */ /* FIXME: implement full support */
if (!rdev->mode_info.mode_config_initialized)
return;
radeon_update_display_priority(rdev); radeon_update_display_priority(rdev);
if (rdev->mode_info.crtcs[0]->base.enabled) if (rdev->mode_info.crtcs[0]->base.enabled)
......
...@@ -579,6 +579,9 @@ void rs690_bandwidth_update(struct radeon_device *rdev) ...@@ -579,6 +579,9 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt; u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt; u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
if (!rdev->mode_info.mode_config_initialized)
return;
radeon_update_display_priority(rdev); radeon_update_display_priority(rdev);
if (rdev->mode_info.crtcs[0]->base.enabled) if (rdev->mode_info.crtcs[0]->base.enabled)
......
...@@ -1277,6 +1277,9 @@ void rv515_bandwidth_update(struct radeon_device *rdev) ...@@ -1277,6 +1277,9 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
struct drm_display_mode *mode0 = NULL; struct drm_display_mode *mode0 = NULL;
struct drm_display_mode *mode1 = NULL; struct drm_display_mode *mode1 = NULL;
if (!rdev->mode_info.mode_config_initialized)
return;
radeon_update_display_priority(rdev); radeon_update_display_priority(rdev);
if (rdev->mode_info.crtcs[0]->base.enabled) if (rdev->mode_info.crtcs[0]->base.enabled)
......
...@@ -2384,6 +2384,9 @@ void dce6_bandwidth_update(struct radeon_device *rdev) ...@@ -2384,6 +2384,9 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
u32 num_heads = 0, lb_size; u32 num_heads = 0, lb_size;
int i; int i;
if (!rdev->mode_info.mode_config_initialized)
return;
radeon_update_display_priority(rdev); radeon_update_display_priority(rdev);
for (i = 0; i < rdev->num_crtc; i++) { for (i = 0; i < rdev->num_crtc; i++) {
......
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