Commit 27c6f0a5 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter

drm/i915: don't implement WaDisableEarlyCull for Haswell

Introduced in commit 87f8020e:
  drm/i915: implement WaDisableEarlyCull for VLV and IVB

Notice that the original patch sent to the mailing list did not
include the Haswell chunk, it was added later.

The bit set by the commit does not exist on Haswell machines (at least
that's what the documentation says). Also, the commit gives me a GPU
hang every time we're loading the driver. So let's revert the Haswell
chunk, making the patch do only what its title actually says.
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1e6210f4
...@@ -3470,10 +3470,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) ...@@ -3470,10 +3470,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
*/ */
I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
/* WaDisableEarlyCull */
I915_WRITE(_3D_CHICKEN3,
_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment