Commit 29d65406 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie

drm/radeon: fix bank information in tiling config

While there are cards with more than 8 mem banks, the max
number of banks from a tiling perspective is 8, so cap
the tiling config at 8 banks.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=43448Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 08ef8e41
...@@ -2136,9 +2136,12 @@ static void evergreen_gpu_init(struct radeon_device *rdev) ...@@ -2136,9 +2136,12 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
if (rdev->flags & RADEON_IS_IGP) if (rdev->flags & RADEON_IS_IGP)
rdev->config.evergreen.tile_config |= 1 << 4; rdev->config.evergreen.tile_config |= 1 << 4;
else else {
rdev->config.evergreen.tile_config |= if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; rdev->config.evergreen.tile_config |= 1 << 4;
else
rdev->config.evergreen.tile_config |= 0 << 4;
}
rdev->config.evergreen.tile_config |= rdev->config.evergreen.tile_config |=
((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8; ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
rdev->config.evergreen.tile_config |= rdev->config.evergreen.tile_config |=
......
...@@ -866,9 +866,12 @@ static void cayman_gpu_init(struct radeon_device *rdev) ...@@ -866,9 +866,12 @@ static void cayman_gpu_init(struct radeon_device *rdev)
/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
if (rdev->flags & RADEON_IS_IGP) if (rdev->flags & RADEON_IS_IGP)
rdev->config.cayman.tile_config |= 1 << 4; rdev->config.cayman.tile_config |= 1 << 4;
else else {
rdev->config.cayman.tile_config |= if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; rdev->config.cayman.tile_config |= 1 << 4;
else
rdev->config.cayman.tile_config |= 0 << 4;
}
rdev->config.cayman.tile_config |= rdev->config.cayman.tile_config |=
((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
rdev->config.cayman.tile_config |= rdev->config.cayman.tile_config |=
......
...@@ -689,8 +689,12 @@ static void rv770_gpu_init(struct radeon_device *rdev) ...@@ -689,8 +689,12 @@ static void rv770_gpu_init(struct radeon_device *rdev)
if (rdev->family == CHIP_RV770) if (rdev->family == CHIP_RV770)
gb_tiling_config |= BANK_TILING(1); gb_tiling_config |= BANK_TILING(1);
else else {
gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
gb_tiling_config |= BANK_TILING(1);
else
gb_tiling_config |= BANK_TILING(0);
}
rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment