Commit 2d1c1939 authored by Fabio Estevam's avatar Fabio Estevam Committed by Greg Kroah-Hartman

nvmem: Broaden the selection of NVMEM_SNVS_LPGPR

The SNVS LPGR IP block is also found on other i.MX SoCs that
are not covered by the current SOC_IMX6 || SOC_IMX7D logic.

One example is the i.MX7ULP.

To avoid keep expanding the SoC logic selection, make it broader
by using the more generic ARCH_MXC symbol instead.
Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 67ff708b
...@@ -195,7 +195,7 @@ config MESON_MX_EFUSE ...@@ -195,7 +195,7 @@ config MESON_MX_EFUSE
config NVMEM_SNVS_LPGPR config NVMEM_SNVS_LPGPR
tristate "Support for Low Power General Purpose Register" tristate "Support for Low Power General Purpose Register"
depends on SOC_IMX6 || SOC_IMX7D || COMPILE_TEST depends on ARCH_MXC || COMPILE_TEST
help help
This is a driver for Low Power General Purpose Register (LPGPR) available on This is a driver for Low Power General Purpose Register (LPGPR) available on
i.MX6 and i.MX7 SoCs in Secure Non-Volatile Storage (SNVS) of this chip. i.MX6 and i.MX7 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
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