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Commit 2daea7af authored by Tomi Valkeinen's avatar Tomi Valkeinen
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OMAPDSS: DSI: use common DSS PLL support 

Now that we have the common DSS PLL support, change DSI to use it. This
results in quite a lot of changes, but almost all of them are trivial
name changes.

The functions to calculate and program the PLL settings can be removed
from dsi.c, as the common PLL API contains the same functionality.

We also need to create struct dss_pll_hw entries for PLL hardware
features for different OMAP platforms, instead of using the
dss_features.c as the old code does.
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 0a20170a
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Inline Side-by-side
Showing with 255 additions and 489 deletions
drivers/video/fbdev/omap2/dss/dispc.c
View file @ 2daea7af
......@@ -3028,7 +3028,7 @@ static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
unsigned long dispc_fclk_rate(void)
{
struct platform_device *dsidev;
struct dss_pll *pll;
unsigned long r = 0;
switch (dss_get_dispc_clk_source()) {
......@@ -3036,12 +3036,12 @@ unsigned long dispc_fclk_rate(void)
r = dss_get_dispc_clk_rate();
break;
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
dsidev = dsi_get_dsidev_from_id(0);
r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
pll = dss_pll_find("dsi0");
r = pll->cinfo.clkout[0];
break;
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
dsidev = dsi_get_dsidev_from_id(1);
r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
pll = dss_pll_find("dsi1");
r = pll->cinfo.clkout[0];
break;
default:
BUG();
......@@ -3053,7 +3053,7 @@ unsigned long dispc_fclk_rate(void)
unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
{
struct platform_device *dsidev;
struct dss_pll *pll;
int lcd;
unsigned long r;
u32 l;
......@@ -3068,12 +3068,12 @@ unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
r = dss_get_dispc_clk_rate();
break;
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
dsidev = dsi_get_dsidev_from_id(0);
r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
pll = dss_pll_find("dsi0");
r = pll->cinfo.clkout[0];
break;
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
dsidev = dsi_get_dsidev_from_id(1);
r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
pll = dss_pll_find("dsi1");
r = pll->cinfo.clkout[0];
break;
default:
BUG();
......
drivers/video/fbdev/omap2/dss/dpi.c
View file @ 2daea7af
......@@ -31,6 +31,7 @@
#include <linux/regulator/consumer.h>
#include <linux/string.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <video/omapdss.h>
......@@ -43,7 +44,7 @@ struct dpi_data {
struct platform_device *pdev;
struct regulator *vdds_dsi_reg;
struct platform_device *dsidev;
struct dss_pll *pll;
struct mutex lock;
......@@ -67,7 +68,7 @@ static struct dpi_data *dpi_get_data_from_pdev(struct platform_device *pdev)
return dev_get_drvdata(&pdev->dev);
}
static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
static struct dss_pll *dpi_get_pll(enum omap_channel channel)
{
/*
* XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
......@@ -88,9 +89,9 @@ static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
case OMAPDSS_VER_OMAP4:
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
return dsi_get_dsidev_from_id(0);
return dss_pll_find("dsi0");
case OMAP_DSS_CHANNEL_LCD2:
return dsi_get_dsidev_from_id(1);
return dss_pll_find("dsi1");
default:
return NULL;
}
......@@ -98,9 +99,9 @@ static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
case OMAPDSS_VER_OMAP5:
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
return dsi_get_dsidev_from_id(0);
return dss_pll_find("dsi0");
case OMAP_DSS_CHANNEL_LCD3:
return dsi_get_dsidev_from_id(1);
return dss_pll_find("dsi1");
default:
return NULL;
}
......@@ -127,7 +128,7 @@ static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
}
struct dpi_clk_calc_ctx {
struct platform_device *dsidev;
struct dss_pll *pll;
/* inputs */
......@@ -135,7 +136,7 @@ struct dpi_clk_calc_ctx {
/* outputs */
struct dsi_clock_info dsi_cinfo;
struct dss_pll_clock_info dsi_cinfo;
unsigned long fck;
struct dispc_clock_info dispc_cinfo;
};
......@@ -167,7 +168,7 @@ static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
}
static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
void *data)
{
struct dpi_clk_calc_ctx *ctx = data;
......@@ -177,10 +178,10 @@ static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
* shifted. So skip all odd dividers when the pixel clock is on the
* higher side.
*/
if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000)
if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000)
return false;
ctx->dsi_cinfo.regm_hsdiv[HSDIV_DISPC] = regm_dispc;
ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
......@@ -188,19 +189,20 @@ static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
}
static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
unsigned long pll,
static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
unsigned long clkdco,
void *data)
{
struct dpi_clk_calc_ctx *ctx = data;
ctx->dsi_cinfo.regn = regn;
ctx->dsi_cinfo.regm = regm;
ctx->dsi_cinfo.n = n;
ctx->dsi_cinfo.m = m;
ctx->dsi_cinfo.fint = fint;
ctx->dsi_cinfo.clkdco = pll;
ctx->dsi_cinfo.clkdco = clkdco;
return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
dpi_calc_hsdiv_cb, ctx);
return dss_pll_hsdiv_calc(ctx->pll, clkdco,
ctx->pck_min, dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
dpi_calc_hsdiv_cb, ctx);
}
static bool dpi_calc_dss_cb(unsigned long fck, void *data)
......@@ -219,17 +221,17 @@ static bool dpi_dsi_clk_calc(struct dpi_data *dpi, unsigned long pck,
unsigned long clkin;
unsigned long pll_min, pll_max;
clkin = dsi_get_pll_clkin(dpi->dsidev);
memset(ctx, 0, sizeof(*ctx));
ctx->dsidev = dpi->dsidev;
ctx->pll = dpi->pll;
ctx->pck_min = pck - 1000;
ctx->pck_max = pck + 1000;
pll_min = 0;
pll_max = 0;
return dsi_pll_calc(dpi->dsidev, clkin,
clkin = clk_get_rate(ctx->pll->clkin);
return dss_pll_calc(ctx->pll, clkin,
pll_min, pll_max,
dpi_calc_pll_cb, ctx);
}
......@@ -277,7 +279,7 @@ static int dpi_set_dsi_clk(struct dpi_data *dpi, enum omap_channel channel,
if (!ok)
return -EINVAL;
r = dsi_pll_set_clock_div(dpi->dsidev, &ctx.dsi_cinfo);
r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo);
if (r)
return r;
......@@ -327,7 +329,7 @@ static int dpi_set_mode(struct dpi_data *dpi)
unsigned long pck;
int r = 0;
if (dpi->dsidev)
if (dpi->pll)
r = dpi_set_dsi_clk(dpi, mgr->id, t->pixelclock, &fck,
&lck_div, &pck_div);
else
......@@ -401,8 +403,8 @@ static int dpi_display_enable(struct omap_dss_device *dssdev)
if (r)
goto err_src_sel;
if (dpi->dsidev) {
r = dsi_pll_init(dpi->dsidev);
if (dpi->pll) {
r = dss_pll_enable(dpi->pll);
if (r)
goto err_dsi_pll_init;
}
......@@ -425,8 +427,8 @@ static int dpi_display_enable(struct omap_dss_device *dssdev)
err_mgr_enable:
err_set_mode:
if (dpi->dsidev)
dsi_pll_uninit(dpi->dsidev, true);
if (dpi->pll)
dss_pll_disable(dpi->pll);
err_dsi_pll_init:
err_src_sel:
dispc_runtime_put();
......@@ -449,9 +451,9 @@ static void dpi_display_disable(struct omap_dss_device *dssdev)
dss_mgr_disable(mgr);
if (dpi->dsidev) {
if (dpi->pll) {
dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
dsi_pll_uninit(dpi->dsidev, true);
dss_pll_disable(dpi->pll);
}
dispc_runtime_put();
......@@ -505,7 +507,7 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
if (timings->pixelclock == 0)
return -EINVAL;
if (dpi->dsidev) {
if (dpi->pll) {
ok = dpi_dsi_clk_calc(dpi, timings->pixelclock, &ctx);
if (!ok)
return -EINVAL;
......@@ -540,17 +542,17 @@ static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
mutex_unlock(&dpi->lock);
}
static int dpi_verify_dsi_pll(struct platform_device *dsidev)
static int dpi_verify_dsi_pll(struct dss_pll *pll)
{
int r;
/* do initial setup with the PLL to see if it is operational */
r = dsi_pll_init(dsidev);
r = dss_pll_enable(pll);
if (r)
return r;
dsi_pll_uninit(dsidev, true);
dss_pll_disable(pll);
return 0;
}
......@@ -579,21 +581,21 @@ static int dpi_init_regulator(struct dpi_data *dpi)
static void dpi_init_pll(struct dpi_data *dpi)
{
struct platform_device *dsidev;
struct dss_pll *pll;
if (dpi->dsidev)
if (dpi->pll)
return;
dsidev = dpi_get_dsidev(dpi->output.dispc_channel);
if (!dsidev)
pll = dpi_get_pll(dpi->output.dispc_channel);
if (!pll)
return;
if (dpi_verify_dsi_pll(dsidev)) {
if (dpi_verify_dsi_pll(pll)) {
DSSWARN("DSI PLL not operational\n");
return;
}
dpi->dsidev = dsidev;
dpi->pll = pll;
}
/*
......
drivers/video/fbdev/omap2/dss/dsi.c
View file @ 2daea7af
This diff is collapsed.
drivers/video/fbdev/omap2/dss/dss.h
View file @ 2daea7af
......@@ -173,18 +173,6 @@ struct dispc_clock_info {
u16 pck_div;
};
struct dsi_clock_info {
/* rates that we get with dividers below */
unsigned long fint;
unsigned long clkdco;
unsigned long clkout[4];
/* dividers */
u16 regn;
u16 regm;
u16 regm_hsdiv[4];
};
struct dss_lcd_mgr_config {
enum dss_io_pad_mode io_pad_mode;
......@@ -318,11 +306,6 @@ static inline void __exit sdi_uninit_port(struct device_node *port)
/* DSI */
typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
unsigned long pll, void *data);
typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
void *data);
#ifdef CONFIG_OMAP2_DSS_DSI
struct dentry;
......@@ -336,71 +319,12 @@ void dsi_dump_clocks(struct seq_file *s);
void dsi_irq_handler(void);
u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
unsigned long pll_min, unsigned long pll_max,
dsi_pll_calc_func func, void *data);
unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
int dsi_pll_set_clock_div(struct platform_device *dsidev,
struct dsi_clock_info *cinfo);
int dsi_pll_init(struct platform_device *dsidev);
void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
struct platform_device *dsi_get_dsidev_from_id(int module);
#else
static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
{
WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
return 0;
}
static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
{
WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
return 0;
}
static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
struct dsi_clock_info *cinfo)
{
WARN("%s: DSI not compiled in\n", __func__);
return -ENODEV;
}
static inline int dsi_pll_init(struct platform_device *dsidev)
{
WARN("%s: DSI not compiled in\n", __func__);
return -ENODEV;
}
static inline void dsi_pll_uninit(struct platform_device *dsidev,
bool disconnect_lanes)
{
}
static inline struct platform_device *dsi_get_dsidev_from_id(int module)
{
return NULL;
}
static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
{
return 0;
}
static inline bool dsi_hsdiv_calc(struct platform_device *dsidev,
unsigned long pll, unsigned long out_min,
dsi_hsdiv_calc_func func, void *data)
{
return false;
}
static inline bool dsi_pll_calc(struct platform_device *dsidev,
unsigned long clkin,
unsigned long pll_min, unsigned long pll_max,
dsi_pll_calc_func func, void *data)
{
return false;
}
#endif
/* DPI */
......
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