Commit 2e132740 authored by Nicolin Chen's avatar Nicolin Chen Committed by Mark Brown

ASoC: fsl_ssi: Clear FIFO directly in fsl_ssi_config()

The FIFO clear helper function is just one line of code now.
So it could be cleaned up by removing it and calling regmap
directly.

Meanwhile, FIFO clear could be applied to all use cases, not
confined to AC97. So this patch also moves FIFO clear in the
trigger() to fsl_ssi_config() and removes the AC97 check.

Note that SOR register is safe from offline_config HW limit.
Signed-off-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Tested-by: default avatarCaleb Crome <caleb@crome.org>
Tested-by: default avatarMaciej S. Szmigiero <mail@maciej.szmigiero.name>
Reviewed-by: default avatarMaciej S. Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 06a99454
......@@ -409,17 +409,6 @@ static void fsl_ssi_rxtx_config(struct fsl_ssi *ssi, bool enable)
}
}
/**
* Clear remaining data in the FIFO to avoid dirty data or channel slipping
*/
static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx)
{
bool tx = !is_rx;
regmap_update_bits(ssi->regs, REG_SSI_SOR,
SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
}
/**
* Exclude bits that are used by the opposite stream
*
......@@ -446,10 +435,11 @@ static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx)
static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
struct fsl_ssi_regvals *vals)
{
int adir = (&ssi->regvals[TX] == vals) ? RX : TX;
int dir = (&ssi->regvals[TX] == vals) ? TX : RX;
bool tx = &ssi->regvals[TX] == vals;
struct regmap *regs = ssi->regs;
struct fsl_ssi_regvals *avals;
int adir = tx ? RX : TX;
int dir = tx ? TX : RX;
bool aactive;
/* Check if the opposite stream is active */
......@@ -489,7 +479,9 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
/* Online configure single direction while SSI is running */
if (enable) {
fsl_ssi_fifo_clear(ssi, vals->scr & SSI_SCR_RE);
/* Clear FIFO to prevent dirty data or channel slipping */
regmap_update_bits(ssi->regs, REG_SSI_SOR,
SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
regmap_update_bits(regs, REG_SSI_SRCR, vals->srcr, vals->srcr);
regmap_update_bits(regs, REG_SSI_STCR, vals->stcr, vals->stcr);
......@@ -511,6 +503,10 @@ static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable,
regmap_update_bits(regs, REG_SSI_SRCR, srcr, 0);
regmap_update_bits(regs, REG_SSI_STCR, stcr, 0);
regmap_update_bits(regs, REG_SSI_SIER, sier, 0);
/* Clear FIFO to prevent dirty data or channel slipping */
regmap_update_bits(ssi->regs, REG_SSI_SOR,
SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx));
}
config_done:
......@@ -1091,7 +1087,6 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai);
struct regmap *regs = ssi->regs;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
......@@ -1116,14 +1111,6 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
return -EINVAL;
}
/* Clear corresponding FIFO */
if (fsl_ssi_is_ac97(ssi)) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
regmap_write(regs, REG_SSI_SOR, SSI_SOR_TX_CLR);
else
regmap_write(regs, REG_SSI_SOR, SSI_SOR_RX_CLR);
}
return 0;
}
......
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