Commit 2e151c70 authored by Peter Neubauer's avatar Peter Neubauer Committed by Thomas Gleixner

x86: HPET force enable for e6xx based systems

As the Soekris net6501 and other e6xx based systems do not have
any ACPI implementation, HPET won't get enabled.
This patch enables HPET on such platforms.

[    0.430149] pci 0000:00:01.0: Force enabled HPET at 0xfed00000
[    0.644838] HPET: 3 timers in total, 0 timers will be used for per-cpu timer

Original patch by Peter Neubauer (http://www.mail-archive.com/soekris-tech@lists.soekris.com/msg06462.html)
slightly modified by Conrad Kostecki <ck@conrad-kostecki.de> and massaged
accoring to Thomas Gleixners <tglx@linutronix.de> by me.
Suggested-by: default avatarConrad Kostecki <ck@conrad-kostecki.de>
Signed-off-by: default avatarEric Sesterhenn <eric.sesterhenn@lsexperts.de>
Cc: Peter Neubauer <pneubauer@bluerwhite.org>
Link: http://lkml.kernel.org/r/5412D3A5.2030909@lsexperts.deSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 8dc12f93
...@@ -497,6 +497,24 @@ void force_hpet_resume(void) ...@@ -497,6 +497,24 @@ void force_hpet_resume(void)
} }
} }
/*
* According to the datasheet e6xx systems have the HPET hardwired to
* 0xfed00000
*/
static void e6xx_force_enable_hpet(struct pci_dev *dev)
{
if (hpet_address || force_hpet_address)
return;
force_hpet_address = 0xFED00000;
force_hpet_resume_type = NONE_FORCE_HPET_RESUME;
dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
"0x%lx\n", force_hpet_address);
return;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU,
e6xx_force_enable_hpet);
/* /*
* HPET MSI on some boards (ATI SB700/SB800) has side effect on * HPET MSI on some boards (ATI SB700/SB800) has side effect on
* floppy DMA. Disable HPET MSI on such platforms. * floppy DMA. Disable HPET MSI on such platforms.
......
...@@ -2860,6 +2860,7 @@ ...@@ -2860,6 +2860,7 @@
#define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601 #define PCI_DEVICE_ID_INTEL_82372FB_1 0x7601
#define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_SCH_LPC 0x8119
#define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a #define PCI_DEVICE_ID_INTEL_SCH_IDE 0x811a
#define PCI_DEVICE_ID_INTEL_E6XX_CU 0x8183
#define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186 #define PCI_DEVICE_ID_INTEL_ITC_LPC 0x8186
#define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4
#define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5
......
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