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Commit 2f34a64a authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM device-tree updates from Olof Johansson:
 "Business as usual -- the bulk of our changes are to devicetree files
  with new hardware support, new SoCs and platforms, and new board
  types.

  New SoCs/platforms:
   - Raspberry Pi Compute Module (CM1) and IO board
   - i.MX6SSL from NXP
   - Renesas RZ/N1D SoC (R9A06G032), Dual Cortex-A7 with Ethernet, CAN
     and PLC interfaces
   - TI AM654 SoC, Quad Cortex-A53, safety subsystem with Cortex-R5
     controllers, communication and PRU subsystem and lots of other
     interfaces (PCIe, USB3, etc).

  New boards and systems:
   - Several Atmel at91-based boards from Laird
   - Marvell Armada388-based Helios4 board from SolidRun
   - Samsung Aires-based phones (s5pv210)
   - Allwinner A64-based Pinebook laptop

  In addition to the above, there's the usual amount of new devices
  described on existing platforms, fixes and tweaks and new minor
  variants of boards/platforms"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (478 commits)
  arm64: dts: sdm845: Add tsens nodes
  arm64: dts: msm8996: thermal: Initialise via DT and add second controller
  arm64: dts: sprd: Add one suspend timer
  arm64: dts: sprd: Add SC27XX ADC device
  arm64: dts: sprd: Add SC27XX eFuse device
  arm64: dts: sprd: Add SC27XX vibrator device
  arm64: dts: sprd: Add SC27XX breathing light controller device
  arm64: dts: meson-axg: add spdif-dit codec
  arm64: dts: meson-axg: add lineout codec
  arm64: dts: meson-axg: add linein codec
  arm64: dts: meson-axg: add tdm interfaces
  arm64: dts: meson-axg: add tdmout formatters
  arm64: dts: meson-axg: add tdmin formatters
  arm64: dts: meson-axg: add spdifout
  arm64: dts: rockchip: add led support for Firefly-RK3399
  arm64: dts: rockchip: remove deprecated Type-C PHY properties on rk3399
  arm64: dts: rockchip: add power button support for Firefly-RK3399
  ARM: dts: aspeed: Add coprocessor interrupt controller
  arm64: dts: meson-axg: add audio arb reset controller
  arm64: dts: meson-axg: add usb power regulator
  ...
parents ee090756 afd3e3da
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Documentation/devicetree/bindings/arm/adapteva.txt deleted 100644 → 0
View file @ ee090756
Adapteva Platforms Device Tree Bindings
---------------------------------------
Parallella board
Required root node properties:
- compatible = "adapteva,parallella";
Documentation/devicetree/bindings/arm/amlogic.txt
View file @ 2f34a64a
......@@ -41,6 +41,14 @@ Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905d", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXL S805X SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s805x", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXL S905W SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905w", "amlogic,meson-gxl";
Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
......@@ -79,6 +87,11 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
- "amlogic,p241" (Meson gxl s805x)
- "amlogic,p281" (Meson gxl s905w)
- "oranth,tx3-mini" (Meson gxl s905w)
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
- "khadas,vim2" (Meson gxm s912)
......
Documentation/devicetree/bindings/arm/atmel-pmc.txt deleted 100644 → 0
View file @ ee090756
* Power Management Controller (PMC)
Required properties:
- compatible: Should be "atmel,<chip>-pmc".
<chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12,
at91sam9x5, sama5d3
- reg: Should contain PMC registers location and length
Examples:
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
};
Documentation/devicetree/bindings/arm/cpus.txt
View file @ 2f34a64a
......@@ -183,6 +183,7 @@ described below.
"marvell,sheeva-v5"
"nvidia,tegra132-denver"
"nvidia,tegra186-denver"
"nvidia,tegra194-carmel"
"qcom,krait"
"qcom,kryo"
"qcom,kryo385"
......@@ -219,6 +220,7 @@ described below.
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
"renesas,r9a06g032-smp"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
......
Documentation/devicetree/bindings/arm/freescale/m4if.txt 0 → 100644
View file @ 2f34a64a
* Freescale Multi Master Multi Memory Interface (M4IF) module
Required properties:
- compatible : Should be "fsl,imx51-m4if"
- reg : Address and length of the register set for the device
Example:
m4if: m4if@83fd8000 {
compatible = "fsl,imx51-m4if";
reg = <0x83fd8000 0x1000>;
};
Documentation/devicetree/bindings/arm/freescale/tigerp.txt 0 → 100644
View file @ 2f34a64a
* Freescale Tigerp platform module
Required properties:
- compatible : Should be "fsl,imx51-tigerp"
- reg : Address and length of the register set for the device
Example:
tigerp: tigerp@83fa0000 {
compatible = "fsl,imx51-tigerp";
reg = <0x83fa0000 0x28>;
};
Documentation/devicetree/bindings/arm/fsl.txt
View file @ 2f34a64a
......@@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board
Required root node properties:
- compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
i.MX6SLL EVK board
Required root node properties:
- compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
Generic i.MX boards
-------------------
......
Documentation/devicetree/bindings/arm/insignal-boards.txt deleted 100644 → 0
View file @ ee090756
* Insignal's Exynos4210 based Origen evaluation board
Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC.
Required root node properties:
- compatible = should be one or more of the following.
(a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
(b) "samsung,exynos4210" - for boards based on Exynos4210 SoC.
Documentation/devicetree/bindings/arm/mediatek.txt
View file @ 2f34a64a
......@@ -51,6 +51,9 @@ Supported boards:
- Evaluation board for MT6797(Helio X20):
Required root node properties:
- compatible = "mediatek,mt6797-evb", "mediatek,mt6797";
- Mediatek X20 Development Board:
Required root node properties:
- compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
......@@ -63,9 +66,6 @@ Supported boards:
- Reference board for MT7623n with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623n with NAND:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
- Bananapi BPI-R2 board:
- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
......
Documentation/devicetree/bindings/arm/omap/l4.txt
View file @ 2f34a64a
......@@ -7,6 +7,7 @@ Required properties:
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
......@@ -15,11 +16,21 @@ Required properties:
Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
- reg : registers link agent and interconnect agent and access protection
- reg-names : "la" for link agent, "ia0" to "ia3" for one to three
interconnect agent instances, "ap" for access if it exists
Examples:
l4: l4@48000000 {
compatible "ti,omap2-l4", "simple-bus";
l4: interconnect@48000000 {
compatible "ti,omap4-l4-per", "simple-bus";
reg = <0x48000000 0x800>,
<0x48000800 0x800>,
<0x48001000 0x400>,
<0x48001400 0x400>,
<0x48001800 0x400>,
<0x48001c00 0x400>;
reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
......
Documentation/devicetree/bindings/arm/rockchip.txt
View file @ 2f34a64a
Rockchip platforms device tree bindings
---------------------------------------
- 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
Required root node properties:
- compatible = "vamrs,ficus", "rockchip,rk3399";
- Amarula Vyasa RK3288 board
Required root node properties:
- compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
......@@ -66,6 +71,15 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
- Google Bob (Asus Chromebook Flip C101PA):
Required root node properties:
compatible = "google,bob-rev13", "google,bob-rev12",
"google,bob-rev11", "google,bob-rev10",
"google,bob-rev9", "google,bob-rev8",
"google,bob-rev7", "google,bob-rev6",
"google,bob-rev5", "google,bob-rev4",
"google,bob", "google,gru", "rockchip,rk3399";
- Google Brain (dev-board):
Required root node properties:
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
......
Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
View file @ 2f34a64a
* Samsung's Exynos SoC based boards
* Samsung's Exynos and S5P SoC based boards
Required root node properties:
- compatible = should be one or more of the following.
- "samsung,aries" - for S5PV210-based Samsung Aries board.
- "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
- "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
......
Documentation/devicetree/bindings/arm/shmobile.txt
View file @ 2f34a64a
......@@ -51,7 +51,8 @@ SoCs:
compatible = "renesas,r8a77990"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
- RZ/N1D (R9A06G032)
compatible = "renesas,r9a06g032"
Boards:
......@@ -112,6 +113,8 @@ Boards:
compatible = "renesas,porter", "renesas,r8a7791"
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
- RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
......
Documentation/devicetree/bindings/arm/ti/k3.txt 0 → 100644
View file @ 2f34a64a
Texas Instruments K3 Multicore SoC architecture device tree bindings
--------------------------------------------------------------------
Platforms based on Texas Instruments K3 Multicore SoC architecture
shall follow the following scheme:
SoCs
----
Each device tree root node must specify which exact SoC in K3 Multicore SoC
architecture it uses, using one of the following compatible values:
- AM654
compatible = "ti,am654";
Boards
------
In addition, each device tree root node must specify which one or more
of the following board-specific compatible values:
- AM654 EVM
compatible = "ti,am654-evm", "ti,am654";
Documentation/devicetree/bindings/arm/xilinx.txt
View file @ 2f34a64a
......@@ -8,18 +8,38 @@ Required root node properties:
Additional compatible strings:
- Xilinx internal board cc108
- Adapteva Parallella board
"adapteva,parallella"
- Avnet MicroZed board
"avnet,zynq-microzed"
"xlnx,zynq-microzed"
- Avnet ZedBoard board
"avnet,zynq-zed"
"xlnx,zynq-zed"
- Digilent Zybo board
"digilent,zynq-zybo"
- Digilent Zybo Z7 board
"digilent,zynq-zybo-z7"
- Xilinx CC108 internal board
"xlnx,zynq-cc108"
- Xilinx internal board zc770 with different FMC cards
- Xilinx ZC702 internal board
"xlnx,zynq-zc702"
- Xilinx ZC706 internal board
"xlnx,zynq-zc706"
- Xilinx ZC770 internal board, with different FMC cards
"xlnx,zynq-zc770-xm010"
"xlnx,zynq-zc770-xm011"
"xlnx,zynq-zc770-xm012"
"xlnx,zynq-zc770-xm013"
- Digilent Zybo Z7 board
"digilent,zynq-zybo-z7"
---------------------------------------------------------------
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
......
Documentation/devicetree/bindings/clock/at91-clock.txt
View file @ 2f34a64a
......@@ -17,14 +17,13 @@ Required properties:
"atmel,at91sam9x5-clk-slow-rc-osc":
at91 internal slow RC oscillator
"atmel,at91rm9200-pmc" or
"atmel,at91sam9g45-pmc" or
"atmel,at91sam9n12-pmc" or
"atmel,at91sam9x5-pmc" or
"atmel,sama5d3-pmc":
"atmel,<chip>-pmc":
at91 PMC (Power Management Controller)
All at91 specific clocks (clocks defined below) must be child
node of the PMC node.
<chip> can be: at91rm9200, at91sam9260, at91sam9261,
at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9x5,
sama5d2, sama5d3 or sama5d4.
"atmel,at91sam9x5-clk-slow" (under sckc node)
or
......
Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
View file @ 2f34a64a
......@@ -40,6 +40,7 @@ video decode local arbiter, all these ports are according to the video HW.
Required properties:
- compatible : must be one of the following string:
"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
......@@ -50,8 +51,9 @@ Required properties:
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701 and
dt-binding/memory/mt8173-larb-port.h for mt8173
dt-binding/memory/mt2701-larb-port.h for mt2701,
dt-binding/memory/mt2712-larb-port.h for mt2712, and
dt-binding/memory/mt8173-larb-port.h for mt8173.
Example:
iommu: iommu@10205000 {
......
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
View file @ 2f34a64a
......@@ -2,8 +2,9 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
Mediatek SMI have two generations of HW architecture, mt8173 uses the second
generation of SMI HW while mt2701 uses the first generation HW of SMI.
Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
the second generation of SMI HW while mt2701 uses the first generation HW of
SMI.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
......@@ -15,6 +16,7 @@ not needed for SMI generation 2.
Required properties:
- compatible : must be one of :
"mediatek,mt2701-smi-common"
"mediatek,mt2712-smi-common"
"mediatek,mt8173-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
......
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
View file @ 2f34a64a
......@@ -4,8 +4,9 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
Required properties:
- compatible : must be one of :
"mediatek,mt8173-smi-larb"
"mediatek,mt2701-smi-larb"
"mediatek,mt2712-smi-larb"
"mediatek,mt8173-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
......@@ -15,7 +16,7 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
Required property for mt2701:
Required property for mt2701 and mt2712:
- mediatek,larb-id :the hardware id of this larb.
Example:
......
Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
View file @ 2f34a64a
......@@ -16,6 +16,8 @@ Required properties:
* "allwinner,sun9i-a80-mmc"
* "allwinner,sun50i-a64-emmc"
* "allwinner,sun50i-a64-mmc"
* "allwinner,sun50i-h6-emmc", "allwinner.sun50i-a64-emmc"
* "allwinner,sun50i-h6-mmc", "allwinner.sun50i-a64-mmc"
- reg : mmc controller base registers
- clocks : a list with 4 phandle + clock specifier pairs
- clock-names : must contain "ahb", "mmc", "output" and "sample"
......
Documentation/devicetree/bindings/net/dwmac-sun8i.txt
View file @ 2f34a64a
......@@ -19,8 +19,6 @@ Required properties:
- reset-names: must be "stmmaceth"
- phy-mode: See ethernet.txt
- phy-handle: See ethernet.txt
- #address-cells: shall be 1
- #size-cells: shall be 0
- syscon: A phandle to the device containing the EMAC or GMAC clock register
Optional properties:
......@@ -86,8 +84,6 @@ emac: ethernet@1c0b000 {
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
......@@ -137,8 +133,6 @@ emac: ethernet@1c0b000 {
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
......@@ -191,8 +185,6 @@ emac: ethernet@1c0b000 {
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
......
Documentation/devicetree/bindings/sound/mrvl,pxa-ssp.txt
View file @ 2f34a64a
......@@ -17,20 +17,18 @@ Example:
/* upstream device */
ssp0: ssp@41000000 {
ssp1: ssp@41000000 {
compatible = "mrvl,pxa3xx-ssp";
reg = <0x41000000 0x40>;
interrupts = <24>;
clock-names = "pxa27x-ssp.0";
dmas = <&dma 13
&dma 14>;
dma-names = "rx", "tx";
};
/* DAI as user */
ssp_dai0: ssp_dai@0 {
compatible = "mrvl,pxa-ssp-dai";
port = <&ssp0>;
port = <&ssp1>;
#sound-dai-cells = <0>;
};
Documentation/devicetree/bindings/timer/ti,davinci-timer.txt 0 → 100644
View file @ 2f34a64a
* Device tree bindings for Texas Instruments DaVinci timer
This document provides bindings for the 64-bit timer in the DaVinci
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.
The timer is a free running up-counter and can generate interrupts when the
counter reaches preset counter values.
Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
watchdog timers.
Required properties:
- compatible : should be "ti,da830-timer".
- reg : specifies base physical address and count of the registers.
- interrupts : interrupts generated by the timer.
- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
"cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6",
"cmpint7" ("cmpintX" may be omitted if not present in the
hardware).
- clocks : the clock feeding the timer clock.
Example:
clocksource: timer@20000 {
compatible = "ti,da830-timer";
reg = <0x20000 0x1000>;
interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>,
<80>, <81>;
interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1",
"cmpint2", "cmpint3", "cmpint4", "cmpint5",
"cmpint6", "cmpint7";
clocks = <&pll0_auxclk>;
};
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ 2f34a64a
......@@ -142,6 +142,7 @@ geekbuying GeekBuying
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
giantec Giantec Semiconductor, Inc.
giantplus Giantplus Technology Co., Ltd.
globalscale Globalscale Technologies, Inc.
gmt Global Mixed-mode Technology, Inc.
......@@ -200,6 +201,7 @@ koe Kaohsiung Opto-Electronics Inc.
kosagi Sutajio Ko-Usagi PTE Ltd.
kyo Kyocera Corporation
lacie LaCie
laird Laird PLC
lantiq Lantiq Semiconductor
lattice Lattice Semiconductor
lego LEGO Systems A/S
......@@ -279,6 +281,7 @@ opalkelly Opal Kelly Incorporated
opencores OpenCores.org
openrisc OpenRISC.io
option Option NV
oranth Shenzhen Oranth Technology Co., Ltd.
ORCL Oracle Corporation
orisetech Orise Technology
ortustech Ortus Technology Co., Ltd.
......@@ -322,6 +325,7 @@ rohm ROHM Semiconductor Co., Ltd
roofull Shenzhen Roofull Technology Co, Ltd
samsung Samsung Semiconductor
samtec Samtec/Softing company
sancloud Sancloud Ltd
sandisk Sandisk Corporation
sbs Smart Battery System
schindler Schindler
......@@ -401,6 +405,7 @@ upisemi uPI Semiconductor Corp.
urt United Radiant Technology Corporation
usi Universal Scientific Industrial Co., Ltd.
v3 V3 Semiconductor
vamrs Vamrs Ltd.
variscite Variscite Ltd.
via VIA Technologies, Inc.
virtio Virtual I/O Device Specification, developed by the OASIS consortium
......
MAINTAINERS
View file @ 2f34a64a
......@@ -2014,6 +2014,7 @@ S: Supported
F: arch/arm/boot/dts/emev2*
F: arch/arm/boot/dts/r7s*
F: arch/arm/boot/dts/r8a*
F: arch/arm/boot/dts/r9a*
F: arch/arm/boot/dts/sh*
F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S
......@@ -2132,6 +2133,15 @@ L: linux-kernel@vger.kernel.org
S: Maintained
F: drivers/memory/*emif*
ARM/TEXAS INSTRUMENTS K3 ARCHITECTURE
M: Tero Kristo <t-kristo@ti.com>
M: Nishanth Menon <nm@ti.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Supported
F: Documentation/devicetree/bindings/arm/ti/k3.txt
F: arch/arm64/boot/dts/ti/Makefile
F: arch/arm64/boot/dts/ti/k3-*
ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE
M: Santosh Shilimkar <ssantosh@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......
arch/arm/boot/dts/Makefile
View file @ 2f34a64a
......@@ -38,6 +38,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91-ariettag25.dtb \
at91-cosino_mega2560.dtb \
at91-kizboxmini.dtb \
at91-wb45n.dtb \
at91sam9g15ek.dtb \
at91sam9g25ek.dtb \
at91sam9g35ek.dtb \
......@@ -50,7 +51,10 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
at91-dvk_som60.dtb \
at91-gatwick.dtb \
at91-tse850-3.dtb \
at91-wb50n.dtb \
sama5d31ek.dtb \
sama5d33ek.dtb \
sama5d34ek.dtb \
......@@ -73,6 +77,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2835-rpi-b-rev2.dtb \
bcm2835-rpi-b-plus.dtb \
bcm2835-rpi-a-plus.dtb \
bcm2835-rpi-cm1-io1.dtb \
bcm2836-rpi-2-b.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
......@@ -200,6 +205,7 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-dlink-dns-313.dtb \
gemini-nas4220b.dtb \
gemini-rut1xx.dtb \
gemini-sl93512r.dtb \
gemini-sq201.dtb \
gemini-wbd111.dtb \
gemini-wbd222.dtb
......@@ -345,7 +351,8 @@ dtb-$(CONFIG_SOC_IMX27) += \
imx27-phytec-phycore-rdk.dtb \
imx27-phytec-phycard-s-rdk.dtb
dtb-$(CONFIG_SOC_IMX31) += \
imx31-bug.dtb
imx31-bug.dtb \
imx31-lite.dtb
dtb-$(CONFIG_SOC_IMX35) += \
imx35-eukrea-mbimxsd35-baseboard.dtb \
imx35-pdk.dtb
......@@ -358,10 +365,14 @@ dtb-$(CONFIG_SOC_IMX51) += \
imx51-digi-connectcore-jsk.dtb \
imx51-eukrea-mbimxsd51-baseboard.dtb \
imx51-ts4800.dtb \
imx51-zii-rdu1.dtb
imx51-zii-rdu1.dtb \
imx51-zii-scu2-mezz.dtb \
imx51-zii-scu3-esb.dtb
dtb-$(CONFIG_SOC_IMX53) += \
imx53-ard.dtb \
imx53-cx9020.dtb \
imx53-kp-ddc.dtb \
imx53-kp-hsc.dtb \
imx53-m53evk.dtb \
imx53-mba53.dtb \
imx53-ppd.dtb \
......@@ -400,6 +411,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-hummingboard2-emmc-som-v15.dtb \
imx6dl-hummingboard2-som-v15.dtb \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
imx6dl-mamoj.dtb \
imx6dl-nit6xlite.dtb \
......@@ -521,6 +533,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-nitrogen6sx.dtb \
imx6sx-sabreauto.dtb \
......@@ -533,6 +547,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-udoo-neo-full.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-ccimx6ulsbcexpress.dtb \
imx6ul-geam.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
......@@ -567,8 +582,10 @@ dtb-$(CONFIG_SOC_VF610) += \
vf610-cosmic.dtb \
vf610m4-cosmic.dtb \
vf610-twr.dtb \
vf610-zii-cfu1.dtb \
vf610-zii-dev-rev-b.dtb \
vf610-zii-dev-rev-c.dtb
vf610-zii-dev-rev-c.dtb \
vf610-zii-ssmb-spu3.dtb
dtb-$(CONFIG_ARCH_MXS) += \
imx23-evk.dtb \
imx23-olinuxino.dtb \
......@@ -695,10 +712,12 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-pepper.dtb \
am335x-phycore-rdk.dtb \
am335x-pocketbeagle.dtb \
am335x-sancloud-bbe.dtb \
am335x-shc.dtb \
am335x-sbc-t335.dtb \
am335x-sl50.dtb \
am335x-wega-rdk.dtb
am335x-wega-rdk.dtb \
am335x-osd3358-sm-red.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \
omap4-droid4-xt894.dtb \
omap4-duovero-parlor.dtb \
......@@ -819,6 +838,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
r9a06g032-rzn1d400-db.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-evb.dtb \
......@@ -859,6 +879,8 @@ dtb-$(CONFIG_ARCH_S3C64XX) += \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-aquila.dtb \
s5pv210-fascinate4g.dtb \
s5pv210-galaxys.dtb \
s5pv210-goni.dtb \
s5pv210-smdkc110.dtb \
s5pv210-smdkv210.dtb \
......@@ -1039,7 +1061,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
tango4-vantage-1172.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-harmony.dtb \
tegra20-iris-512.dtb \
tegra20-colibri-iris.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
tegra20-plutux.dtb \
......@@ -1109,6 +1131,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
zynq-zybo.dtb \
zynq-zybo-z7.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \
......@@ -1138,6 +1161,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-388-clearfog-pro.dtb \
armada-388-db.dtb \
armada-388-gp.dtb \
armada-388-helios4.dtb \
armada-388-rd.dtb
dtb-$(CONFIG_MACH_ARMADA_39X) += \
armada-398-db.dtb
......@@ -1168,7 +1192,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623a-rfb-emmc.dtb \
mt7623a-rfb-nand.dtb \
mt7623n-rfb-emmc.dtb \
mt7623n-rfb-nand.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
......
arch/arm/boot/dts/am335x-baltos.dtsi
View file @ 2f34a64a
......@@ -396,7 +396,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <7 IRQ_TYPE_EDGE_RISING>;
};
};
......
arch/arm/boot/dts/am335x-evm.dts
View file @ 2f34a64a
......@@ -778,7 +778,7 @@ wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
};
};
......
arch/arm/boot/dts/am335x-evmsk.dts
View file @ 2f34a64a
......@@ -690,7 +690,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio0>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */
ref-clock-frequency = <38400000>;
};
};
......
arch/arm/boot/dts/am335x-osd3358-sm-red.dts 0 → 100755
View file @ 2f34a64a
This diff is collapsed.
arch/arm/boot/dts/am335x-sancloud-bbe.dts 0 → 100644
View file @ 2f34a64a
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
#include "am335x-boneblack-common.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "SanCloud BeagleBone Enhanced";
compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
};
&am33xx_pinmux {
pinctrl-names = "default";
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
usb_hub_ctrl: usb_hub_ctrl {
pinctrl-single,pins = <
AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLUP | MUX_MODE7) /* rmii1_refclk.gpio0_29 */
>;
};
mpu6050_pins: pinmux_mpu6050_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE7) /* uart0_ctsn.gpio1_8 */
>;
};
lps3331ap_pins: pinmux_lps3331ap_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */
>;
};
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
};
&i2c0 {
lps331ap: barometer@5c {
compatible = "st,lps331ap-press";
st,drdy-int-pin = <1>;
reg = <0x5c>;
interrupt-parent = <&gpio1>;
interrupts = <26 IRQ_TYPE_EDGE_RISING>;
};
mpu6050: accelerometer@68 {
compatible = "invensense,mpu6050";
reg = <0x68>;
interrupt-parent = <&gpio0>;
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
orientation = <0xff 0 0 0 1 0 0 0 0xff>;
};
usb2512b: usb-hub@2c {
compatible = "microchip,usb2512b";
reg = <0x2c>;
reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
/* wifi on port 4 */
};
};
arch/arm/boot/dts/am335x-sl50.dts
View file @ 2f34a64a
This diff is collapsed.
arch/arm/boot/dts/am33xx.dtsi
View file @ 2f34a64a
......@@ -29,8 +29,8 @@ aliases {
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
d_can0 = &dcan0;
d_can1 = &dcan1;
d-can0 = &dcan0;
d-can1 = &dcan1;
usb0 = &usb0;
usb1 = &usb1;
phy0 = &usb0_phy;
......
arch/arm/boot/dts/am3517-evm.dts
View file @ 2f34a64a
......@@ -127,6 +127,7 @@ lcd0: display@0 {
status = "okay";
pinctrl-names = "default";
enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */
vcc-supply = <&vdd_io_reg>;
port {
lcd_in: endpoint {
......@@ -154,6 +155,7 @@ panel-timing {
bl: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
power-supply = <&vdd_io_reg>;
pinctrl-0 = <&backlight_pins>;
pwms = <&pwm11 0 5000000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
......@@ -168,6 +170,13 @@ pwm11: dmtimer-pwm@11 {
ti,timers = <&timer11>;
#pwm-cells = <3>;
};
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
#phy-cells = <0>;
};
};
&davinci_emac {
......@@ -203,6 +212,7 @@ tca6416: gpio@21 {
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&vdd_io_reg>;
};
};
......@@ -220,15 +230,21 @@ &mmc1 {
cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */
};
&mmc2 {
&mmc3 {
status = "disabled";
};
&mmc3 {
status = "disabled";
&usbhshost {
port1-mode = "ehci-phy";
};
&usbhsehci {
phys = <&hsusb1_phy>;
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_rst_pins>;
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
......@@ -287,4 +303,32 @@ OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
>;
};
hsusb1_rst_pins: pinmux_hsusb1_rst_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_pins>;
hsusb1_pins: pinmux_hsusb1_pins {
pinctrl-single,pins = <
OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3) /* etk_d8.hsusb1_dir */
OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3) /* etk_d9.hsusb1_nxt */
OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3) /* etk_d0.hsusb1_data0 */
OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3) /* etk_d1.hsusb1_data1 */
OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3) /* etk_d2.hsusb1_data2 */
OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3) /* etk_d7.hsusb1_data3 */
OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3) /* etk_d4.hsusb1_data4 */
OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3) /* etk_d5.hsusb1_data5 */
OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3) /* etk_d6.hsusb1_data6 */
OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3) /* etk_d3.hsusb1_data7 */
>;
};
};
arch/arm/boot/dts/am3517-som.dtsi
View file @ 2f34a64a
......@@ -14,6 +14,32 @@ cpu@0 {
cpu0-supply = <&vdd_core_reg>;
};
};
wl12xx_buffer: wl12xx_buf {
compatible = "regulator-fixed";
regulator-name = "wl1271_buf";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_buffer_pins>;
gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
regulator-always-on;
vin-supply = <&vdd_1v8_reg>;
};
wl12xx_vmmc2: wl12xx_vmmc2 {
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_wkup_pins>;
gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
startup-delay-us = <70000>;
enable-active-high;
regulator-always-on;
vin-supply = <&wl12xx_buffer>;
};
};
&gpmc {
......@@ -64,7 +90,6 @@ tps: tps65023@48 {
regulators {
vdd_core_reg: VDCDC1 {
regulator-name = "vdd_core";
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
......@@ -72,7 +97,6 @@ vdd_core_reg: VDCDC1 {
vdd_io_reg: VDCDC2 {
regulator-name = "vdd_io";
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
......@@ -80,7 +104,6 @@ vdd_io_reg: VDCDC2 {
vdd_1v8_reg: VDCDC3 {
regulator-name = "vdd_1v8";
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......@@ -88,7 +111,6 @@ vdd_1v8_reg: VDCDC3 {
vdd_usb18_reg: LDO1 {
regulator-name = "vdd_usb18";
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......@@ -96,7 +118,6 @@ vdd_usb18_reg: LDO1 {
vdd_usb33_reg: LDO2 {
regulator-name = "vdd_usb33";
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
......@@ -126,8 +147,63 @@ touchscreen: tsc2004@4b {
};
};
&mmc2 {
interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&wl12xx_vmmc2>;
non-removable;
bus-width = <4>;
cap-power-off-card;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */
ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
bluetooth {
compatible = "ti,wl1271-st";
enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */
max-speed = <3000000>;
};
};
&omap3_pmx_core {
wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */
OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
rtc_pins: pinmux_rtc_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
......@@ -139,4 +215,23 @@ tsc2004_pins: pinmux_tsc2004_pins {
OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */
OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */
>;
};
};
&omap3_pmx_wkup {
wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
>;
};
};
arch/arm/boot/dts/am437x-gp-evm.dts
View file @ 2f34a64a
......@@ -790,7 +790,7 @@ wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio1>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_EDGE_RISING>;
};
};
......
arch/arm/boot/dts/am571x-idk.dts
View file @ 2f34a64a
......@@ -66,10 +66,6 @@ mmc0-led {
};
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&extcon_usb2 {
id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
......
arch/arm/boot/dts/am572x-idk-common.dtsi
View file @ 2f34a64a
......@@ -57,10 +57,6 @@ mmc0-led {
};
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&extcon_usb2 {
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
......
arch/arm/boot/dts/am57xx-idk-common.dtsi
View file @ 2f34a64a
......@@ -395,8 +395,13 @@ &usb1 {
dr_mode = "host";
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&usb2 {
dr_mode = "peripheral";
extcon = <&extcon_usb2>;
dr_mode = "otg";
};
&mmc1 {
......
arch/arm/boot/dts/armada-388-clearfog-base.dts
View file @ 2f34a64a
......@@ -3,11 +3,6 @@
* Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828)
*
* Copyright (C) 2015 Russell King
*
* This board is in development; the contents of this file work with
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
*/
/dts-v1/;
......
arch/arm/boot/dts/armada-388-clearfog-pro.dts
View file @ 2f34a64a
......@@ -3,11 +3,6 @@
* Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
*
* Copyright (C) 2015 Russell King
*
* This board is in development; the contents of this file work with
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
*/
#include "armada-388-clearfog.dts"
......
arch/arm/boot/dts/armada-388-clearfog.dts
View file @ 2f34a64a
......@@ -3,11 +3,6 @@
* Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
*
* Copyright (C) 2015 Russell King
*
* This board is in development; the contents of this file work with
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
*/
/dts-v1/;
......@@ -235,7 +230,7 @@ rear_button_pins: rear-button-pins {
&spi1 {
/*
* Add SPI CS pins for clearfog:
* CS0: W25Q32 (not populated on uSOM)
* CS0: W25Q32
* CS1:
* CS2: mikrobus
*/
......
arch/arm/boot/dts/armada-388-clearfog.dtsi
View file @ 2f34a64a
......@@ -3,11 +3,6 @@
* Device Tree include file for SolidRun Clearfog 88F6828 based boards
*
* Copyright (C) 2015 Russell King
*
* This board is in development; the contents of this file work with
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
*/
#include "armada-388.dtsi"
......@@ -230,7 +225,7 @@ mikro_uart_pins: mikro-uart-pins {
&spi1 {
/*
* Add SPI CS pins for clearfog:
* CS0: W25Q32 (not populated on uSOM)
* CS0: W25Q32
* CS1: PIC microcontroller (Pro models)
* CS2: mikrobus
*/
......
arch/arm/boot/dts/armada-388-helios4.dts 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Helios4
* based on SolidRun Clearfog revision A1 rev 2.0 (88F6828)
*
* Copyright (C) 2017 Aditya Prayoga <aditya@kobol.io>
*
*/
/dts-v1/;
#include "armada-388.dtsi"
#include "armada-38x-solidrun-microsom.dtsi"
/ {
model = "Helios4";
compatible = "kobol,helios4", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
};
aliases {
/* So that mvebu u-boot can update the MAC addresses */
ethernet1 = &eth0;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_12v: regulator-12v {
compatible = "regulator-fixed";
regulator-name = "power_brick_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&reg_12v>;
};
reg_5p0v_hdd: regulator-5v-hdd {
compatible = "regulator-fixed";
regulator-name = "5V_HDD";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&reg_12v>;
};
reg_5p0v_usb: regulator-5v-usb {
compatible = "regulator-fixed";
regulator-name = "USB-PWR";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
enable-active-high;
gpio = <&expander0 6 GPIO_ACTIVE_HIGH>;
vin-supply = <&reg_12v>;
};
system-leds {
compatible = "gpio-leds";
status-led {
label = "helios4:green:status";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
default-state = "on";
};
fault-led {
label = "helios4:red:fault";
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
};
io-leds {
compatible = "gpio-leds";
sata1-led {
label = "helios4:green:ata1";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "ata1";
default-state = "off";
};
sata2-led {
label = "helios4:green:ata2";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
linux,default-trigger = "ata2";
default-state = "off";
};
sata3-led {
label = "helios4:green:ata3";
gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
linux,default-trigger = "ata3";
default-state = "off";
};
sata4-led {
label = "helios4:green:ata4";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,default-trigger = "ata4";
default-state = "off";
};
usb-led {
label = "helios4:green:usb";
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usb-host";
default-state = "off";
};
};
fan1: j10-pwm {
compatible = "pwm-fan";
pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */
};
fan2: j17-pwm {
compatible = "pwm-fan";
pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */
};
usb2_phy: usb2-phy {
compatible = "usb-nop-xceiv";
vbus-regulator = <&reg_5p0v_usb>;
};
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
};
soc {
internal-regs {
i2c@11000 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-Board Revision bit 0 #
* 1-Board Revision bit 1 #
* 5-USB3 overcurrent
* 6-USB3 power
*/
expander0: gpio-expander@20 {
/*
* This is how it should be:
* compatible = "onnn,pca9655",
* "nxp,pca9555";
* but you can't do this because of
* the way I2C works.
*/
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pca0_pins>;
interrupt-parent = <&gpio0>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
board_rev_bit_0 {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "board-rev-0";
};
board_rev_bit_1 {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
input;
line-name = "board-rev-1";
};
usb3_ilimit {
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
input;
line-name = "usb-overcurrent-status";
};
};
temp_sensor: temp@4c {
compatible = "ti,lm75";
reg = <0x4c>;
vcc-supply = <&reg_3p3v>;
};
};
i2c@11100 {
/*
* External I2C Bus for user peripheral
*/
clock-frequency = <400000>;
pinctrl-0 = <&helios_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
sata@a8000 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
};
sata1: sata-port@1 {
reg = <1>;
};
};
sata@e0000 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
sata2: sata-port@0 {
reg = <0>;
};
sata3: sata-port@1 {
reg = <1>;
};
};
spi@10680 {
pinctrl-0 = <&spi1_pins
&microsom_spi1_cs_pins>;
pinctrl-names = "default";
status = "okay";
};
sdhci@d8000 {
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
pinctrl-0 = <&helios_sdhci_pins
&helios_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
vmmc = <&reg_3p3v>;
wp-inverted;
};
usb@58000 {
usb-phy = <&usb2_phy>;
status = "okay";
};
usb3@f0000 {
status = "okay";
};
usb3@f8000 {
status = "okay";
};
pinctrl@18000 {
pca0_pins: pca0-pins {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
microsom_phy0_int_pins: microsom-phy0-int-pins {
marvell,pins = "mpp18";
marvell,function = "gpio";
};
helios_i2c1_pins: i2c1-pins {
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
helios_sdhci_cd_pins: helios-sdhci-cd-pins {
marvell,pins = "mpp20";
marvell,function = "gpio";
};
helios_sdhci_pins: helios-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
helios_led_pins: helios-led-pins {
marvell,pins = "mpp24", "mpp25",
"mpp49", "mpp50",
"mpp52", "mpp53",
"mpp54";
marvell,function = "gpio";
};
helios_fan_pins: helios-fan-pins {
marvell,pins = "mpp41", "mpp43",
"mpp48", "mpp55";
marvell,function = "gpio";
};
microsom_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp59";
marvell,function = "spi1";
};
};
};
};
};
arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
View file @ 2f34a64a
......@@ -3,11 +3,6 @@
* Device Tree file for SolidRun Armada 38x Microsom
*
* Copyright (C) 2015 Russell King
*
* This board is in development; the contents of this file work with
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
......@@ -99,7 +94,6 @@ w25q32: spi-flash@0 {
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
status = "disabled";
};
};
......
arch/arm/boot/dts/aspeed-ast2500-evb.dts
View file @ 2f34a64a
......@@ -80,20 +80,20 @@ lm75@4d {
};
};
&ehci0 {
/*
* Enable port A as device (via the virtual hub) and port B as
* host by default on the eval board. This can be easily changed
* by replacing the override below with &ehci0 { ... } to enable
* host on both ports.
*/
&vhub {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ah_default>;
};
&ehci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2bh_default>;
};
&uhci {
status = "okay";
/* No pinctrl, this follows the above EHCI settings */
};
arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
View file @ 2f34a64a
......@@ -21,9 +21,9 @@ reserved-memory {
#size-cells = <1>;
ranges;
vga_memory: framebuffer@bf000000 {
vga_memory: framebuffer@9f000000 {
no-map;
reg = <0xbf000000 0x01000000>; /* 16M */
reg = <0x9f000000 0x01000000>; /* 16M */
};
flash_memory: region@98000000 {
......
arch/arm/boot/dts/aspeed-g4.dtsi
View file @ 2f34a64a
......@@ -92,6 +92,12 @@ vic: interrupt-controller@1e6c0080 {
reg = <0x1e6c0080 0x80>;
};
cvic: copro-interrupt-controller@1e6c2000 {
compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
valid-sources = <0x7fffffff>;
reg = <0x1e6c2000 0x80>;
};
mac0: ethernet@1e660000 {
compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
......@@ -113,6 +119,8 @@ ehci0: usb@1e6a1000 {
reg = <0x1e6a1000 0x100>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2h_default>;
status = "disabled";
};
......@@ -123,6 +131,20 @@ uhci: usb@1e6b0000 {
#ports = <3>;
clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
status = "disabled";
/*
* No default pinmux, it will follow EHCI, use an explicit pinmux
* override if you don't enable EHCI
*/
};
vhub: usb-vhub@1e6a0000 {
compatible = "aspeed,ast2400-usb-vhub";
reg = <0x1e6a0000 0x300>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2d_default>;
status = "disabled";
};
apb {
......@@ -161,7 +183,7 @@ adc: adc@1e6e9000 {
status = "disabled";
};
sram@1e720000 {
sram: sram@1e720000 {
compatible = "mmio-sram";
reg = <0x1e720000 0x8000>; // 32K
};
......@@ -224,7 +246,7 @@ pwm_tacho: pwm-tacho-controller@1e786000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1e786000 0x1000>;
clocks = <&syscon ASPEED_CLK_APB>;
clocks = <&syscon ASPEED_CLK_24M>;
resets = <&syscon ASPEED_RESET_PWM>;
status = "disabled";
};
......
arch/arm/boot/dts/aspeed-g5.dtsi
View file @ 2f34a64a
......@@ -127,6 +127,13 @@ vic: interrupt-controller@1e6c0080 {
reg = <0x1e6c0080 0x80>;
};
cvic: copro-interrupt-controller@1e6c2000 {
compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
valid-sources = <0xffffffff>;
copro-sw-interrupts = <1>;
reg = <0x1e6c2000 0x80>;
};
mac0: ethernet@1e660000 {
compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
reg = <0x1e660000 0x180>;
......@@ -148,6 +155,8 @@ ehci0: usb@1e6a1000 {
reg = <0x1e6a1000 0x100>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ah_default>;
status = "disabled";
};
......@@ -156,6 +165,8 @@ ehci1: usb@1e6a3000 {
reg = <0x1e6a3000 0x100>;
interrupts = <13>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2bh_default>;
status = "disabled";
};
......@@ -166,6 +177,20 @@ uhci: usb@1e6b0000 {
#ports = <2>;
clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
status = "disabled";
/*
* No default pinmux, it will follow EHCI, use an explicit pinmux
* override if you don't enable EHCI
*/
};
vhub: usb-vhub@1e6a0000 {
compatible = "aspeed,ast2500-usb-vhub";
reg = <0x1e6a0000 0x300>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
status = "disabled";
};
apb {
......@@ -211,7 +236,7 @@ adc: adc@1e6e9000 {
status = "disabled";
};
sram@1e720000 {
sram: sram@1e720000 {
compatible = "mmio-sram";
reg = <0x1e720000 0x9000>; // 36K
};
......@@ -281,7 +306,7 @@ pwm_tacho: pwm-tacho-controller@1e786000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1e786000 0x1000>;
clocks = <&syscon ASPEED_CLK_APB>;
clocks = <&syscon ASPEED_CLK_24M>;
resets = <&syscon ASPEED_RESET_PWM>;
status = "disabled";
};
......@@ -1417,6 +1442,11 @@ pinctrl_usb2ah_default: usb2ah_default {
groups = "USB2AH";
};
pinctrl_usb2ad_default: usb2ad_default {
function = "USB2AD";
groups = "USB2AD";
};
pinctrl_usb11bhid_default: usb11bhid_default {
function = "USB11BHID";
groups = "USB11BHID";
......
arch/arm/boot/dts/at91-dvk_som60.dts 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-dvk_som60.dts - Device Tree file for the DVK SOM60 board
*
* Copyright (C) 2018 Laird,
* 2018 Ben Whitten <ben.whitten@lairdtech.com>
*
*/
/dts-v1/;
#include "at91-som60.dtsi"
#include "at91-dvk_su60_somc.dtsi"
#include "at91-dvk_su60_somc_lcm.dtsi"
/ {
model = "Laird DVK SOM60";
compatible = "laird,dvk-som60", "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
chosen {
stdout-path = &dbgu;
tick-timer = &pit;
};
};
&mmc0 {
status = "okay";
};
&spi0 {
status = "okay";
};
&ssc0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&usart1 {
status = "okay";
};
&usart2 {
status = "okay";
};
&usart3 {
status = "okay";
};
&uart0 {
status = "okay";
};
&dbgu {
status = "okay";
};
&pit {
status = "okay";
};
&adc0 {
status = "okay";
};
&can1 {
status = "okay";
};
&macb0 {
status = "okay";
};
&macb1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
arch/arm/boot/dts/at91-dvk_su60_somc.dtsi 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-dvk_su60_somc.dtsi - Device Tree file for the DVK SOM60 base board
*
* Copyright (C) 2018 Laird,
* 2018 Ben Whitten <ben.whitten@lairdtech.com>
*
*/
/ {
sound {
compatible = "atmel,asoc-wm8904";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck2_as_audio_mck>;
atmel,model = "wm8904 @ DVK-SOM60";
atmel,audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Mic", "MICBIAS",
"IN1L", "Mic";
atmel,ssc-controller = <&ssc0>;
atmel,audio-codec = <&wm8904>;
status = "okay";
};
};
&mmc0 {
status = "okay";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
slot@0 {
bus-width = <4>;
cd-gpios = <&pioE 31 GPIO_ACTIVE_HIGH>;
cd-inverted;
};
};
&spi0 {
status = "okay";
/* spi0.0: 4M Flash Macronix MX25R4035FM1IL0 */
spi-flash@0 {
compatible = "mxicy,mx25u4035", "jedec,spi-nor";
spi-max-frequency = <33000000>;
reg = <0>;
};
};
&ssc0 {
atmel,clk-from-rk-pin;
status = "okay";
};
&i2c0 {
status = "okay";
wm8904: wm8904@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
clocks = <&pck2>;
clock-names = "mclk";
};
};
&i2c1 {
status = "okay";
eeprom@87 {
compatible = "giantec,gt24c32a", "atmel,24c32";
reg = <87>;
pagesize = <32>;
};
};
&usart1 {
status = "okay";
};
&usart2 {
status = "okay";
};
&usart3 {
status = "okay";
};
&uart0 {
status = "okay";
};
&dbgu {
status = "okay";
};
&pit {
status = "okay";
};
&adc0 {
status = "okay";
};
&can1 {
status = "okay";
};
&macb0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ethernet-phy@7 {
reg = <7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_geth_int>;
interrupt-parent = <&pioB>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
txen-skew-ps = <800>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <400>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <400>;
rxd1-skew-ps = <400>;
rxd2-skew-ps = <400>;
rxd3-skew-ps = <400>;
};
};
&macb1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ethernet-phy@1 {
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eth_int>;
interrupt-parent = <&pioC>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
};
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-dvk_su60_somc_lcm.dtsi - Device Tree file for the DVK SOM60 LCD board
*
* Copyright (C) 2018 Laird,
* 2018 Ben Whitten <ben.whitten@lairdtech.com>
*
*/
/ {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&hlcdc_pwm 0 50000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
panel: panel {
compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc_lcd_reg>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
panel_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&hlcdc_panel_output>;
};
};
};
vcc_lcd_reg: fixedregulator_lcd {
compatible = "regulator-fixed";
regulator-name = "VCC LCM";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
status = "okay";
};
};
&pinctrl {
board {
pinctrl_lcd_ctp_int: lcd_ctp_int {
atmel,pins =
<AT91_PIOC 28 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
&i2c1 {
status = "okay";
ft5426@56 {
compatible = "focaltech,ft5426", "edt,edt-ft5406";
reg = <56>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_ctp_int>;
interrupt-parent = <&pioC>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
};
&hlcdc {
status = "okay";
hlcdc-display-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
port@0 {
hlcdc_panel_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
};
};
arch/arm/boot/dts/at91-gatwick.dts 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-gatwick.dts - Device Tree file for the Gatwick board
*
* Copyright (C) 2018 Laird
*
*/
/dts-v1/;
#include "at91-wb50n.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Laird Workgroup Bridge 50N - Project Gatwick";
compatible = "laird,gatwick", "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
gpio_keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
reset-button {
label = "Reset Button";
linux,code = <KEY_SETUP>;
gpios = <&pioE 31 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
ethernet {
label = "gatwick:yellow:ethernet";
gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wifi {
label = "gatwick:green:wifi";
gpios = <&pioA 28 GPIO_ACTIVE_LOW>;
default-state = "off";
};
ble {
label = "gatwick:blue:ble";
gpios = <&pioA 22 GPIO_ACTIVE_LOW>;
default-state = "off";
};
lora {
label = "gatwick:orange:lora";
gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
default-state = "off";
};
blank {
label = "gatwick:green:blank";
gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
default-state = "off";
};
user {
label = "gatwick:yellow:user";
gpios = <&pioA 12 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
};
&pinctrl {
board {
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pullup deglitch */
};
};
};
&mmc0 {
status = "okay";
};
&macb1 {
status = "okay";
};
&dbgu {
status = "okay";
};
/* FTDI USART */
&usart0 {
status = "okay";
};
/* GPS USART */
&usart1 {
pinctrl-0 = <&pinctrl_usart1>;
status = "okay";
};
&spi1 {
status = "okay";
spidev@0 {
compatible = "semtech,sx1301";
reg = <0>;
spi-max-frequency = <8000000>;
};
};
&usb1 {
status = "okay";
/delete-property/atmel,oc-gpio;
};
&usb2 {
status = "okay";
};
arch/arm/boot/dts/at91-som60.dtsi 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-som60.dtsi - Device Tree file for the SOM60 module
*
* Copyright (C) 2018 Laird,
* 2018 Ben Whitten <ben.whitten@lairdtech.com>
*
*/
#include "sama5d36.dtsi"
/ {
model = "Laird SOM60";
compatible = "laird,som60", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
chosen {
stdout-path = &dbgu;
};
memory {
reg = <0x20000000 0x8000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
};
&pinctrl {
board {
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_mmc0_en: mmc0_en {
atmel,pins =
<AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_nand0_wp: nand0_wp {
atmel,pins =
<AT91_PIOE 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_usb_vbus: usb_vbus {
atmel,pins =
<AT91_PIOE 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
/* Conflicts with USART2_SCK */
};
pinctrl_usart2_sck: usart2_sck {
atmel,pins =
<AT91_PIOE 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
/* Conflicts with USB_VBUS */
};
pinctrl_usb_oc: usb_oc {
atmel,pins =
<AT91_PIOE 15 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
/* Conflicts with USART3_SCK */
};
pinctrl_usart3_sck: usart3_sck {
atmel,pins =
<AT91_PIOE 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
/* Conflicts with USB_OC */
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins =
<AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_geth_int: geth_int {
atmel,pins =
<AT91_PIOB 25 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
/* Conflicts with USART1_SCK */
};
pinctrl_usart1_sck: usart1_sck {
atmel,pins =
<AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
/* Conflicts with GETH_INT */
};
pinctrl_eth_int: eth_int {
atmel,pins =
<AT91_PIOC 10 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_pck2_as_audio_mck: pck2_as_audio_mck {
atmel,pins =
<AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
};
&mmc0 {
slot@0 {
reg = <0>;
bus-width = <8>;
};
};
&mmc1 {
status = "okay";
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
&spi0 {
cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
};
&usart0 {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>;
};
&usart1 {
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
};
&usart2 {
pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts_cts>;
};
&usart3 {
pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>;
};
&adc0 {
pinctrl-0 = <
&pinctrl_adc0_adtrg
&pinctrl_adc0_ad0
&pinctrl_adc0_ad1
&pinctrl_adc0_ad2
&pinctrl_adc0_ad3
&pinctrl_adc0_ad4
&pinctrl_adc0_ad5
>;
};
&macb0 {
phy-mode = "rgmii";
};
&macb1 {
phy-mode = "rmii";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_nand_addr>;
pinctrl-names = "default";
status = "okay";
};
&nand_controller {
status = "okay";
nand: nand@3 {
reg = <0x3 0x0 0x2>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
ubootspl@0 {
label = "u-boot-spl";
reg = <0x0 0x20000>;
};
uboot@20000 {
label = "u-boot";
reg = <0x20000 0x80000>;
};
ubootenv@a0000 {
label = "u-boot-env";
reg = <0xa0000 0x20000>;
};
ubootenv@c0000 {
label = "u-boot-env";
reg = <0xc0000 0x20000>;
};
ubi@e0000 {
label = "ubi";
reg = <0xe0000 0xfe00000>;
};
};
};
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
atmel,vbus-gpio = <&pioC 14 GPIO_ACTIVE_HIGH>;
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_vbus &pinctrl_usb_oc>;
num-ports = <3>;
atmel,vbus-gpio = <0
&pioE 20 GPIO_ACTIVE_HIGH
0>;
atmel,oc-gpio = <0
&pioE 15 GPIO_ACTIVE_LOW
0>;
};
arch/arm/boot/dts/at91-wb45n.dts 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-wb45n.dts - Device Tree file for WB45NBT board
*
* Copyright (C) 2018 Laird
*
*/
/dts-v1/;
#include "at91-wb45n.dtsi"
/ {
model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)";
compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9";
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
irqbtn@18 {
reg = <18>;
label = "IRQBTN";
linux,code = <99>;
gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
gpio-key,wakeup = <1>;
};
};
};
&watchdog {
status = "okay";
};
&usb0 {
status = "okay";
};
&mmc0 {
status = "okay";
};
&spi0 {
status = "okay";
};
&macb0 {
status = "okay";
};
&dbgu {
status = "okay";
};
&usart0 {
status = "okay";
};
&usart3 {
status = "okay";
};
&i2c1 {
status = "okay";
};
arch/arm/boot/dts/at91-wb45n.dtsi 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-wb45n.dtsi - Device Tree file for WB45NBT board
*
* Copyright (C) 2018 Laird
*
*/
#include "at91sam9g25.dtsi"
/ {
model = "Laird Workgroup Bridge 45N - Atmel AT91SAM (dt)";
compatible = "laird,wb45n", "laird,wbxx", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x4000000>;
};
atheros {
compatible = "atheros,ath6kl";
atheros,board-id = "SD32";
};
};
&reset_controller {
compatible = "atmel,sama5d3-rstc";
};
&shutdown_controller {
atmel,wakeup-mode = "low";
};
&slow_xtal {
clock-frequency = <32768>;
};
&main_xtal {
clock-frequency = <12000000>;
};
&ebi {
status = "okay";
nand_controller: nand-controller {
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb &pinctrl_nand_oe_we>;
pinctrl-names = "default";
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bs";
reg = <0x0 0x20000>;
};
uboot@20000 {
label = "u-boot";
reg = <0x20000 0x80000>;
};
ubootenv@a0000 {
label = "u-boot-env";
reg = <0xa0000 0x20000>;
};
ubootenv@c0000 {
label = "redund-env";
reg = <0xc0000 0x20000>;
};
kernel-a@e0000 {
label = "kernel-a";
reg = <0xe0000 0x280000>;
};
kernel-b@360000 {
label = "kernel-b";
reg = <0x360000 0x280000>;
};
rootfs-a@5e0000 {
label = "rootfs-a";
reg = <0x5e0000 0x2600000>;
};
rootfs-b@2be0000 {
label = "rootfs-b";
reg = <0x2be0000 0x2600000>;
};
user@51e0000 {
label = "user";
reg = <0x51e0000 0x2dc0000>;
};
logs@7fa0000 {
label = "logs";
reg = <0x7fa0000 0x60000>;
};
};
};
};
};
&usb0 {
num-ports = <2>;
atmel,vbus-gpio = <
&pioB 12 GPIO_ACTIVE_HIGH
&pioA 31 GPIO_ACTIVE_HIGH
>;
atmel,oc-gpio = <&pioB 13 GPIO_ACTIVE_LOW>;
};
&macb0 {
phy-mode = "rmii";
};
&spi0 {
cs-gpios = <&pioA 14 0>, <&pioA 7 0>, <0>, <0>;
};
&usb2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_board_usb2>;
atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
};
&mmc0 {
pinctrl-0 = <
&pinctrl_mmc0_slot0_clk_cmd_dat0
&pinctrl_mmc0_slot0_dat1_3>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
&pinctrl {
usb2 {
pinctrl_board_usb2: usb2-board {
atmel,pins =
<AT91_PIOB 11 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB11 gpio vbus sense, deglitch */
};
};
};
arch/arm/boot/dts/at91-wb50n.dts 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-wb50n.dts - Device Tree file for wb50n evaluation board
*
* Copyright (C) 2018 Laird
*
*/
/dts-v1/;
#include "at91-wb50n.dtsi"
/ {
model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
btn0@10 {
reg = <10>;
label = "BTNESC";
linux,code = <1>; /* ESC button */
gpios = <&pioA 10 GPIO_ACTIVE_LOW>;
gpio-key,wakeup = <1>;
};
irqbtn@31 {
reg = <31>;
label = "IRQBTN";
linux,code = <99>; /* SysReq button */
gpios = <&pioE 31 GPIO_ACTIVE_LOW>;
gpio-key,wakeup = <1>;
};
};
leds {
compatible = "gpio-leds";
led0 {
label = "wb50n:blue:led0";
gpios = <&pioA 12 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led1 {
label = "wb50n:green:led1";
gpios = <&pioA 24 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led2 {
label = "wb50n:red:led2";
gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
};
&watchdog {
status = "okay";
};
&mmc0 {
status = "okay";
};
&macb1 {
status = "okay";
};
&dbgu {
status = "okay";
};
/* On BB40 this port is labeled UART1 */
&usart0 {
status = "okay";
};
/* On BB40 this port is labeled UART0 */
&usart1 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&spi1 {
status = "okay";
spidev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <8000000>;
};
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
arch/arm/boot/dts/at91-wb50n.dtsi 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/*
* at91-wb50n.dtsi - Device Tree include file for wb50n cpu module
*
* Copyright (C) 2018 Laird
*
*/
#include "sama5d31.dtsi"
/ {
model = "Laird Workgroup Bridge 50N - Atmel SAMA5D";
compatible = "laird,wb50n", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
chosen {
bootargs = "ubi.mtd=6 root=ubi0:rootfs rootfstype=ubifs rw";
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x4000000>;
};
};
&pinctrl {
board {
pinctrl_mmc0_cd: mmc0_cd {
atmel,pins = <AT91_PIOC 26 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PC26 GPIO with pullup deglitch */
};
pinctrl_usba_vbus: usba_vbus {
atmel,pins = <AT91_PIOB 13 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB13 GPIO with deglitch */
};
};
};
&slow_xtal {
clock-frequency = <32768>;
};
&main_xtal {
clock-frequency = <12000000>;
};
&slow_osc {
atmel,osc-bypass;
};
&usart1_clk {
atmel,clk-output-range = <0 132000000>;
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
cd-gpios = <&pioC 26 GPIO_ACTIVE_LOW>;
slot@0 {
reg = <0>;
bus-width = <4>;
};
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
status = "okay";
atheros@0 {
compatible = "atheros,ath6kl";
atheros,board-id = "SD32";
reg = <0>;
bus-width = <4>;
};
};
&macb1 {
phy-mode = "rmii";
};
&dbgu {
dmas = <0>, <0>; /* Do not use DMA for dbgu */
};
/* On BB40 this port is labeled UART1 */
&usart0 {
atmel,use-dma-rx;
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>;
};
/* On BB40 this port is labeled UART0 */
&usart1 {
atmel,use-dma-rx;
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
dtr-gpios = <&pioD 13 GPIO_ACTIVE_LOW>;
dsr-gpios = <&pioD 11 GPIO_ACTIVE_LOW>;
dcd-gpios = <&pioD 7 GPIO_ACTIVE_LOW>;
rng-gpios = <&pioD 8 GPIO_ACTIVE_LOW>;
};
/* USART3 is direct-connect to the Bluetooth UART on the radio SIP */
&usart3 {
atmel,use-dma-rx;
atmel,use-dma-tx;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usart3 &pinctrl_usart3_rts_cts>;
status = "okay";
};
&spi1 {
cs-gpios = <&pioC 25 0>, <0>, <0>, <0>;
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_nand_addr>;
pinctrl-names = "default";
status = "okay";
};
&nand_controller {
status = "okay";
nand: nand@3 {
reg = <0x3 0x0 0x2>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bs";
reg = <0x0 0x20000>;
};
uboot@20000 {
label = "u-boot";
reg = <0x20000 0x80000>;
};
ubootenv@a0000 {
label = "u-boot-env";
reg = <0xa0000 0x20000>;
};
ubootenv@c0000 {
label = "u-boot-env";
reg = <0xc0000 0x20000>;
};
kernel-a@e0000 {
label = "kernel-a";
reg = <0xe0000 0x500000>;
};
kernel-b@5e0000 {
label = "kernel-b";
reg = <0x5e0000 0x500000>;
};
rootfs-a@ae0000 {
label = "rootfs-a";
reg = <0xae0000 0x3000000>;
};
rootfs-b@3ae0000 {
label = "rootfs-b";
reg = <0x3ae0000 0x3000000>;
};
user@6ae0000 {
label = "user";
reg = <0x6ae0000 0x14e0000>;
};
};
};
};
&usb0 {
atmel,vbus-gpio = <&pioB 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA 2 GPIO_ACTIVE_LOW>;
atmel,oc-gpio = <&pioA 4 GPIO_ACTIVE_LOW>;
};
arch/arm/boot/dts/at91sam9261.dtsi
View file @ 2f34a64a
......@@ -590,7 +590,7 @@ pioC: gpio@fffff800 {
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc", "syscon";
compatible = "atmel,at91sam9261-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
......
arch/arm/boot/dts/at91sam9263.dtsi
View file @ 2f34a64a
......@@ -93,7 +93,7 @@ aic: interrupt-controller@fffff000 {
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc", "syscon";
compatible = "atmel,at91sam9263-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
......
arch/arm/boot/dts/at91sam9rl.dtsi
View file @ 2f34a64a
......@@ -832,7 +832,7 @@ pioD: gpio@fffffa00 {
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9g45-pmc", "syscon";
compatible = "atmel,at91sam9rl-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
interrupt-controller;
......
arch/arm/boot/dts/at91sam9x5.dtsi
View file @ 2f34a64a
......@@ -389,13 +389,13 @@ ssc0_clk: ssc0_clk {
};
};
rstc@fffffe00 {
reset_controller: rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32k>;
};
shdwc@fffffe10 {
shutdown_controller: shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
clocks = <&clk32k>;
......@@ -470,7 +470,7 @@ dma1: dma-controller@ffffee00 {
clock-names = "dma_clk";
};
pinctrl@fffff400 {
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
......@@ -1206,7 +1206,7 @@ ep@6 {
};
};
watchdog@fffffe40 {
watchdog: watchdog@fffffe40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
......
arch/arm/boot/dts/bcm-cygnus.dtsi
View file @ 2f34a64a
......@@ -41,6 +41,10 @@ / {
model = "Broadcom Cygnus SoC";
interrupt-parent = <&gic>;
aliases {
ethernet0 = &eth0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
......@@ -417,6 +421,11 @@ spi2: spi@1802a000 {
status = "disabled";
};
rng: rng@18032000 {
compatible = "brcm,iproc-rng200";
reg = <0x18032000 0x28>;
};
sdhci0: sdhci@18041000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x18041000 0x100>;
......
arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2835-rpi-cm1.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
compatible = "raspberrypi,compute-module", "brcm,bcm2835";
model = "Raspberry Pi Compute Module IO board rev1";
};
&gpio {
/*
* This is based on the official GPU firmware DT blob.
*
* Legend:
* "NC" = not connected (no rail from the SoC)
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "GPIO0",
"GPIO1",
"GPIO2",
"GPIO3",
"GPIO4",
"GPIO5",
"GPIO6",
"GPIO7",
"GPIO8",
"GPIO9",
"GPIO10",
"GPIO11",
"GPIO12",
"GPIO13",
"GPIO14",
"GPIO15",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"GPIO28",
"GPIO29",
"GPIO30",
"GPIO31",
"GPIO32",
"GPIO33",
"GPIO34",
"GPIO35",
"GPIO36",
"GPIO37",
"GPIO38",
"GPIO39",
"GPIO40",
"GPIO41",
"GPIO42",
"GPIO43",
"GPIO44",
"GPIO45",
"HDMI_HPD_N",
/* Also used as ACT LED */
"EMMC_EN_N",
/* Used by eMMC */
"SD_CLK_R",
"SD_CMD_R",
"SD_DATA0_R",
"SD_DATA1_R",
"SD_DATA2_R",
"SD_DATA3_R";
pinctrl-0 = <&gpioout &alt0>;
};
&hdmi {
hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio14>;
status = "okay";
};
arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi 0 → 100644
View file @ 2f34a64a
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
/ {
leds {
act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
reg_3v3: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_1v8: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
};
&sdhost {
non-removable;
vmmc-supply = <&reg_3v3>;
vqmmc-supply = <&reg_1v8>;
};
arch/arm/boot/dts/bcm2837.dtsi
View file @ 2f34a64a
......@@ -17,6 +17,12 @@ local_intc: local_intc@40000000 {
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&local_intc>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&local_intc>;
......
arch/arm/boot/dts/bcm283x.dtsi
View file @ 2f34a64a
......@@ -66,6 +66,12 @@ timer@7e003000 {
clock-frequency = <1000000>;
};
txp@7e004000 {
compatible = "brcm,bcm2835-txp";
reg = <0x7e004000 0x20>;
interrupts = <1 11>;
};
dma: dma@7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xf00>;
......
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
View file @ 2f34a64a
......@@ -90,3 +90,7 @@ wps {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts
View file @ 2f34a64a
......@@ -80,3 +80,7 @@ rfkill {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
View file @ 2f34a64a
......@@ -146,3 +146,7 @@ &usb3 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts
View file @ 2f34a64a
......@@ -38,3 +38,7 @@ restart {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
View file @ 2f34a64a
......@@ -57,3 +57,7 @@ restart {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
View file @ 2f34a64a
......@@ -64,3 +64,7 @@ restart {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View file @ 2f34a64a
......@@ -91,3 +91,7 @@ &usb3 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
View file @ 2f34a64a
......@@ -83,3 +83,7 @@ restart {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
View file @ 2f34a64a
......@@ -158,3 +158,7 @@ port@5 {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
View file @ 2f34a64a
......@@ -74,3 +74,7 @@ wps {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
View file @ 2f34a64a
......@@ -118,3 +118,7 @@ eject {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
View file @ 2f34a64a
......@@ -104,3 +104,7 @@ restart {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
View file @ 2f34a64a
......@@ -57,3 +57,7 @@ restart {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
View file @ 2f34a64a
......@@ -105,3 +105,7 @@ &usb2 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
View file @ 2f34a64a
......@@ -99,3 +99,7 @@ &spi_nor {
&usb2 {
vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
View file @ 2f34a64a
......@@ -62,3 +62,7 @@ restart {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
View file @ 2f34a64a
......@@ -127,3 +127,7 @@ &usb2 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
View file @ 2f34a64a
......@@ -39,3 +39,7 @@ restart {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4709-netgear-r7000.dts
View file @ 2f34a64a
......@@ -101,3 +101,7 @@ &usb2 {
&usb3 {
vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4709-netgear-r8000.dts
View file @ 2f34a64a
......@@ -182,3 +182,7 @@ &usb2 {
&usb3 {
vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
View file @ 2f34a64a
......@@ -104,3 +104,7 @@ &usb3 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
View file @ 2f34a64a
......@@ -115,3 +115,7 @@ &usb3 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47094-linksys-panamera.dts
View file @ 2f34a64a
......@@ -31,5 +31,238 @@ wps {
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
};
rfkill {
label = "WiFi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
};
reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
wps {
label = "bcm53xx:white:wps";
gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>;
};
usb2 {
label = "bcm53xx:green:usb2";
gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port2>, <&ehci_port2>;
linux,default-trigger = "usbport";
};
usb3 {
label = "bcm53xx:green:usb3";
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>,
<&xhci_port1>;
linux,default-trigger = "usbport";
};
power {
label = "bcm53xx:white:power";
gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
};
wifi-disabled {
label = "bcm53xx:amber:wifi-disabled";
gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
};
wifi-enabled {
label = "bcm53xx:white:wifi-enabled";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
};
bluebar1 {
label = "bcm53xx:white:bluebar1";
gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
};
bluebar2 {
label = "bcm53xx:white:bluebar2";
gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
};
bluebar3 {
label = "bcm53xx:white:bluebar3";
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
};
bluebar4 {
label = "bcm53xx:white:bluebar4";
gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
};
bluebar5 {
label = "bcm53xx:white:bluebar5";
gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>;
};
bluebar6 {
label = "bcm53xx:white:bluebar6";
gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>;
};
bluebar7 {
label = "bcm53xx:white:bluebar7";
gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>;
};
bluebar8 {
label = "bcm53xx:white:bluebar8";
gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
};
};
mdio-bus-mux {
/* BIT(9) = 1 => external mdio */
mdio_ext: mdio@200 {
reg = <0x200>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mdio-mii-mux {
compatible = "mdio-mux-mmioreg";
mdio-parent-bus = <&mdio_ext>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1800c1c0 0x4>;
/* BIT(6) = mdc, BIT(7) = mdio */
mux-mask = <0xc0>;
mdio-mii@0 {
/* Enable MII function */
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
compatible = "brcm,bcm53125";
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
reset-names = "robo_reset";
reg = <0>;
dsa,member = <1 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan5";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan6";
};
port@4 {
reg = <4>;
label = "lan3";
};
sw1_p8: port@8 {
reg = <8>;
ethernet = <&sw0_p0>;
label = "cpu";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
};
};
&usb2 {
vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
};
&usb3 {
vcc-gpio = <&chipcommon 14 GPIO_ACTIVE_HIGH>;
};
&srab {
compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab";
status = "okay";
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan7";
};
port@2 {
reg = <2>;
label = "lan4";
};
port@3 {
reg = <3>;
label = "lan8";
};
port@4 {
reg = <4>;
label = "wan";
};
port@8 {
reg = <8>;
ethernet = <&gmac2>;
label = "cpu";
fixed-link {
speed = <1000>;
full-duplex;
};
};
sw0_p0: port@0 {
reg = <0>;
label = "extsw";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
View file @ 2f34a64a
......@@ -60,3 +60,7 @@ &usb3 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
View file @ 2f34a64a
......@@ -60,3 +60,7 @@ &usb3 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
View file @ 2f34a64a
......@@ -100,3 +100,7 @@ &usb3 {
&spi_nor {
status = "okay";
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47094-netgear-r8500.dts
View file @ 2f34a64a
......@@ -91,3 +91,7 @@ rfkill {
};
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm47094.dtsi
View file @ 2f34a64a
......@@ -7,9 +7,10 @@
#include "bcm4708.dtsi"
/ {
usb3_phy: usb3-phy {
compatible = "brcm,ns-bx-usb3-phy";
};
};
&usb3_phy {
compatible = "brcm,ns-bx-usb3-phy";
};
&uart0 {
......
arch/arm/boot/dts/bcm5301x.dtsi
View file @ 2f34a64a
......@@ -154,13 +154,6 @@ usb2_phy: usb2-phy {
clock-names = "phy-ref-clk";
};
usb3_phy: usb3-phy {
compatible = "brcm,ns-ax-usb3-phy";
reg = <0x18105000 0x1000>, <0x18003000 0x1000>;
reg-names = "dmp", "ccb-mii";
#phy-cells = <0>;
};
axi@18000000 {
compatible = "brcm,bus-axi";
reg = <0x18000000 0x1000>;
......@@ -359,7 +352,33 @@ mdio: mdio@18003000 {
reg = <0x18003000 0x8>;
#size-cells = <1>;
#address-cells = <0>;
status = "disabled";
};
mdio-bus-mux {
compatible = "mdio-mux-mmioreg";
mdio-parent-bus = <&mdio>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x18003000 0x4>;
mux-mask = <0x200>;
mdio@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
usb3_phy: usb3-phy@10 {
compatible = "brcm,ns-ax-usb3-phy";
reg = <0x10>;
usb3-dmp-syscon = <&usb3_dmp>;
#phy-cells = <0>;
status = "disabled";
};
};
};
usb3_dmp: syscon@18105000 {
reg = <0x18105000 0x1000>;
};
i2c0: i2c@18009000 {
......
arch/arm/boot/dts/bcm53573.dtsi
View file @ 2f34a64a
......@@ -48,6 +48,14 @@ gic: interrupt-controller@1000 {
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm/boot/dts/bcm94708.dts
View file @ 2f34a64a
......@@ -42,3 +42,7 @@ memory {
reg = <0x00000000 0x08000000>;
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm94709.dts
View file @ 2f34a64a
......@@ -42,3 +42,7 @@ memory {
reg = <0x00000000 0x08000000>;
};
};
&usb3_phy {
status = "okay";
};
arch/arm/boot/dts/bcm953012er.dts
View file @ 2f34a64a
......@@ -90,3 +90,7 @@ port@5 {
};
};
};
&usb3_phy {
status = "okay";
};
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