Commit 2fa9b361 authored by Yixun Lan's avatar Yixun Lan Committed by Jerome Brunet

clk: meson: axg: fix the od shift of the sys_pll

According to the datasheet, the od shift of sys_pll is actually 16.

Fixes: 78b4af31 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: default avatarYixun Lan <yixun.lan@amlogic.com>
[fixed commit message]
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent 6b71acec
...@@ -64,7 +64,7 @@ static struct meson_clk_pll axg_sys_pll = { ...@@ -64,7 +64,7 @@ static struct meson_clk_pll axg_sys_pll = {
}, },
.od = { .od = {
.reg_off = HHI_SYS_PLL_CNTL, .reg_off = HHI_SYS_PLL_CNTL,
.shift = 10, .shift = 16,
.width = 2, .width = 2,
}, },
.lock = &meson_clk_lock, .lock = &meson_clk_lock,
......
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